JPH01215066A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration by arranging a conductor layer composed of one layer or two or more of these layers of combination in a high melting- point metal or an silicide or a nitride thereof on a contact section of a diffusion layer under a second wiring layer. CONSTITUTION:An insulating film 4 is formed onto the surface of a P-type semiconductor substrate 1, and a gate electrode layer consisting of a polycide layer is shaped. A resist pattern 12 is formed onto an insulating film 5 shaped onto the gate electrode layer 7, and the insulating film 5 is removed through reactive etching. A gate electrode 3 is formed through reactive etching, and the pattern 12 is gotten rid of. An N<-> layer is shaped through ion implantation, using the gate electrode 3 as a mask. An inter-layer insulating film 6a formed on the whole surface on the gate electrode 3, and sidewalls 6 are shaped on the sidewalls of the gate electrode 3 through reactive etching. An N<+> layer is formed by employing ion implantation. An inter-layer insulating film 10 is shaped, one parts of the insulating film 5 and the sidewall 6 are taken off through etching, and an opening section 9 is formed. Conductor layers 13 made up of multilayers composed of a high melting-point metal or these silicide or nitride are shaped, and a wiring layer 8 is formed onto the layers 13. Accordingly, the degree of integration can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention is applicable to semiconductor devices, particularly LDDs (Lightly Devices).
The present invention relates to a structure of a MOS type semiconductor device having a doped drain structure, a mask ROM using the same, and a integrated Vi circuit using the mask ROM.

[Conventional technology]

The structure and manufacturing process of a conventional MOS type semiconductor device will be explained using -.

6 and 7 show a conventional structure and a connecting part, 1 is a substrate of the first conductivity type, 2 is a diffusion layer of the second conductivity type, and 2a is a low concentration region of the diffusion layer. , 2b is a region with a high concentration of the diffusion layer, 3 is a gate electrode, 4 is a gate insulating film, 5 is an interlayer insulating film, 6 is a side wall, 7 is a first wiring layer, and 8 is a second wiring layer. , 9 are connection parts (contact parts).

In the LDD structure, as shown in FIG. 4, the diffusion layer 2 of the second conductivity type consists of a region 2a with a low concentration and a region 2b with a high concentration. The channel length can be secured without diffusion spreading under the train 4, and since this region 2a makes the resistance of this part higher than that of the region 2b, the electric field generated near the drain is relaxed, and this electric field causes the inside of the gate insulating film near the train to be It is suitable for miniaturization because it can suppress the so-called hot carrier phenomenon, which is the deterioration of transistor characteristics such as threshold value that occurs when carriers are injected and captured.

The manufacturing method is shown in FIG. 8(a) to FIG. 8(e).
is formed on the gate insulating film 4, then a low concentration diffusion region 2a is formed as shown in FIG. 8(b), and then a diffusion region 2a with a low concentration is formed as shown in FIG.
Glabellar insulation l to form sidewalls as shown
B16a and then anisotropically etched the eighth
(d) Form the sidewall 6 as shown in the figure, then the 8th
(e) As shown in the figure, a highly concentrated diffusion region 2b is formed, and the above is the method for forming the LDD structure.

[The problem that the invention seeks to solve]

The problems with the conventional MO8 type semiconductor device as described above are as follows.
The following points can be mentioned.

(1) As shown in FIG. 7, the connecting portion 9 between the two layers has conventionally formed a hole-shaped opening, but photolithography is required to prevent short-circuiting between the opening 9 and the metal of the first wiring layer 7. A combination margin a was required. This has been a bottleneck in achieving high integration, as the margin a is determined by the capability of the exposure device, and can therefore simply be made smaller.

(2) For the same reason as in the previous section, for the combination allowance a,
The length of the second wiring layer 8 cannot be reduced, and the propagation delay due to this resistance makes it impossible to increase the speed.

(3) For the same reason as in the above (1), the parasitic diffusion capacitance is not reduced due to the combinational margin a, and high speed cannot be achieved.

These problems are particularly noticeable in read-only memories, so-called mask ROMs, in which data is written during the process, and integrated circuits containing the same, and have been a major reason for the inability to integrate them as the capacity increases.

The present invention is a semiconductor device and a mask RO that solves such problems.
An object of the present invention is to provide an integrated circuit incorporating a mask ROM and a mask ROM.

[Means to solve the problem]

The present invention relates to a MOS type semiconductor device having an LDD structure, in which a diffusion layer of a second conductivity type formed on a substrate of a first conductivity type and a polycrystalline silicon, a high melting point metal, a silicide, or the polycrystalline silicon. A first wiring layer made of polycide made of a combination of and the high melting point metal or the silicide, and a second wiring layer made of polycrystalline silicon, the high melting point metal, silicide, polycide, metal, etc., and the diffusion layer and A connecting portion of the second wiring layer is adjacent to a gate electrode portion of the first wiring layer having the LDD structure, and the second wiring layer intersects with the first wiring layer at this portion. In the structure, the opening of the connection portion between the second wiring layer and the diffusion layer is formed larger than the boundary between the silicon surface of the diffusion layer and the sidewall insulating film of the electrode portion. In the semiconductor device, at least a layer of a high melting point metal, a silicide of the high melting point metal, a nitride of the high melting point metal, or a layer thereof is provided in a contact portion of the diffusion layer under the second wiring layer. A semiconductor device is characterized in that a conductor layer is arranged, which is a combination of two or more layers, and further, in a connection portion between the diffusion layer and the second wiring layer, the silicon surface of the diffusion layer is 'J4 is larger than the width of the second wiring layer.
The present invention is a semiconductor device characterized by a characteristic semiconductor device, a mask ROM characterized by being composed of this diagonal conductor device, and an integrated circuit characterized by using this mask R-OM.

[For production]

In the conventional method, the first layer wiring spacing is 1 as shown in Figure 7.
It becomes +2a. Here, the size a of the opening between the first wiring layers is the alignment margin.However, in the method of the present invention, there is no need to provide alignment margin, and the minimum wiring spacing that is subject to processing restrictions as shown in FIG. 2 is sufficient.

For example, the line width and interval of the first layer are respectively 1.2 μm and 1.2 μm.
2μm, alignment margin a is 1.0μm, j is 1.2μm, conventional method: j +2a = (1,2+1.0X2)μ
m = 3.2 μm, method of the present invention = 1.2 μm, and in the case of the present invention, the thickness is about half or less than that of the conventional method.

Since the semiconductor device of the present invention is constructed as described above, the chip area can be reduced, and the diffusion area of the source or drain diffusion layer is reduced accordingly, thereby reducing parasitics. Similarly, the wiring length of the second layer is shortened by this amount, the wiring resistance is reduced, the propagation delay is reduced, and high-speed conversion cost can be reduced.

〔Example〕

An example in which an embodiment of the present invention is applied to an N-channel MOSFET will be described.

FIG. 1 and FIG. 2 are explanatory diagrams of a semiconductor device of the present invention and its connection parts, respectively.

In the southern countries, the same symbols as those in Figures 6 to 8 are the same.
In FIG. 0, which shows a corresponding portion and will not be described repeatedly, 5 is an insulating film between the eyebrows selectively formed on the second wiring layer 3, and 11 is a gate electrode in the opening 9. This is the sidewall insulating film of No. 13. 13 is a conductor layer arranged between the first and second wiring layers.

In Fig. 1, 1 is a P- region formed on a P' type semiconductor substrate or an N- type semiconductor substrate made of silicon single crystal, 2 is an N'' type diffusion layer, and 2a is a low concentration diffusion layer. In the layer, 2b is a high concentration diffusion layer.3 is the first wiring metal, which is a high melting point metal such as polycrystalline silicon MO, W, etc., or Mo5t.
, WSi, TiSi, or the like is used, and is shown as a gate electrode portion in FIG. 4 is an insulating film such as 8102 formed on the substrate 1 which is mainly used as a gate insulating film, and 5 is a glabellar insulating film such as 5i02 or Si's N4 selectively provided on the first wiring 3. As a result, the first and second wiring layers are separated, and if an opening as shown in FIG. 2 is simply formed using conventional techniques, the two wiring layers will be short-circuited on the gate t@3. Therefore, the formation of this interlayer insulation WA5 is the first point of the present invention, and this point will be explained in the embodiment of the manufacturing method described later.Also, this film 5 is formed by thermal oxidation or CVD method or CVD method. An insulating film such as 3i3N4 formed by a method is used. Reference numeral 6 denotes a side wall provided by anisotropic etching mainly on both sides of the first wiring M3, and in the gate electrode part, it is used as a source and a drain. It is used to further isolate the pair of semiconductor regions used and to ensure a sufficient effective channel length.

Further, 10 is an insulating film between the eyebrows of the first wiring layer and the second wiring layer, and 11 is a side wall of the gate electrode 3 in the opening that makes contact between the first wiring layer and the second wiring WA8. This sidewall insulating film is an insulating film formed on the upper part of the gate insulating film 4 by anisotropic etching.
The sidewall of the DDm structure is formed by the same mechanism as the sidewall when forming the opening (9 in FIG. 2) by anisotropic etching the sidewall and the interlayer insulating film 10. It will be done! This is a sidewall insulating film formed in combination with a 1N insulating film, and the difference between these is explained by overetching during etching of the opening. In other words, if the over-etching is long, the interlayer insulating film 10 will be completely etched even on the rm wall of the gate electrode 3, and the sidewall insulating film 11 will become only the sidewall. Conversely, if the amount of etching is reduced, the second state will occur.

Reference numeral 13 denotes a conductor layer formed between the first wiring and the second wiring and made of a combination of one or two of a high melting point metal, a silicide thereof, or a nitride thereof. As shown in the figure, the second wiring layer is S such as AL.
In the case of a metal that easily reacts with L at low temperatures, the metal such as AL forms a diffusion layer 2-a or 2a near the boundary between the sidewall insulating film 11 and the Si surface (arrowed part in the figure) due to heat treatment of the second wiring layer. Therefore, a diagonal conductor layer 13 is formed to prevent this from penetrating through the boundary between and 2b. This conductor layer is made of Ti,
Refractory metals such as W and MO, their silicides, or nitrides are suitable; scraps or a combination of two or more of these metals may be used; this conductor layer may be formed entirely under the second wiring layer. Alternatively, it may be formed only on the Si surface of the connecting portion between the first and second interconnection layers.On the other hand, this also reduces the contact resistance of the connecting portion of the first and second wiring layers. be able to.

Furthermore, if the conductor layer 13 has a high etching selectivity with respect to the second wiring layer (for example, the second wiring layer is Poly-Si and the conductor layer is MOSt), as shown in FIG.
) When the wiring width of the second wiring layer 8 is smaller than that of the Si surface in the opening 9 as shown in (b), when the second wiring layer is etched, the Si surface is etched and a groove is formed. , This prevents problems such as AL disconnection.

(14 is an element isolation insulating film.) As shown in FIG. 1, the semiconductor device of the present invention has the following features: (1) As shown in FIG. This is formed to be larger than the boundary between the sidewall or the sidewall insulating film 11, and as a result, there is no margin for alignment based on design rules.

However, although the alignment margin a can be eliminated on the pattern, there is still a misalignment between the first wiring layer 7 and the opening 9 formed by photolithography. The actual contact area within the opening 9 becomes smaller and the contact resistance increases. Therefore, by making the opening 9 reach the top of the first layer wiring 1m7, this misalignment can be avoided. did it.

(2) If a structure like the above (1) is introduced in a conventional process, the first and second wiring layers will be short-circuited.

Therefore, isolation is achieved by selectively forming an insulator [5] only on the first wiring layer.

(3) Also, on the side surface of the first wiring layer, it is separated from the second wiring layer in a self-aligned manner by a sidewall or a sidewall insulating film 11.

(4) Further, at the connection portion between the second wiring layer and the diffusion layer, there is provided a conductor layer between them, which is made of a combination of one or two layers of a high melting point metal, a silicide thereof, or a nitride thereof.

etc., which is different from conventional devices.

Next, an embodiment of the method for manufacturing a semiconductor device of the present invention will be described based on FIGS. 3<a) to 3(j!').

In the figure, 12 is a photoresist pattern.

The method for manufacturing a semiconductor device of the present invention is as follows: (1) First, as shown in FIG. 3(a), after forming a gate insulating film 4 on the surface of a p-type semiconductor substrate 1, High loan agreement 1! J! Alternatively, a gate electrode layer (IXjI matrix fa layer 7) of a polycide layer made of a combination of these two is formed.

(2) Next, as shown in FIG. 3(b), an insulation WA5 is formed on the gate electrode layer 7 by CVD. (In this case, the gate electrode 7 layer may be subjected to oxidation heat treatment, etc., and 3i02, Si3 Na is used as the film.) -(3) As shown in FIG. 3(c), a photoresist pattern is formed on the insulating film 5. form 12.

(4) As shown in Figure 3(d), reactive etching (R
IE) to remove the insulating film 5 by etching.
As shown in FIG. 3(e), gate ′! :h%3 and photoresist 1-
Remove pattern 12.

(5) As shown in FIG. 3(f), the gate voltage f! 3 as a mask, an n- layer (low concentration diffusion layer 2a) is formed by ion implantation of P+ or As+ into the base plate 1.

(6) As shown in FIG. 3(g), an F-inter insulating film 6a is formed over the entire surface of the gate electrode 3 by CVD.

This insulating film uses SiO2 or Si3N4.

(7) As shown in FIG. 3(h), the entire surface is etched away by reactive etching to form sidewalls 6 on the sidewalls of the gate electrodes 3.

(8) Next, as shown in FIG. 3(i), 31
An n layer (dense diffusion layer 2b) is formed using P1 or As+ ion implantation.

(9) As shown in FIG. 3(j), a glabellar insulating film 10 is formed by CVD. This film is 5i02 or Si3N4
Use.

(10) As shown in FIG. 3(k), the interlayer insulating film 10
A part of the glabellar insulating film 5 and the sidewall 6 under a predetermined portion of is removed by etching to form the sidewall 11 and the opening 9 of the connection part.

At this time, the etching conditions for the interlayer insulating film 5, the overetching layer when forming the sidewall 6, the interlayer insulating film 10, and the opening of the connection part are as follows! By adjusting the insulation film 5 or 11 between the first wiring layer N7 and the second wiring layer 8 to a minimum thickness of 500 Å or more, leakage between the two can be prevented and a breakdown voltage can be ensured. .

(11) After fi, as shown in Figure 3 (1), MOLW
A multilayer conductor layer consisting of one or a combination of two or more conductor layers made of a high melting point metal such as , Ti, silicide, or nitride of these is formed by sputtering or CVD, and then A second wiring layer is formed.

At this time, when forming this conductor layer on the entire surface under the second wiring layer, the formation of the conductor layer and the formation of the second wiring layer are performed continuously, and after the resist pattern is formed, the etching and etching of the second wiring layer are performed. This structure can be formed by etching the conductor layer in one step or in two steps. At the same time, it is also possible to improve resistance to electromigration.

On the other hand, when forming a conductor layer only between or near the Si surface of the second wiring layer and the diffusion layer, the conductor layer is formed on the entire surface in the state shown in Fig. 3 (k), and the former is only formed on the Si surface by heat treatment. There is a method of siliciding and then selectively etching to form a silicide film only on the Si surface, and this can be done by using Ti or the like. In the latter case, the structure of the present invention can be realized by forming a resist pattern only in the necessary part after forming the conductor layer on the same machine, etching that part, and then forming the second layer wiring 8 by the conventional method. MA S K ROM using this, also this MA
An integrated circuit with built-in S K ROM has been realized.

In the embodiments of the present invention, an example of an N-channel transistor formed in a P- region on a P-type substrate or an N-substrate has been described; Needless to say, the present invention can also be applied to P-channel transistors formed in

〔Effect of the invention〕

By using the structure of the semiconductor device of the present invention, (1)
Since the alignment margin can be removed, the interval between the first wirings becomes smaller, so that higher density can be achieved.

(2) Since the length of the second layer wiring can be shortened, wiring resistance can be reduced and wiring delay can be reduced.

(3) Since the area of the diffusion layer was reduced, it was possible to reduce the capacitance of the diffusion layer and the parasitic capacitance of the second layer wiring, thereby optimizing the yield.

(4) The overall chip area became smaller, the number of effective chips in the same unit increased, and costs were reduced.

The above-mentioned speed-up and cost-reduction in particular became possible without metal penetration or processing problems, which had a great effect.

In particular, regarding the chip area, using the example described in [Function], in LM bi MASK ROM, one direction in the CBLL portion is 2.0 μ x 1000 = 20
00μ was able to be reduced.

Furthermore, this effect also makes it possible to reduce the area of the ROM portion of an integrated circuit incorporating a ROM.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams of the semiconductor device of the present invention and its connection parts, FIGS. 3(a) to (j) are detailed explanatory diagrams of the present invention, and FIGS. 4 and 5 (a). )(b) is an explanatory diagram of the necessity of the structure of the present invention, FIGS. 6 and 7 are explanatory diagrams of the structure and connection parts of a conventional semiconductor device, and FIG. 8(a) is an explanatory diagram of the necessity of the structure of the present invention.
-(e) are explanatory diagrams of the LDD structure. 1...Si substrate 2...Diffusion layer 2a...Low concentration diffusion layer 2b...High concentration diffusion layer 3...Gate electrode portion 4 of first wiring layer...Day 1~ Insulating film 5...Insulating film 6 formed only on the first interconnect layer...Side wall 6a...Insulating film 7 for forming the side wall...First interconnect layer 8...・Second wiring layer 9...Connection part 10...Glabella insulating film 11 between the first and second wirings...Side wall insulating film 12...Photoresist 13...Conductor layer 14... - Element isolation insulating film Note that the same reference numerals in the figures indicate the same or equivalent parts. Applicant: Seiko Epson Corporation

Claims (2)

[Claims] (1) A MOS semiconductor device having an LDD structure, in which a diffusion layer of a second conductivity type formed on a substrate of a first conductivity type, polycrystalline silicon, a high melting point metal, silicide, or the polycrystalline silicon is formed on a substrate of a first conductivity type. A first wiring layer made of polycide made of a high melting point metal or a combination with the silicide, and a second wiring layer made of polycrystalline silicon, a high melting point metal, silicide, polycide, metal, etc. The connection part of the second wiring layer corresponds to L.
In a structure in which the second wiring layer is adjacent to the gate electrode portion made of the first wiring layer having a DD structure and the second wiring layer intersects the first wiring layer at this portion, the second wiring layer and the first wiring layer are adjacent to each other. A semiconductor device characterized in that the opening of the connection portion with the diffusion layer is formed larger than the boundary between the silicon surface of the diffusion layer and the sidewall insulating film of the electrode portion. A conductor layer made of a refractory metal, a silicide of the refractory metal, or a nitride of the refractory metal, or a combination of two or more of these layers, is provided at the contact portion of the diffusion layer under the second wiring layer. A semiconductor device comprising: (2) The semiconductor device according to item 1, wherein at a connection portion between the diffusion layer and the second wiring layer, a silicon surface of the diffusion layer is larger than a width of the second wiring layer.