KR19990086618A - How to form a trench - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a trench for isolation between devices on a silicon substrate, wherein a trench oxide is formed after forming a liner oxide film on a trench inner side and a pad oxide film on a silicon substrate, and forming a stacked oxide oxide The nitride film portion stacked on the substrate is removed. Then, by annealing these silicon oxides at different temperatures, the strain and defects of the silicon oxide are reduced to reduce the etching rate, thereby preventing the silicon oxide on the trench side from being etched simultaneously during the etching of the pad oxide film of the silicon substrate. .

Description

How to form a trench

The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for forming a trench on a semiconductor substrate.

In the fabrication of a semiconductor integrated circuit, a process of separating a semiconductor substrate into an active region where a semiconductor element and the substrate are connected, and a region different from the device region by a field oxide dielectric material is required.

Field oxide dielectric material generally means silicon oxide film. Although various field oxide film formation methods have been developed and proposed, in general, LOCOS (Localized oxidation of Silicon) method is widely used. In the LOCOS method, an element region of a semiconductor substrate is masked using a silicon nitride film as a mask, and a field oxide region is formed as a field dielectric region by a thermal oxidation method or the like. This LOCOS method has the effect of simple process, but there is a problem that the efficiency of the final produced semiconductor is reduced.

One of the biggest reasons for the efficiency deterioration in the LOCOS method is a bird beak phenomenon, i.e., a field oxide region penetrates under the masking silicon nitride film, thereby reducing the usable device region. Another problem encountered in forming field oxide films is that stresses induced by deviations from the edges of the device regions and relative unplanarization with adjacent field layers are caused. The unplanarized region in the element region causes deterioration of the gate oxide film, that is, the formation of a conductive layer for the remaining region becomes difficult. Although a method for solving such a problem has been proposed, there is a problem in that the proposed method causes a complicated process and a price increase.

In order to solve this problem, another separation method, that is, a trench separation method, has been proposed.

In the trench isolation method, as shown in FIG. 1A, a trench 4 is formed by etching a predetermined area of the silicon substrate 3 on which the pad oxide film 1 and the nitride film 2 are formed, by a predetermined depth or more, and forming the trench inner side surface. After forming a liner oxide 5 in the silicon oxide, silicon oxide or the like is deposited in the trench 4 to separate device regions. Compared to the LOCOS method, such a trench isolation method is easy to integrate and does not generate a bird big phenomenon.

On the other hand, after the device region is separated by the trench isolation method, it is necessary to remove the nitride film and the pad oxide film of the separated device regions. In this case, the etching rate of the silicon oxides in the trench is faster than that of the liner oxide film. There is a problem that the bonding between the liner oxide film and the gate oxide film is incomplete. That is, in the case of nicking the pad oxide film as shown in FIG. 1B, the etching rate of the oxide 5 in the trench 4, which is usually formed by isotropic wet etching and is formed by a chemical vapor deposition method, or the like. Is faster than the pad oxide film 1, the liner oxide film 5 is etched at the same time as the side of the trench 4 is deeply etched as shown in FIG. Here, FIG. 1C is a detailed cross-sectional view detailing part A of FIG. 1B.

In this situation, when the gate oxide film and the like are stacked on the silicon substrate, the gate oxide film 6 stacked on the side of the etched trench 4 as shown in FIG. 1D is formed on the top of the silicon substrate 3. In addition, since the thin layer is laminated, the junction between the liner oxide film 5 on the side of the trench 4 and the gate oxide film 6 is incomplete, which may cause junction leakage.

In order to solve this problem, a method of annealing the silicon oxide in the trench 4 has been proposed. In other words, by reducing the strain and defects of the silicon oxide through the annealing it is possible to slow down the etching rate to solve the above problems. For this purpose, the silicon oxide was annealed at 900 to 1000 ° C. for 30 to 40 minutes. However, through the conventional method, the etching rate of the silicon oxide in the trench is high, resulting in incomplete bonding between the side of the trench 4 and the liner oxide film 5. It doesn't effectively prevent things from happening.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a trench formation method capable of reducing the etching rate of silicon oxide in the trench in contact with the liner oxide film and the gate oxide film.

In order to achieve the above object, the present invention provides a method for forming a trench in a silicon substrate, comprising the steps of: laminating a pad oxide film and a nitride film which is a silicon oxide film on a silicon substrate; Etching the pad oxide film, the nitride film, and predetermined portions of the silicon substrate to form a trench; Forming a liner oxide film which is a silicon oxide film inside the trench, and depositing silicon oxide on the silicon substrate; Removing the stacked silicon oxide to the nitride film portion; Sequentially annealing the silicon substrate from which silicon oxide has been removed to the nitride film portion at different temperatures; And removing the nitride film and the pad oxide film from the silicon substrate.

1A is a cross-sectional view of a silicon substrate with a trench formed therein;

1B is a cross-sectional view illustrating a state in which a nitride film and a pad oxide film are removed from the silicon substrate of FIG. 1A;

1C is a detailed cross-sectional view of portion A of FIG. 1B,

1D is a detailed cross-sectional view of a state in which a gate oxide film is laminated on the silicon substrate of FIG. 1C;

2a to f are cross-sectional views showing the trench forming process according to the present invention,

FIG. 2G is a detailed cross-sectional view of portion B of FIG. 2E;

FIG. 2H is a detailed cross sectional view of the portion C of FIG. 2F;

3 is a view showing an annealing process required when performing a trench forming method according to the present invention.

<Description of the symbols for the main parts of the drawings>

10 silicon substrate 20 pad oxide film

30 nitride film 40 liner oxide film

50: trench oxide

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views showing the process of the trench forming method according to the present invention.

The present invention is disclosed by forming a pad oxide film 20 on a silicon substrate 10 as shown in FIG. 2A. The pad oxide film 20 can be formed of a silicon oxide film by a thermal oxidation method or the like. In this case, the pad oxide film 20 is used as a buffer, and a nitride film 30 is deposited on the pad oxide film 20 by chemical vapor deposition at low pressure, as shown, and the nitride film 30 acts as a mask.

Then, a trench is formed by etching a predetermined portion of the silicon 10 by a photo etching method or the like as shown in FIG. 2B. Thereafter, after the silicon oxide film, that is, the liner oxide film 40 is laminated on the inner side of the trench, the silicon oxide 50 is deposited on the silicon substrate 10 by a chemical vapor deposition method or the like. Here, the silicon oxide 50 is by chemical vapor deposition, the liner oxide film 40 is by thermal oxidation, etc., the density of the liner oxide film 40 will be higher than that of the silicon oxide 50. .

Thereafter, as illustrated in FIG. 2C, silicon oxides other than silicon oxide 50 stacked on the silicon substrate 10 where the trench is formed, that is, silicon oxide stacked on the nitride film 30, are removed by a photolithography method. By polishing the silicon oxide 50 by CMP (Chemical Mechanical Polishing), the silicon oxide 50 has a height close to that of the nitride film 30 as shown in FIG. 2D.

Subsequently, the pad oxide film 20 and the silicon nitride layer 30 are sequentially erased through a wet etching method or the like as shown in FIG. 2E according to the necessity of impurity implantation or the like, and then the gate oxide film 60 is formed as shown in FIG. can do.

However, when the pad oxide film 20 and the nitride film 30 are etched as described above, that is, when the process of FIG. 2E is performed, as shown in FIG. 1B, one side of the trench is simultaneously etched.

In order to prevent this, in the present invention, before etching the pad oxide film 20 and the nitride film 30, the silicon oxide 50 in the trench is subjected to a two-step annealing process as shown in FIG.

That is, heating is started at room temperature, and the temperature is raised to 900 to 1000 ° C. After maintaining this temperature for 30 to 40 minutes, the temperature is lowered to room temperature. Up to this point, in the present specification, it is referred to as primary annealing. After a predetermined time elapses after performing the primary annealing, heating is started again, and the temperature is raised to 1100 to 1150 ° C, and the temperature is maintained for 15 to 60 seconds and then lowered to room temperature. Thus, the annealing performed after performing the primary annealing is referred to herein as the secondary annealing.

Table 1 shows the thickness of the silicon oxide 50 etched by the conventional annealing method and the thickness etched after the primary and secondary annealing.

Annealing Temperature (℃) Etching Rate (per minute) Conventional Annealing 1000 92 ± 17Å Primary Annealing 1100 21 ± 10Å Secondary annealing 1150 19 ± 10Å

As can be seen in Table 1, the etching rate of the silicon oxide 50 of the present invention is lowered, and as shown in FIG. 2G, the trench side surfaces and the liner oxide film 40 are together with the pad oxide film 20 by etching. It becomes possible to prevent the case of etching. Here, FIG. 2G is a detailed sectional view of the portion B shown in FIG. 2E.

In the case where the gate oxide film 60 is laminated on the silicon substrate 10 as shown in FIG. 2F with the pad oxide film 20 removed, the trench sidewalls and the liner oxide film 40 are not etched as described above. In this case, as shown in FIG. 2H (detailed cross-sectional view of the portion C shown in FIG. 2F), the gate oxide film 60 is prevented from being laminated thinly, and thus the bonding with the liner oxide film 40 is easy. .

As described above, the present invention has an effect that the junction between the trench side surface, the liner oxide film, and the gate oxide film is incompletely formed by etching, thereby preventing junction leakage.

Claims (5)

As a method of forming a trench in a silicon substrate, Stacking a pad oxide film and a nitride film on the silicon substrate; Etching a portion of the pad oxide film, the nitride film, and the silicon substrate to form a trench; Forming a liner oxide layer inside the trench, and depositing silicon oxide inside the trench; Removing the stacked silicon oxide up to the nitride layer; Sequentially annealing the silicon substrate from which the silicon oxide has been removed to the nitride film portion at different temperatures; And removing the nitride film and the pad oxide film from the silicon substrate. The method of claim 1, The first annealing is a trench forming method for returning to room temperature after raising from 900 to 1000 ℃. The method according to claim 1 or 2, The second annealing is a trench forming method of returning to room temperature after raising to 1100 ~ 1150 ℃ after performing the first annealing. The method of claim 2, The trench forming method of maintaining the 900 to 1000 ℃ 30 to 40 minutes when performing the first annealing. The method of claim 3, wherein A trench forming method for maintaining the 1100 to 1150 [deg.] C. for 15 to 60 seconds when performing the second annealing.