KR19990085772A - Shallow Trench Isolation Method for Semiconductor Devices - Google Patents

Abstract

The present invention discloses a shallow trench isolation method of a semiconductor device which prevents the edge of the device isolation layer from being recessed. This is a first step of sequentially forming a first insulating film and an etch stop film on the semiconductor substrate, a second step of forming a etch stop film pattern / first insulating film pattern by etching a predetermined portion of the etch stop film / first insulating film, A third step of forming a trench by etching the semiconductor substrate to a predetermined depth using an etch stop layer pattern / first insulating layer pattern as a mask, a fourth step of forming a sidewall oxide film on sidewalls and a bottom of the trench, and the sidewall oxide film A fifth step of forming a second insulating film in the formed product, a sixth step of filling a trench by depositing a third insulating film on the entire surface of the resultant product on which the second insulating film is formed, and the second until the etch stop layer pattern is exposed And a seventh step of removing a third insulating film, and an eighth step of forming an isolation layer in the trench by etching the etch stop layer pattern. Include.

Description

Shallow Trench Isolation Method for Semiconductor Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a shallow trench device isolation method of a semiconductor device which prevents the edge of the device isolation layer from being recessed.

Recently, as semiconductor devices have been highly integrated, researches for reducing the area of device isolation regions for isolating individual devices such as transistors from each other are being actively conducted. Representative methods for reducing the area of the isolation region include a shallow trench isolation region by etching a predetermined region of the semiconductor substrate to form a shallow trench isolation region and filling the trench region with an insulating layer. It is widely adopted.

1 to 6 are cross-sectional views illustrating a shallow trench element isolation method of a semiconductor device according to the prior art.

Reference numeral 11 denotes a semiconductor substrate, 13 a first insulating film, 13a a first insulating film pattern, 15 an etch stop film, 15a an etch stop film, 16 a trench, 17 a sidewall oxide film, 19 Is a second insulating film, 19a is a second insulating film pattern, and 19b is an isolation film.

Referring to FIG. 1, the first insulating layer 13 and the etch stop layer 15 are sequentially formed on the semiconductor substrate 11.

Referring to FIG. 2, an etching stop layer pattern 15a / first insulating layer pattern 13a is formed by etching a predetermined portion of the etch stop layer 15 / first insulating layer 13 using a photolithography method. do.

Subsequently, the trench 16 is formed by anisotropically etching the semiconductor substrate 11 to a predetermined depth using the etch stop layer pattern 15a and the first insulating layer pattern 13a as a mask. Forming a sidewall oxide film 17 on the sidewalls and the bottom of the trench 16 by thermally oxidizing the resultant, and a second insulating film so that the trench 16 is sufficiently buried in the entire surface of the resultant surface on which the sidewall oxide film 17 is formed. 19) For example, an oxide film having excellent embedding characteristics is formed.

Referring to FIG. 3, the second insulating layer 19 is etched by chemical mechanical polishing (CMP) until the etch stop layer pattern 15a is exposed to form a second insulating layer pattern (in the trench 16). 19a).

At this time, the second insulating layer pattern 19a may have a recess phenomenon in which the edge surface thereof is lower than the center surface of the edge effect of the chemical mechanical polishing (CMP) process.

Referring to FIG. 4, the etch stop layer pattern 15a is wet etched.

Referring to FIG. 5, an isolation layer 19b is formed in the trench 16 by etching the first insulating layer pattern 13a and cleaning the resultant.

At this time, the device isolation layer 19b is recessed even more than in the process of FIG. 3 to expose the upper side wall of the trench 16, that is, the edge sidewall of the active region, as shown by reference numeral "A".

Referring to FIG. 6, a gate oxide film (not shown) and a conductive film are sequentially formed on the entire surface of the resultant device on which the device isolation film 19b exposing the edge sidewalls of the active region is formed, and the conductive film 21 is patterned to form an active region. A gate electrode 21 is formed to cover the gap.

In this case, the gate electrode 21 surrounds the device isolation layer 19b and the edge sidewall A of the active region.

The edge sidewall A, which is enclosed by the gate electrode 21, receives an electric field in the vertical and lateral directions thereof, thereby lowering the threshold voltage, increasing the sub-threshold leakage current, and decreasing the punching margin. .

In particular, as the width of the MOS transistor becomes smaller, the threshold voltage is lowered, causing not only the punching or leakage current of the transistor, but also the transistor is formed first at the interface between the active region and the device isolation layer, and then the channel is formed in the active region. Hump phenomenon occurs that is formed and turned on.

In addition, if the cleaning process is not performed sufficiently to prevent the sidewall oxide layer 17 from being etched when the device isolation layer 19b is formed, another problem may occur in that device characteristics are changed by residual contaminants.

SUMMARY OF THE INVENTION An object of the present invention is to provide a shallow trench isolation method of a semiconductor device which prevents the edge of the device isolation film formed in the trench from being recessed.

1 to 6 are cross-sectional views illustrating a shallow trench element isolation method of a semiconductor device according to the prior art.

7 to 11 are cross-sectional views illustrating a shallow trench device isolation method of a semiconductor device according to the present invention.

In order to achieve the above object, the present invention sequentially forms a first insulating film and an etch stop film on a semiconductor substrate. A predetermined portion of the etch stop layer / first insulating layer is etched to form an etch stop layer pattern / first insulating layer pattern. A trench is formed by etching the semiconductor substrate to a predetermined depth using the etch stop layer pattern / first insulating layer pattern as a mask. A sidewall oxide film is formed on sidewalls and bottoms of the trenches. A second insulating film is formed on the resultant formed sidewall oxide film. The trench is filled by depositing a third insulating film on the entire surface of the resultant product in which the second insulating film is formed. The second and third insulating layers are removed until the etch stop layer pattern is exposed. The device isolation layer is formed in the trench by etching the etch stop layer pattern.

It is preferable that a said 1st insulating film is an oxide film.

The etch stop film is preferably an insulating film having an excellent selectivity with respect to the oxide film.

The second insulating film is preferably an insulating film having an excellent selectivity with respect to the wet etchant.

It is preferable to add the step of curing the second and third insulating film by heat-treating the resultant after the sixth step.

And after the eighth step, it is preferable to add the step of washing the result.

Therefore, according to the shallow trench device isolation method of the semiconductor device according to the present invention, the device isolation film is formed by stacking an insulating film having a good selectivity with respect to a cleaning etchant used for cleaning on the trench surface before forming the insulating film for trench filling. Prevent the phenomenon that the edges of the recesses are recessed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

7 to 11 are cross-sectional views illustrating a shallow trench device isolation method of a semiconductor device according to the present invention.

Reference numeral 51 is a semiconductor substrate, 53 is a first insulating film, 53a is a first insulating film pattern, 55 is an etch stop film, 55a is an etch stop film, 56 is a trench, 57 is a sidewall oxide film, 59 Is a second insulating film, 61 is a third insulating film, 63 is a third insulating film, 63 is a third insulating film pattern, and 61b is an isolation layer.

Referring to FIG. 7, the first insulating layer 53 and the etch stop layer 55 are sequentially formed on the semiconductor substrate 51, for example, the silicon substrate.

It is preferable that the first insulating film 53 is an oxide film and the etch stop film 55 is an insulating film having an excellent selectivity with respect to the oxide film, for example, a nitride film.

Referring to FIG. 8, an etch stop layer pattern 55a / first insulating layer pattern 53a is formed by etching a predetermined portion of the etch stop layer 55 / first insulating layer 53 by using a photolithography method. A narrow and long trench 56 is formed by anisotropically etching the semiconductor substrate 51 to a predetermined depth using the etch stop layer pattern 55a / the first insulating layer pattern 53a as a mask.

Subsequently, a step of forming a sidewall oxide layer 57 on the sidewalls and the bottom of the trench 56, an insulating material having a good selectivity with a wet etchant on the surface of the resultant layer on which the sidewall oxide layer 57 is formed, such as P-TEOS. Forming a second insulating film 59 by depositing Tetra Ethyl Ortho Silicate, an insulating material having excellent filling characteristics such that the trench 56 is sufficiently buried in the entire surface of the resultant product on which the second insulating film 59 is formed. _The process of forming the third insulating film 61 using _3- TEOS or USG (Undoped Silicate Glass), and the process of heat-treating the resultant to cure the second and third insulating films 59 and 61 are sequentially performed. .

The sidewall oxide layer 57 removes damage on the surface of the semiconductor substrate 51 when the trench 56 is formed.

The second insulating layer 59 is formed to prevent the sidewall oxide layer 57 from being etched in a subsequent process, that is, a cleaning process, to prevent the edge of the device isolation layer from being recessed.

Referring to FIG. 9, the second and third insulating layers 59 and 61 may be fully etched by a chemical mechanical polishing (CMP) process until the etch stop layer pattern 55a is exposed. A third insulating film pattern 61a / second insulating film pattern 59a / side wall oxide film 57 is formed.

Referring to FIG. 10, the etch stop layer pattern 55a is wet etched.

Referring to FIG. 11, an isolation layer 61b is formed in the trench 56 by etching the first insulating layer pattern 53a and cleaning the resultant.

In this case, since the second insulating layer 59b is still left at a predetermined thickness on the sidewall oxide layer 57, the edge of the device isolation layer 61b is protected without being etched, so that a conventional recess phenomenon does not appear.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the shallow trench isolation method of the semiconductor device according to the present invention, an etching agent used for cleaning the trench surface before forming the insulating film for filling the trench is used for cleaning etchant. By stacking an insulating film having a good selectivity, the edge of the device isolation layer is prevented from being recessed so that problems such as a decrease in a threshold voltage, an increase in a subthreshold voltage leakage current, and a hump do not occur.

Claims (6)

A first step of sequentially forming a first insulating film and an etch stop film on the semiconductor substrate; Etching a predetermined portion of the etch stop layer / first insulating layer to form an etch stop layer pattern / first insulating layer pattern; Forming a trench by etching the semiconductor substrate to a predetermined depth using the etching stop layer pattern / first insulating layer pattern as a mask; Forming a sidewall oxide film on sidewalls and bottoms of the trenches; A fifth step of forming a second insulating film on a resultant in which the sidewall oxide film is formed; A sixth step of filling the trench by depositing a third insulating film on the entire surface of the resultant product in which the second insulating film is formed; A seventh step of removing the second and third insulating films until the etch stop layer pattern is exposed; And And forming an isolation layer in the trench by etching the etch stop layer pattern. The method of claim 1, wherein the first insulating film A shallow trench element isolation method for a semiconductor device comprising an oxide film. The method of claim 1, wherein the etch stop film A shallow trench element isolation method for a semiconductor device, comprising: an insulating film having an excellent selectivity with respect to an oxide film. The method of claim 1, wherein the second insulating film A shallow trench device isolation method for a semiconductor device, comprising: an insulating film having an excellent selectivity with a wet etchant. The method of claim 1, wherein after the sixth step And heat-treating the resultant to cure the second and third insulating films. The method of claim 1, wherein after the eighth step Shallow trench device isolation method of the semiconductor device characterized in that it further comprises the step of cleaning the result.