KR19990080755A - Nonvolatile Semiconductor Device Manufacturing Method - Google Patents

Abstract

Disclosed is a method of manufacturing a nonvolatile semiconductor device capable of high integration of a memory cell. An oxide film is formed on the semiconductor substrate on which the first gate insulating film and the conductive film are sequentially stacked to expose a portion of the surface of the conductive film, and an isolation insulating film is selectively formed only on the surface exposed portion of the conductive film. Remove the barrier. The conductive layer is etched using the isolation insulating layer as a mask to form a first gate electrode, and a second gate insulating layer is formed on the first gate insulating layer including both sidewalls of the first gate electrode, and then a surface of the center portion of the isolation insulating layer. A second gate electrode is formed over a predetermined portion on the second gate insulating film including both edge portions thereof so as to expose the predetermined portion, and the isolation insulating film is exposed such that a predetermined portion of the surface of the substrate under the surface exposed portion of the isolation insulating film is exposed. And etching the first gate electrode to separate the first gate electrode. As a result, 1) it is possible to bring the line width of the first gate electrode to a size smaller than that allowed by the photolithography process by changing the process, so that the entire length of the first gate electrode can be formed to a smaller size than before, and 2) Since the buzz big is formed only on one side of the isolation insulating layers separated from each other, it is possible to minimize the increase in the line width of the first gate electrode by the buzz big.

Description

Nonvolatile Semiconductor Device Manufacturing Method

The present invention relates to a method of manufacturing a non-volatile semiconductor device, and more particularly, to a method of manufacturing a nonvolatile semiconductor device capable of achieving high integration of a nonvolatile memory cell through a process change.

Nonvolatile semiconductor devices have the advantage of being capable of electrically erasing and storing data and preserving data even when power is not supplied, and have recently expanded its application in various fields.

Such nonvolatile semiconductor devices are classified into NAND type and NOR type according to the structure of the memory cell array. These non-volatile semiconductor devices have advantages and disadvantages of high integration and high speed. There is an increasing trend in use in emerging applications.

Among these, in the NOR type nonvolatile semiconductor device directly related to the present invention, a plurality of memory cells composed of a single transistor are connected in parallel to one bit line, and a drain is connected between a bit connected to a bit line and a source connected to a common source line. Since only one cell transistor is connected, the current of the memory cell is increased and high-speed operation is possible. However, due to the increase in the area occupied by the bit line contact and the source line, it is difficult to achieve high integration of the memory device.

In the NOR-type nonvolatile semiconductor device having the above characteristics, a floating gate (hereinafter referred to as a first gate electrode) and a control gate (hereinafter referred to as a second gate electrode) are interposed between an interlayer insulating film. The memory cells are configured to have a stacked structure so that a series of operations related to storing, erasing, and reading data are performed in the following manner. At this time, the program related to the storage of data is made by the hot electron injection (HEI) or the Fowler-nordheim tunnel (FN) method, and the erasure related to erasing the data is performed by the FN tunnel method, here as an example In this case, we will look into the case where the program is implemented in the HEI method.

First, the case of the program will be described. When a voltage is applied between the bit line and the second gate electrode to form a channel between the source and the drain, hot electrons are generated at the drains, and these electrons are formed in the gate insulating film (or tunneling insulating film) due to the voltage of the second gate electrode. The barrier is injected over the first gate electrode. As a result, a program is made and data is written to the erased cells. As such, when the first gate electrode is filled with electrons, the threshold voltages (hereinafter, referred to as Vth) of the memory cells are increased due to the electrons, so that the cell is supplied by supplying a power voltage to the second gate electrode connected to the word line. When read, the high threshold voltage prevents the channel from forming and no current flows, so one state can be memorized.

On the other hand, when erasing again to store new information, the second gate electrode is grounded and a high voltage is applied to the source to supply a strong electric field across the gate insulating film between the first gate electrode and the substrate. The barrier of the insulating film is thinned so that the electrons stored in the first gate electrode in the FN tunnel manner penetrate through the thin insulating film barrier and escape to the substrate at once. As a result, data is erased. In this case, since there is no electron in the first gate electrode, the threshold voltage of the cell is lowered. Thus, when the cell is read by applying a power supply voltage to the control gate, one state different from the first can be stored.

Therefore, the data is read in such a manner that an appropriate voltage is applied to the bit line and the second gate electrode of the selected cell to read the presence or absence of current in the memory cell transistor.

However, in the nonvolatile semiconductor device of the above structure, first, a memory cell is connected in parallel to a bit line so that Vth of the memory cell transistor is lower than a voltage (for example, 0V) applied to the second gate electrode of the non-selection cell. In this case, a malfunction occurs in which all cells are read as on cells regardless of whether the selected cells are turned on or off. Therefore, there is a difficulty in managing Vth tightly. In the HEI method, excessive cell current flows from the source to the drain, which causes a problem in that a pump having a high capacity is required to generate a voltage required for the program.

In order to solve this problem, recently, a nonvolatile semiconductor device having various structures called a split gate type has been proposed. 1 shows, for example, US Patent Application No. A cross-sectional view showing a single transistor structure of a nonvolatile semiconductor device disclosed in 5,045,488 is presented.

Referring to FIG. 1, in the conventional nonvolatile semiconductor device having a split gate type structure, a first gate insulating layer 102 is formed in an active region on a semiconductor substrate 100, and a first gate insulating layer 102 is formed on the first gate insulating layer 102. The first gate electrode 104a is formed on a predetermined portion so as to be spaced apart from each other by a predetermined interval, and an isolation insulating layer 110 is formed on the first gate electrode 104a, and both sides of the first gate electrode 104a are formed. A second gate insulating film (or tunneling insulating film) 112 for data erasing is formed on the gate insulating film 102 including the second insulating film 110. The second insulating film 110 and the second gate insulating film 112 are disposed over a predetermined portion. The first gate electrode 104a formed to form the gate electrode 114a and spaced apart from each other on the same plane is common to the source region 112 formed inside the substrate 100. The channel region formed under the first gate electrode 104a and the channel region formed under the second gate electrode 114a are connected to each other in series on the substrate 100. Able to know.

Therefore, the nonvolatile semiconductor device having the above structure is manufactured through the following seventh step, as can be seen from the process flowchart shown in FIGS. 2A to 2G.

As a first step, as shown in FIG. 2A, a field oxide film is formed on a predetermined portion of the semiconductor substrate 100 to define an isolation region and an active region, and then selectively the first region only on the active region on the substrate 100. The gate insulating film 102 is formed.

As a second step, as shown in FIG. 2B, a first conductive film 104 made of polysilicon is formed on the first gate insulating film 102, and an oxide film 106 made of nitride is sequentially formed thereon. do.

As a third step, the photoresist pattern 108 is formed thereon so that the surface of the antioxidant film 106 of the portion (the portion corresponding to A1) where the floating gate is to be formed is exposed as shown in FIG. 2C, The antioxidant film 106 is etched using this as a mask.

As a fourth step, as shown in FIG. 2D, the photoresist pattern 108 is removed, and an oxidation process is performed using the antioxidant film 106 as a mask. As a result, the isolation insulating film 110 is selectively formed only in the portion which is not protected by the antioxidant film 106.

As a fifth step, as shown in FIG. 2E, the anti-oxidation film 106 is removed, and the first conductive film 104 is dry-etched using the isolation insulating film 110 as a mask to dry the first gate electrode of polysilicon. A thin filmed second gate insulating film (or tunneling insulating film) 112 is formed on the first gate insulating film 102 including both sidewalls of the first gate electrode 104a by performing an oxidation process. do.

As a sixth step, as shown in FIG. 2F, a second conductive film made of polysilicon is formed on the second gate insulating film 112 including the isolation insulating film 110, and a photosensitive film pattern defining a control gate forming portion thereon ( After forming 108a), the second conductive layer is dry-etched using this as a mask to form a second gate electrode 114a made of polysilicon.

As a seventh step, as shown in FIG. 2G, the photoresist pattern 108a is removed, and a predetermined portion on the isolation insulating layer 110 including the second gate electrode 114a and a predetermined portion on the first gate insulating layer 102 are removed. A photoresist pattern 108b is formed over the surface, and a high concentration of impurities are ion-implanted using the mask as a mask to form a source region 116 and a drain region (not shown) in the substrate 100, and then the photoresist pattern 108b. ) To complete the process.

When the nonvolatile semiconductor device is manufactured as described above, a program related to data storage is performed in the following manner. That is, when a high voltage is applied to the source region 116 of the memory cell, the first gate electrode 104a is induced to a predetermined voltage by the coupling due to the voltage, whereby the second gate electrode 114a When a predetermined voltage (eg, a voltage higher than the Vth of the transistor formed by the second gate electrode and the channel) is applied to the channel to form a channel between the source and the drain, the HEI method is used to enter the first gate electrode 104a. Electrons generated at the drain are injected. As a result, a program is made and data is written to the erased cell.

At this time, if the voltage applied to the second gate electrode is appropriately adjusted, the electric field near the edge of the first gate electrode 104a can be increased, thereby increasing the program effect as well as the source. Since the current flowing between the drain and the drain can be reduced, the power consumption is also reduced, so that a high capacity pump is not required when programming by the HEI method.

On the other hand, the erasure applies a high voltage to the second gate electrode 114a, so that the electrons stored in the floating gate 104a are stored in the second gate by the electric field between the second gate electrode 114a and the first gate electrode 104a. By exiting toward the second gate electrode 114a via the insulating film (or tunneling insulating film) 112 in the FN tunnel manner, the data is erased.

Therefore, the data reading of the memory cell is performed by applying an appropriate voltage to the bit line and the second gate line connected to the drain of the memory cell so as to read the presence or absence of the current of the memory cell transistor.

In this case, since the cell current flows only when both the channel region by the second gate electrode and the channel region by the first gate electrode are formed in the nonvolatile memory cell, the selection transistor of the memory cell transistor is typically about 1.0V. Fabricated to have Vth, the first gate electrode has a high Vth for programmed cells, and a low Vth (in some cases -Vth) for erased cells.

Therefore, in this case, even if the transistor of the first gate electrode has -Vth (the channel is formed even when 0V is applied to the control gate) due to over erase, the selection transistor is turned off. It is possible to prevent the current from flowing regardless of on or off, thereby preventing malfunction of the device without managing Vth tightly.

However, when manufacturing the nonvolatile semiconductor device by applying the above process, since the gates of the select transistors forming the first gate electrode and the second gate electrode are formed, respectively, the overall gate length of the memory cell increases during device fabrication. As a result, it is difficult to achieve high integration of memory cells. To compensate for this, when designing a circuit, the size of the first gate electrode should be defined to be smaller than that of the conventional case. Currently, the photolithography process is applied due to the relationship that the first gate electrode 104a has an island shape. In this case, it is impossible to bring the gate line line width smaller than a predetermined design rule.

Particularly, in the process of growing the isolation insulating film during the fourth step process, since the bird's beak (I) is generated by the oxidation process, the width of the first gate electrode 104a is larger than the preset "A1". Not only increases the size of " A2 ", but also causes the gate width of the select transistor constituting the second gate electrode (indicated by X in FIG. 1) to be caused by the buzz big of the first gate electrode 104a. Since the portion is to be further extended on the same plane by a smaller portion to form a larger, the width of the gate line is bound to be larger than the design rule.

As described above, when the width of the first gate electrode 104a is larger than the design rule by the buzz big I, the overall gate length of the nonvolatile memory cell increases from 1 to 1 so that the semiconductor device can be highly integrated. There is no urgent need for improvement.

Accordingly, an object of the present invention is to change the process to implement the entire length of the first gate electrode smaller than the size set by the design rule when manufacturing the nonvolatile memory cell transistor, thereby achieving high integration of the nonvolatile memory cell. The present invention provides a method for manufacturing a nonvolatile semiconductor device.

1 is a cross-sectional view showing a conventional nonvolatile semiconductor device structure;

2A to 2G are process flowcharts illustrating a method of manufacturing the nonvolatile semiconductor device of FIG. 1;

3 is a cross-sectional view showing a structure of a nonvolatile semiconductor device according to a first embodiment of the present invention;

4A to 4G are process flowcharts illustrating a method of manufacturing the nonvolatile semiconductor device of FIG. 3;

5 is a cross-sectional view showing a structure of a nonvolatile semiconductor device according to a second embodiment of the present invention;

6A to 6G are process flowcharts illustrating the method of manufacturing the nonvolatile semiconductor device of FIG. 5.

In order to achieve the above object, a first embodiment of the present invention includes the steps of sequentially forming a conductive film and an antioxidant film on a semiconductor substrate provided with a first gate insulating film; Etching the antioxidant film to expose a portion of the surface of the conductive film; Forming an isolation insulating film on a surface exposed portion of the conductive film by using the antioxidant film as a mask, and removing the antioxidant film; Etching the conductive layer using the isolation insulating layer as a mask to form a first gate electrode; Forming a second gate insulating film on the first gate insulating film including both sidewalls of the first gate electrode; Forming a second gate electrode over a predetermined portion on the second gate insulating film, including both edge portions thereof, to expose a predetermined portion of the central surface of the isolation insulating film; And selectively etching the isolation insulating film and the first gate electrode to expose a predetermined portion of the surface of the substrate under the surface exposed portion of the isolation insulating film, and separating the first gate electrode. This is provided.

In order to achieve the above object, a second embodiment of the present invention includes the steps of sequentially forming a conductive film and an antioxidant film on a semiconductor substrate provided with a first gate insulating film; Etching the antioxidant film so that the surface of the conductive film is partially exposed; Forming an isolation insulating film on a surface exposed portion of the conductive film by using the antioxidant film as a mask, and removing the antioxidant film; Etching the conductive layer using the isolation insulating layer as a mask to form a first gate electrode; Forming a second gate insulating film on the first gate insulating film including both sidewalls of the first gate electrode; Forming a second gate electrode over a predetermined portion on said second gate insulating film including said isolation insulating film; And selectively etching the second gate electrode, the isolation insulating layer, and the first gate electrode to expose a predetermined portion of the surface of the substrate under the center portion of the second gate electrode to separate the first and second gate electrodes, respectively. A nonvolatile semiconductor device manufacturing method is provided.

In this case, the etching process of the antioxidant film is performed such that the surface of the conductive film in a region corresponding to a predetermined portion of the periphery including the source region forming portion is exposed.

In the case of manufacturing the nonvolatile semiconductor device as described above, two first gate electrodes adjacent to the source region are attached to each other to form one large island shape, and then separated from the source region forming unit by an etching process. Since the first gate electrode forming process is performed in a manner of giving, the line width of the first gate electrode can be formed smaller than the size set by the design rule without difficulty in the progress of the photolithography process. In addition, since the buzz big does not occur in the isolation insulating film placed on the upper side of the first gate electrode connected to the source region, the buzz big only occurs in the isolation insulating film placed on the outer side of the first gate electrode. The increase in the length of the gate electrode can be minimized, and at the same time, it is possible to reduce the spacers between the first gate electrodes, thereby realizing a small memory cell.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

In the present invention, when forming the first gate electrode of a nonvolatile semiconductor device, the first gate electrode is initially formed into a large island shape instead of being formed in a split form, and then the etching process is used to center the source region. By proceeding the process in a manner that is separated from each other by using, a technique that focuses on achieving a high integration of the memory cell by preventing the increase in the overall length of the first gate electrode compared to the design rule, as shown in FIG. 6 to be described in detail with reference to the drawings shown in the following.

3 is a cross-sectional view illustrating a structure of a nonvolatile semiconductor device according to a first embodiment of the present invention, and FIGS. 4A to 4G are process flowcharts illustrating the method of manufacturing the nonvolatile semiconductor device of FIG. 3. FIG. 5 is a cross-sectional view illustrating a structure of a nonvolatile semiconductor device according to a second embodiment of the present invention, and FIGS. 6A to 6G are process flowcharts illustrating the method of manufacturing the nonvolatile semiconductor device of FIG. 5.

First, look at the first embodiment of the present invention.

Referring to FIG. 3, in the nonvolatile semiconductor device having a split gate type structure, a first gate insulating layer 202 is formed in an active region on a semiconductor substrate 200, and a first gate insulating layer 202 is formed. The first gate electrode 204a is formed at a predetermined portion on the first gate electrode 204a so as to be spaced apart from each other with the source region 216 interposed therebetween, and an isolation insulating film 210 is formed on the first gate electrode 204a. A second gate insulating film (or tunneling insulating film) 212 for data erasing is formed on the first gate insulating film 202 including the outer side surface of the gate electrode 204a, and a predetermined portion and a first portion of the isolation insulating film 210 are formed. The first gate electrode 204a is formed so that the second gate electrode 214a is formed over a predetermined portion on the second gate insulating film 212 and is spaced apart from each other by a predetermined distance on the same plane. ) Is commonly connected to the source region 216 formed in the substrate 200, and the channel region formed under the first gate electrode 204a and the channel region formed under the second gate electrode 214a are formed of the substrate ( It can be seen that it is configured to have a structure that is connected in series on each other on 200). In this case, the isolation insulating layer 210 has a structure in which the buzz big I is not formed on the side adjacent to the source region 216, and only the opposite side is formed. Referring to FIG. 3, since the buzz big I is formed only on one side of the isolation insulating layer 210 placed on the upper side of the first gate electrode 204a, the line width A of the first gate electrode 204a itself may be reduced. It can be seen that high integration of memory cells can be implemented.

In the figure, reference numeral L1 denotes the overall length of the first gate electrode 204a initially set during the process, and reference numeral L2 denotes the first gate electrode 204a by the occurrence of buzz big I after the process is completed. Denotes a state in which the length of the cross-section is increased, and the reference numeral X denotes the gate width of the selection transistor forming the second gate electrode 214a.

Therefore, the nonvolatile memory device having the above structure is manufactured through the following seventh step, as can be seen from the process flowchart shown in FIGS. 4A to 4G.

As a first step, as shown in FIG. 4A, a field oxide film is formed in a predetermined portion on the semiconductor substrate 200 to define an isolation region and an active region, and then selectively 70 to only the active region on the substrate 200. A 150 gate thick first gate insulating film 202 is formed.

As a second step, in order to form a first gate electrode used as a floating gate, as shown in FIG. 4B, a polysilicon material first conductive film 204 is formed on the first gate insulating film 202. It is formed to a thickness of 2000 kPa, and an antioxidant film 206 of nitride film material is sequentially formed thereon. At this time, the antioxidant film 206 is formed to a thickness of 200 ~ 1500 200.

As a third step, as shown in FIG. 4C, the source region forming portion and a portion corresponding to the predetermined region around the source region are formed so that the first gate electrodes adjacent to each other are centered around the source region to form one large island shape. The photoresist pattern 208 is formed thereon so that the surface of the antioxidant film 206 (part indicated by reference numeral L1 in the drawing) is exposed, and the antioxidant film 206 is etched using it as a mask. When the first gate electrode forming portion is defined as described above, the length of the first gate electrode to be formed in the fifth step is increased in size from "A1" to "L1" in FIG. The advantage is that the etching process can be easily performed without being restricted.

As a fourth step, as illustrated in FIG. 4D, the photoresist pattern 208 is removed, and an oxidation process is performed using the antioxidant film 206 as a mask. As a result, an isolation insulating film 210 having a thickness of 1000 to 2000 선택 is selectively formed only on the portion that is not protected by the antioxidant film 206.

As a fifth step, as shown in FIG. 4E, the anti-oxidation film 206 is removed, and the first conductive film 204 is dry-etched using the isolation insulating film 210 as a mask to dry the first gate electrode of polysilicon. 204a is formed. In this case, the first gate electrode 204a is manufactured to have a length of L2 which is slightly increased from the length of L1 initially set by the buzz big formed on both edges of the isolation insulating layer 310. Subsequently, a second gate insulating film (or tunneling insulating film) 212 having a thickness of 200 to 400 상 에 is formed on the first gate insulating film 202 including the isolation insulating film 210 and the first gate electrode 204a. In this case, the second gate insulating film 212 may be formed to have a single layer structure of a thermal oxide film, or may be formed to have a structure in which the thermal oxide film and the CVD oxide film are stacked. In the case of the isolation insulating film 210, since the thickness thereof is much thicker than that of the second gate insulating film 212, the thickness of the insulating film formed thereon is not shown.

As a sixth step, in order to form a second gate electrode used as a control gate and a gate of the selection transistor, as shown in FIG. 4F, polysilicon or polysilicon is formed on the second gate insulating film 212 including the isolation insulating film 210. A second conductive film made of polyside material is formed to a thickness of 1000 to 2000 GPa, a photosensitive film pattern 208a defining a second gate electrode forming part is formed thereon, and then the second conductive film is dry-etched using this as a mask. As a result, the central portion of the isolation insulating film 210 is exposed to a predetermined portion, and the second gate electrode 214a made of polysilicon or polyside is formed over both edge portions thereof and a predetermined portion on the second gate insulating film 212 connected thereto. ) Is formed.

As a seventh step, as shown in FIG. 4G, the photoresist layer pattern 208a is removed, a photoresist layer is formed on the second gate insulation layer including the second gate electrode 214a and the isolation insulation layer 210, and then the isolation insulation layer is formed. The photoresist pattern 208b is formed by selectively etching the surface of the central portion of the 210 to expose a predetermined portion thereof. The isolation insulating film 210 and the first gate electrode 204a are magnetized to expose a predetermined portion of the surface of the gate insulating film 202 by using the photoresist pattern 208b formed as a mask to perform a high concentration impurity ion implantation process. The first gate electrode 204 is separated from each other on the substrate 200 by being etched in a matching manner so as to be spaced apart from each other by a predetermined interval. Subsequently, a high concentration of impurities are ion-implanted onto the surface exposed portion of the gate insulating layer 202 using the photoresist pattern 208 as a mask to form a source region 216 and a drain region (not shown) in the substrate 200. Then, the photoresist pattern 208b is removed, thereby completing the process.

When the process is performed in this way, the photolithography process is not limited when the first gate electrode 204a is formed. Therefore, in consideration of the fact that the length of the first gate electrode 204a is increased due to buzz big when manufacturing the memory cell, the process is performed. In the initial stage, it becomes possible to adjust the overall length of the first gate electrode 204a.

In this case, a buzz big I is not generated on the isolation insulating film 210 placed on the upper side of the first gate electrode 204a connected to the source region 216. The gap between the line width A of each of the first gate electrodes 204a and the first gate electrode 204a is reduced due to the relationship in which the buzz big I is generated only in the isolation insulating layer 210 placed on the upper side. You can take smaller than if. Due to this, the gate width (the portion indicated by X in FIG. 3) of the selection transistor constituting the second gate electrode 214a is further extended on the same plane by the portion smaller by the buzz big of the first gate electrode 104a. In this regard, the overall width of the first and second gate electrodes 204a and 214a can be reduced due to the smaller width of the first gate electrode 204a than in the conventional case. It can be implemented.

Next, a second embodiment of the present invention will be described.

As shown in the cross-sectional view of FIG. 5, in the non-volatile semiconductor device according to the embodiment, the second insulating layer 310 is formed by the second gate electrode 314a serving as the gate of the control gate and the selection transistor in the state where the memory cell manufacturing process is completed. Since the basic structure is the same as that of the first embodiment except that it is formed on the entire surface instead of a predetermined portion of the phase, a description of the basic structure is omitted here.

In the case of FIG. 5, since the buzz big I is formed only on one side of the isolation insulating layer 310 disposed above the first gate electrode 304a, the line width A of the first gate electrode 304a itself can be reduced. It can be seen that high integration of memory cells can be implemented.

In the figure, reference numeral L1 denotes the overall length of the first gate electrode 304a initially set during the process, and reference numeral L2 denotes the first gate electrode 304a by the occurrence of buzz big I after the process is completed. Denotes a state in which the length of the cross-section is increased, and the reference numeral X denotes the gate width of the selection transistor forming the second gate electrode 314a.

Therefore, the nonvolatile memory device having the above structure is manufactured through the following seventh step as can be seen from the process flowchart shown in Figs. 6A to 6G. For convenience, a brief description will be made of a method for manufacturing the process, which is different from the first embodiment.

As a first step, as shown in FIG. 6A, a first gate insulating layer 302 is formed in an active region on the semiconductor substrate 300.

As a second step, as shown in FIG. 6B, the first conductive film 304 made of polysilicon and the antioxidant film 306 made of nitride film are sequentially formed on the first gate insulating film 202.

As a third step, as shown in FIG. 6C, a source region forming portion and a portion corresponding to a predetermined region around the source region are formed in order to form a large island shape by attaching adjacent first gate electrodes around the source region to each other. The photoresist pattern 308 is formed thereon so that the surface of the antioxidant film 306 (part indicated by reference numeral L1 in the drawing) is exposed, and the antioxidant film 306 is etched using this as a mask.

As a fourth step, as shown in FIG. 6D, the photoresist pattern 308 is removed, and an oxidation process is performed using the antioxidant film 306 as a mask to selectively select only a portion that is not protected by the antioxidant film 306. An isolation insulating layer 310 is formed.

As a fifth step, as shown in FIG. 6E, the anti-oxidation film 306 is removed, and the first conductive film 304 is dry-etched using the isolation insulating film 310 as a mask to dry-etch the first conductive film 304. A first gate electrode 304a is formed, and a second gate insulating film (or tunneling insulating film) 312 having a single layer structure of a thermal oxide film or a structure in which the thermal oxide film and the CVD oxide film are stacked on the entire surface thereof is formed. In this case, the first gate electrode 304a is manufactured to have a length of L2 slightly increased from the length of L1 initially set by the buzz big formed on both edges of the isolation insulating layer 310.

As a sixth step, as shown in FIG. 6F, a second conductive film made of polysilicon or polyside is formed on the second gate insulating film 312 including the isolation insulating film 310, and the second gate electrode forming part is formed thereon. After defining the photosensitive film pattern 308a, the second conductive film is dry-etched using this as a mask. As a result, a second gate electrode 314a of polysilicon or polyside material is formed over a predetermined portion on the second gate insulating film 312 around the insulating insulating film 310.

As a seventh step, as shown in FIG. 6G, the photoresist pattern 308a is removed, a photoresist is formed on the second gate insulating layer 312 including the second gate electrode 314a, and then the second gate electrode ( The photoresist pattern 308b is formed by selectively etching the surface of the center portion 314a so as to expose a predetermined portion thereof. By using the photoresist pattern 308b as a mask, the isolation insulating film 310 and the first gate electrode 304a are etched in a self-aligning manner so that a predetermined portion of the surface of the gate insulating film 302 is exposed. The first and second gate electrodes 304a and 314a are separated from each other. Subsequently, a source region 316 and a drain region (not shown) are formed in the substrate 300 by ion implanting a high concentration of impurities onto the surface exposed portion of the gate insulating layer 302 using the photoresist pattern 308b as a mask. Next, the photoresist pattern 308b is removed, thereby completing the process.

In the case of manufacturing the nonvolatile memory cell as described above, the line width A and the overall length of each of the first gate electrodes 304a can be made smaller than in the case of the first embodiment as in the first embodiment. It is possible to implement smaller memory cells.

As described above, according to the present invention, 1) the line width of the first gate electrode can be reduced to a size smaller than that allowed by the photolithography process by changing the process, so that the entire length of the first gate electrode is formed to be smaller than the conventional one. 2) Since the buzz big is formed only on one side of the isolation insulating films separated from each other, the line width of the first gate electrode can be minimized by the buzz big, thereby realizing a highly integrated memory cell.

Claims (18)

Sequentially forming a conductive film and an antioxidant film on the semiconductor substrate provided with the first gate insulating film; Etching the antioxidant film to expose a portion of the surface of the conductive film; Forming an isolation insulating film on the surface exposed portion of the conductive film by using the antioxidant film as a mask, and removing the antioxidant film; Etching the conductive layer using the isolation insulating layer as a mask to form a first gate electrode; Forming a second gate insulating film on the first gate insulating film including both sidewalls of the first gate electrode; Forming a second gate electrode over a predetermined portion on the second gate insulating film, including both edge portions thereof, to expose a predetermined portion of the central surface of the isolation insulating film; And And separating the first gate electrode by selectively etching the isolation insulating film and the first gate electrode to expose a predetermined portion of the surface of the substrate under the surface exposed portion of the isolation insulating film. Device manufacturing method. The method of claim 1, wherein the second gate insulating film is formed in a single layer structure of a thermal oxide film or a stacked structure of a thermal oxide film and a CVD oxide film. The method of claim 1, wherein the second gate insulating layer is formed to a thickness of about 200 to about 400 microns. The method of claim 1, wherein the anti-oxidation film is formed of a nitride film having a thickness of 200-1500 kV. The method of claim 1, wherein the first gate electrode is formed of polysilicon having a thickness of 1000 to 2000 kV. The method of claim 1, wherein the second gate electrode is formed of polysilicon or polyside having a thickness of 1000 to 2000 kV. The method of claim 1, wherein the first gate insulating layer is formed to a thickness of about 70 to about 150 microns. 2. The method of claim 1, wherein the isolation insulating film is formed of an oxide film having a thickness of 1000 to 2000 GPa. The method of claim 1, wherein the etching of the anti-oxidation film is performed such that the surface of the conductive film in a region corresponding to a predetermined portion of the periphery including a source region forming portion is exposed. Sequentially forming a conductive film and an antioxidant film on the semiconductor substrate provided with the first gate insulating film; Etching the antioxidant film so that the surface of the conductive film is partially exposed; Forming an isolation insulating film on a surface exposed portion of the conductive film by using the antioxidant film as a mask, and removing the antioxidant film; Etching the conductive layer using the isolation insulating layer as a mask to form a first gate electrode; Forming a second gate insulating film on the first gate insulating film including both sidewalls of the first gate electrode; Forming a second gate electrode over a predetermined portion on said second gate insulating film including said isolation insulating film; And Selectively etching the second gate electrode, the isolation insulating layer and the first gate electrode to separate the first and second gate electrodes so that the substrate surface positioned below the center portion of the second gate electrode is partially exposed. Nonvolatile semiconductor device manufacturing method characterized in that consisting of a step. The method of claim 10, wherein the second gate insulating film is formed in a single layer structure of a thermal oxide film or a stacked structure of a thermal oxide film and a CVD oxide film. 11. The method of claim 10, wherein the second gate insulating film is formed to a thickness of 200 ~ 400Å. The method of claim 10, wherein the anti-oxidation film is formed of a nitride film having a thickness of 200-1500 kV. The method of claim 10, wherein the first gate electrode is formed of polysilicon having a thickness of 1000 to 2000 μs. The method of claim 10, wherein the second gate electrode is formed of polysilicon or polyside having a thickness of 1000 to 2000 μs. The method of claim 10, wherein the first gate insulating layer is formed to a thickness of 70 to 150 kV. The method of claim 10, wherein the isolation insulating film is formed of an oxide film having a thickness of 1000 to 2000 kV. The method of claim 10, wherein the etching of the anti-oxidation film is performed such that the surface of the conductive film in a region corresponding to a predetermined portion of the periphery including a source region forming portion is exposed.