經濟部智慧財產局員工消費合作社印製 405168 a7 _B7 五、發明説明（1 ) 〔發明所屬之技術領域〕 本發明係關於非依電性半導體元件之製造方法者，詳 言之，係有關於可藉由工程變更以求得非依電性存儲單元 之高積體化，而獲得非依電性半導體元件之製造方法。 〔習知技術〕 非依電性半導體元件’係具有可電性地消除及存儲資 料，而即使未供給電源也可保存資料之優點，因此近幾年 來在多種多樣之領域中廣泛地擴大其應用範圍β 此種非依電性半導體元件，係按照記憶胞陣列之構造 而大幅地區分為NAND型及NOR型；此等型態大致上區別 為高積體化及高速性而各具有其本身之優點，其使用也在 漸漸地增加中。 其中，與本發明直接關聯的NOR型非依電性半導趙 元件，係於了個位元線並聯連結有由單一電晶體所形成之 多數個存儲單元，並在連結至該位元線之汲極與連結至共 同源極線之源極間只連結一個單元電晶體，藉此使存儲單 疋之電流增大以進行高速度動作，然而，位元線接點及源 極線所占據之面積卻增大，以致於不易使存儲單元高積體 化。 具有如上述特徵之N0R型非依電性半導體元件，係 通常在透過層間絕緣膜來積層漂浮閘（以下，稱為第一閘 極）及控制閉（以下稱第：閘極）之構造中構成存儲單元， 按照以下之方式進行關聯於資料之存儲、消除/解碼之一 連串動作。 1 -I. *^ϋ I i ^^1 I - - 1^1 1^1 *11 I. n^i 1^1 I ^^1 ^—J • · Λ4-* (請先聞讀背面之注f項再填寫本頁)Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 405168 a7 _B7 V. Description of the Invention (1) [Technical Field to which the Invention belongs] The present invention relates to a method for manufacturing non-electrical semiconductor devices. In particular, The manufacturing method of the non-independent semiconductor element is obtained by engineering to obtain the high integration of the non-independent memory cell. [Known Technology] Non-electrical semiconductor devices have the advantage of being able to erase and store data electrically, and to save data even without power supply. Therefore, in recent years, it has been widely used in a variety of fields. Range β This type of non-electrically dependent semiconductor device is largely divided into NAND type and NOR type according to the structure of the memory cell array. These types are roughly distinguished by high integration and high speed, each with its own characteristics. The advantage is that its use is gradually increasing. Among them, the NOR-type non-electroconductive semiconductor device directly related to the present invention is connected to a bit line in parallel with a plurality of memory cells formed by a single transistor, and is connected to the bit line. Only one unit transistor is connected between the drain and the source connected to the common source line, thereby increasing the current of the memory cell for high-speed operation. However, the bit line contacts and the source line occupy the However, the area is increased, so that it is not easy to make the memory cell highly integrated. The N0R-type non-electrostatic semiconductor element having the characteristics described above is generally constructed in a structure in which a floating gate (hereinafter, referred to as a first gate) and a control gate (hereinafter referred to as a "gate") are laminated through an interlayer insulating film. The storage unit performs a series of operations related to data storage, erasure / decoding in the following manner. 1 -I. * ^ Ϋ I i ^^ 1 I--1 ^ 1 1 ^ 1 * 11 I. n ^ i 1 ^ 1 I ^^ 1 ^ —J • · Λ4- * (Please read the (Note f, then fill out this page)
經濟部智慧財產局員工消費合作社印製 __405168 B7_ 五、發明説明（2 ) ~ '~ 此時，與資料之存儲關聯的程式，係藉HEI(h〇t eiectr〇n injection)或FN随道（fowle卜㈣dheim tunne〇來進行，而與 資料之消除有關聯之一連串動作則藉1?1^隧道方式來進行 〇 以下，就程式藉由HEI方式來執行之情況作為一例說 明之。 首先，就程式之情形來說明❶當將電壓施加於位元線 及第二閘極以在源極與汲極間形成通道時，在汲極產生熱 電子，此熱電子則因第二閘極之電壓而超越閘絕緣膜（或 隧道絕緣膜）之疊障而注入於第一閘極。其結果，成為程 式而將資料寫入於所去除之單元。如此，在第一閘極填充 電子時，為此電子而存儲單元之閾電壓（以下，稱為Vth) 則上升；當將電源電壓供給字元線連結之第二閘極以讀出 單元時，則高閾值電壓而無法形成通道，以致電流不流 通’因此使之成為可記憶一個狀態。 一方面，為了存儲新資訊而再去除時，若使第二閘極 接地將高電壓外加於源極以便將強電場供給第一閘極與基 板間之閘絕緣膜兩端的話，閘絕緣膜之疊障則變薄，因此 由EN隧道方式所存儲於第一閘極内之電子便穿透已變薄 之絕緣膜疊障，而一下子離開到基板側。其結果，執行資 料之消除。因此，第一閘極内沒有電子而單元之閾電壓變 低，所以將電源電壓外加於控制閘來讀單元時，變成可記 憶與開始之情況不同之另一狀態。 即，將電壓適當地外加於選擇單元之位元線及第二閘 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -6- 1 I : I - - - -I 1— I - - I I II -- I n - 11 I (請先閲讀背面之注意事項再填寫本頁) ^05168 b7 ----— — —^_ —_____ 五、發明説明（3 ) 極以解碼存儲單元電晶體之有無電流，藉此來執行資料之 解碼。 然而，這種構造之非依電性半導體元件，卻產生以下 之問題，即： (1) 當存儲單元並聯地連結於位元線，而存儲單元電 晶體之Vth變成低於外加於選擇單元之第二閘極的電壓（例 如0V)時，不管選擇單元之0N(接通）、〇FF(斷開），電流 均流通，所有之單元則產生讓接通單元讀出之錯誤動作， 因此存在著必須嚴格地管理Vth之難題； (2) 當藉HEI方式來編程式時，隨著從源極向汲極側流 通過度之電池電流，而令程式產生必需要的電壓時，將產 生需要高電容之泵的問題。 為了解決此問題’最近，提案有一種所謂分離閘型 (split gate type)之多種多樣的構造的非依電性半導體元件 。第5圖係作為其一例而提示美國專利第5,〇45,488號所揭 露之非依電性半導體元件之單一電晶體構造的斷面圖。 於第5圖中，具有分離閘型構造之習知非依電性半導 體元件為：其形成得較大；半導體基板丨00上之源極領域 形成有第一閘緣膜102 ’且在閘絕緣膜1〇2上之一定部分形 成有相互隔離一定間隔之第一閘極l〇4a ;在該第一閘極 l〇4a上部形成有隔離絕緣膜110;在包含前述第一閘極1〇乜 之兩側面之閘絕緣膜102上，為消除資料而形成有第一閘 絕緣膜（或隧道絕緣膜）112 ;在該隔離絕緣膜no及第一閘 絕緣膜112上之一定部分，形成有第二閛極114a ;而在同 本紙張尺度適用中國國家標準（CNS ) μ规格（210Χ 297公釐） ： :^-- (請先聞讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs __405168 B7_ V. Invention Description (2) ~ '~ At this time, the program related to the storage of data is accompanied by HEI (h〇t eiectr〇n injection) or FN. (Fowle is performed by ㈣dheim tunne〇, and a series of actions related to the elimination of data is performed by 1 ~ 1 ^ tunnel mode. Below 0, the program is executed by HEI method as an example. First, let ’s The situation of the program is explained. When a voltage is applied to the bit line and the second gate to form a channel between the source and the drain, a hot electron is generated at the drain, which is due to the voltage of the second gate. It is injected into the first gate beyond the barrier of the gate insulating film (or tunnel insulating film). As a result, the data is written into the removed unit as a program. Thus, when the first gate is filled with electrons, this is done for this purpose. The threshold voltage (hereinafter referred to as Vth) of the memory cell is increased. When the power supply voltage is supplied to the second gate connected to the word line to read the cell, the threshold voltage is too high to form a channel, so that current does not flow. 'therefore On the one hand, if it is removed in order to store new information, if the second gate is grounded, a high voltage is applied to the source to supply a strong electric field to the gate insulating film between the first gate and the substrate. At the end, the stack barrier of the gate insulating film becomes thinner, so the electrons stored in the first gate by the EN tunnel method penetrate the thinned stack barrier and leave to the substrate side at a time. As a result Therefore, the elimination of data is performed. Therefore, there is no electron in the first gate and the threshold voltage of the cell becomes low, so when the power supply voltage is applied to the control gate to read the cell, it becomes a state that can be memorized and different from the beginning. , The voltage is appropriately applied to the bit line of the selection unit and the second scale. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -6- 1 I: I----I 1— I- -II II-I n-11 I (Please read the precautions on the back before filling out this page) ^ 05168 b7 ----— — — ^ _ —_____ V. Description of the invention (3) The pole is used to decode the memory unit power. The current of the crystal is used to decode the data. However, the non-electrically dependent semiconductor element of this structure has the following problems: (1) When the memory cells are connected in parallel to the bit line, the Vth of the memory cell transistor becomes lower than the voltage applied to the selection cell. When the voltage of the second gate (for example, 0V), no matter whether the selected unit is 0N (on) or 0FF (off), the current flows, and all the units generate the wrong action to read the on unit, so there is It is necessary to strictly manage the problem of Vth; (2) When programming by HEI, as the excessive battery current flows from the source to the drain side, and the program generates the necessary voltage, the required high voltage will be generated. Problems with capacitor pumps. In order to solve this problem, recently, a non-electrostatic semiconductor device having a variety of structures called a split gate type has been proposed. Fig. 5 is a cross-sectional view showing, as an example, a single transistor structure of a non-electronic semiconductor device disclosed in U.S. Patent No. 5,045,488. In FIG. 5, a conventional non-electrical semiconductor element having a split gate structure is: it is formed relatively large; a first gate edge film 102 ′ is formed in a source region on a semiconductor substrate and is insulated at the gate A certain portion of the film 102 is formed with first gate electrodes 104a separated from each other at a certain interval; an isolation insulating film 110 is formed on the first gate electrode 104a; and the first gate electrode 104 On both sides of the gate insulating film 102, a first gate insulating film (or a tunnel insulating film) 112 is formed for erasing data; a portion of the isolation insulating film no and the first gate insulating film 112 is formed with a first The second pole 114a; and the same paper size applies the Chinese National Standard (CNS) μ specification (210 × 297 mm):: ^-(Please read the precautions on the back before filling this page)
'1T 經濟部智慧財產局員工消費合作社印製 405168 五、發明説明（4 ) 一平面上被配置成相互隔離一規定間隔之第一閘極i 04a， 係共同地連結於一形成在基板100内部之源極領域U6 ;形 成在第一閘極104a下部之通道領域，係構成為在基板1〇〇 上具有相互串聯地連結著之構造。 以下，參照第6圖（A)〜第6圓（G) ’分七階段說明如上 述構造之非依電性半導體元件之製造工程。 製造工程之第一階段如第ό圖（A)所示，於半導體基板 上之一定部分形成場氧化膜，定義（界定）元件分離領域與 有源領域之後，僅在基板上1〇〇之有源領域選擇性地形成 第一閘絕緣膜102。 第二階段如第6圖（Β)所示，於第一閘絕緣膜ι〇2上形 成多晶矽材質之第一導電性膜104，進而在其上依次形成 氮化膜材質之氧化防止膜106。 第三階斧如第6圖（C)所示，於其上面形成感光膜圖案 108以便露出形成有漂浮閘之部分（相當於八丨之部分）的氧 化膜106表面，然後將此作為遮覆膜而蝕刻氧化防止膜1〇6 〇 第四階段如第6圖（D)所示’去除感光膜圖案1〇8，將 氧化膜106當做遮覆膜而進行氧化工程。其結果，僅在未 由氧化防止膜106所保護之部分選擇性地形成隔離絕緣膜 110 ° 第五階段如第6圖（Ε)所示，去除氧化防止膜丨〇6，將 隔離絕緣膜110當做遮覆膜，乾式蝕刻第一導電性膜丨〇4以 形成多晶矽材質之第一閘極1 〇4a，進而施行氧化工程，於 本紙張尺度適用中國國家梯準（〇泌）八4規格（210父297公董） ----；---；----^— (請先閱讀背面之注意事項再填寫本頁) ,ιτ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 4〇5l6§ b7 五、發明説明（5 ) 包含有第一閘極104a之兩側壁的第一閘絕緣膜102上形成 薄薄之第二閘絕緣膜（或隧道絕緣膜）丨12。 第六階段如第6圖（F)所示，在包含有隔離絕緣膜11〇 之第二閘絕緣膜U2上，形成多晶矽材質之第二導電性膜 ’ ’進而在其上面形成一用來界定控制閘形成部之感光膜囷 案108a後，將此當做遮覆膜，乾蝕刻第二導電性膜以形成 多晶矽材質之第二閘電極114a。 第七階段如第6圖（G)所示，去除感光膜圖案i〇8a，在 包含第二閘極114a之隔離絕緣膜no上之一定部分及第一 閘絕緣膜102上之一定部分形成感光膜圖膜1〇8b，以此當 做遮覆膜而離子植入高濃度之雜質於全面，藉此將源極領 域116及汲極領域（未圖示）形成於基板1〇〇之後，去除感光 膜圖案，完成工程之進行。 當要製$如上述一般之非依電性半導體元件時，按照 以下之方式執行資料之存儲及其關聯之程序。即，若將高 電壓外加於存儲單元之源極領域116的話，在藉由前述電 壓之耦合下第一閘極1 〇4a便被一定之電壓所誘導；當在此 時將一定之電壓（例如，高於由第二閘極及通道所形成之 電晶體Vth的電壓）外加於第二閘極U4a以便在源極與汲極 間形成通道時，利用HEI方式將汲極所產生之電子注入第 -閉極1G軸。其結果，成為程式㈣資料記錄於被消除 之單元。 此時，若將外加於第二閘極之電壓適當地調節的話， 可在第一閘極104a邊緣附近使電場變大，所以可使程式效 本紙張尺度適用中國國家操準（CNS )八4^|^ (^!0x297公着） '" (請先閱讀背面之注意事項再填寫本頁)'1T Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 405168 5. Description of the Invention (4) The first gates i 04a, which are arranged on a plane to isolate each other at a predetermined interval, are commonly connected to one formed inside the substrate 100 The source region U6; the channel region formed in the lower part of the first gate electrode 104a has a structure in which the substrate 100 is connected in series with each other. Hereinafter, the manufacturing process of the non-electrostatic semiconductor element structured as described above will be described in seven stages with reference to FIGS. 6 (A) to 6 (G) '. In the first stage of the manufacturing process, as shown in Figure (A), a field oxide film is formed on a certain portion of the semiconductor substrate. After defining (defining) the field of element separation and the field of active, only 100% of the The source region selectively forms the first gate insulating film 102. In the second stage, as shown in FIG. 6 (B), a first conductive film 104 made of polycrystalline silicon is formed on the first gate insulating film ι02, and an oxidation prevention film 106 made of a nitride film is sequentially formed thereon. As shown in FIG. 6 (C), a third-stage axe is formed with a photosensitive film pattern 108 on it so as to expose the surface of the oxide film 106 where the floating gate is formed (equivalent to the part of the eighth), and then this is used as a mask. As shown in FIG. 6 (D), the fourth step is to remove the photosensitive film pattern 108, and the oxidation process is performed using the oxide film 106 as a masking film. As a result, the isolation insulating film 110 is selectively formed only on the portion not protected by the oxidation prevention film 106. In the fifth stage, as shown in FIG. 6 (E), the oxidation prevention film is removed, and the isolation insulation film 110 is removed. As a masking film, the first conductive film is dry-etched to form the first gate electrode 104a of the polycrystalline silicon material, and then an oxidation process is performed. In this paper, China ’s national ladder standard (〇 Bi) 8 4 specifications ( 210 Father 297 Public Director) ----; ---; ---- ^ — (Please read the notes on the back before filling out this page), ιτ The Intellectual Property Department of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the intellectual property of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau 405l6§ b7 V. Description of the Invention (5) A thin second gate insulating film (or a tunnel insulating film) is formed on the first gate insulating film 102 including the two side walls of the first gate electrode 104a ) 丨 12. In the sixth stage, as shown in FIG. 6 (F), a second conductive film made of polycrystalline silicon is formed on the second gate insulating film U2 including the insulating insulating film 110, and then a second conductive film is formed on the second insulating film U2 to define After controlling the light-sensitive film 108a of the gate forming portion, this is used as a masking film, and the second conductive film is dry-etched to form a second gate electrode 114a made of polycrystalline silicon. In the seventh stage, as shown in FIG. 6 (G), the photosensitive film pattern i08a is removed, and a photosensitive portion is formed on a certain portion of the isolation insulating film no including the second gate electrode 114a and a certain portion on the first gate insulating film 102. The film pattern film 108b is used as a masking film to ion-implant high-concentration impurities in a comprehensive manner, thereby forming the source region 116 and the drain region (not shown) on the substrate 100, and then removing the light. Film pattern to complete the project. When the general non-electrical semiconductor device is to be manufactured as described above, the data storage and related procedures are performed in the following manner. That is, if a high voltage is applied to the source region 116 of the memory cell, the first gate 104a is induced by a certain voltage under the coupling of the foregoing voltage; when a certain voltage (for example, , The voltage higher than the transistor Vth formed by the second gate and the channel) is applied to the second gate U4a so that when a channel is formed between the source and the drain, the electrons generated by the drain are injected into the first using the HEI method. -Closed pole 1G axis. As a result, the program data is recorded in the deleted unit. At this time, if the voltage applied to the second gate is appropriately adjusted, the electric field can be increased near the edge of the first gate 104a, so that the paper size can be adapted to the Chinese National Standard (CNS) 8-4. ^ | ^ (^! 0x297public works) '" (Please read the notes on the back before filling this page)
* 9 - 五、發明説明（6) 應增加之同時，可使流通於源極與沒極間之電流變小藉 此減少電力消耗，並於藉由方式之程序時不需要古 電容之泵。 间 另—方面’在消除之時’將高電壓施加於第二閉極U4a ‘以便藉著第二閘電極114a與第一閘極】04a間之電場來存儲 於漂浮閘104a内之電子便通過第二閘絕緣膜（或随道絕緣 膜）Π2而藉由FN随道方式離開到第二開電極心側以 執行資料之消除》 因此，將適當之電愿施加於連結至存儲單元之沒極的 位元線及第二閘極線以解碼存儲單元之電流之有無，藉此 來進行存儲單元之資料解碼。 此時，如上述非依電性存儲單元只要是未形成藉助第 一閘極之通道領域及藉助第一閘電極之通道領域之全部， 即不流通電十電流，因此存儲單元電晶體之選擇電晶體， 通常被製作成具有1.0V左右之vth;其中，被程式化時則 第一閘極具有高Vth，而被消除之單元時則第一閘極具有 低Vth(視情況而具有一 Vth) 〇 經濟部智慧財產局W工消費合作社印製 故此時，因第一閘極之電晶艘過度消除（〇ver erase)而 即使具有一 Vth(即使在控制閘外加有也形成通道）也將 選擇電晶體斷開（OFF)，所以不管選擇單元之on/ 〇FF， 均可防止電流之流通現象，即使未嚴格管理Vth，也可防 止元件之錯誤動作。 〔發明之所要解決之課題〕 然而，若適用如上述之工程來製造非依電性元件時， 本紙張尺國家橾準（CNS ) Μ規格（21〇X297公釐〉 -10" A7 4〇5168 五、發明説明（7 ) 由於分別形成用來構成第一閘極及第二閘極之選擇電晶雜 之閘門，而產生因在元件之製造時增加存儲單元件之總閘 長度而無法謀求存儲單元之高積體化的問題。為了補實此 問題缺點，在電路設計時就必須將第一閘極之尺寸界定為 小於既有之尺寸，然而，只因現在之第—閘極1〇“具有島 形之形狀而對於光蝕刻工程之適用仍有界限，因此無法將 閘線之線寬作成小於既往設定的設計規格大小。 尤其是，在第四階段之工程進行時，在使隔離絕緣膜 成長之過程中，因氧化工程而產生鳥嘴狀（bird，s beak)， 因此第一閘極1 〇4a之寬度增加到大於既往設定之“ A1 ” ，不但具有“A2”之大小，且成為第二閘極之選擇電晶 體之閘寬度（在第5圈用X表示之部分）也在同一平面上更延 長大到因第一閘極1〇4&之鳥嘴狀而變小之部分，所以閘線 之線寬大於碌計規則之線寬。 */ 若如上所述因烏嘴I而第一閘極丨〇4&之寬度大於設計 規則時，非依電性存儲單元之總閘長度則u增加到12，而 無法謀求半導體元件之高積體化，所以極亟求改善此問題 之對策。 經濟部智慧財產局員工消費合作社印製 本發明之目的係在於提供一種非依電性半導體元件之 製造方法，以便在非依電性存儲單元電晶體之製造時，變 更工程’使得第一閘極之全體長度小於由設計規則所設定 之尺寸，藉此可謀非依電性存儲單元之高積體化。 〔用以解決課題之手段〕 為了達成此種目的，關於本發明之第一實施例包含有 本紙張尺度適财關家鰣（CNS ) - 經濟部智慧財產局員工消費合作社印製 405168 B7 五、發明説明（8 ) 導電性膜及氧化防止膜形成工程，係在具有第一閘絕 緣膜之半導體基板上，依次形成導電性膜及氧化防止膜； 蝕刻工程，係將前述氧化防止膜加以蝕刻以便前述導 電性膜表面只要露出一定部分； 去除工程，係將前述氧化防止膜當做遮覆膜，於前述 導電性膜表面露出部形成隔離絕緣膜後，去除前述氧化防 止膜； 第一閘極形成工程，係將隔離絕緣膜當做遮覆膜，蝕 刻前述導電性膜以形成第一閘極； 第二閘絕緣膜形成工程，係在包含前述第一閘極之兩 側壁的該第一閘絕緣膜上形成第二閘絕緣膜； 第二閘極形成工程，係在包含前述隔離絕緣膜之兩邊 緣的前述第十閘絕緣膜上之一定部分形成第二閘極，以便 前述隔離絕緣膜之中央部表面僅露出一定部分；及 分離工程，係將别述隔離絕緣膜及前述第一閘極選擇 蝕刻以分離前述第一閘極，以便位置於前述隔離絕緣膜之 表面露出部下側之前述基板表面，僅露出一定部分。 又’為了達成刖述目的’關於本發明之第二實施例， 包含有： 導電性膜及乳化防止膜形成工程，係在備有第一閘絕 緣膜之半導體基板上，依次形成導電性膜及氧化防止膜； 触刻工程’係將前述氧化防止膜加以钱刻以便前述導 電性膜表面只露出一定部分； —^n ^^^^1 n I t ml (請先閲讀背面之注意事項再填寫本頁) 卞 - Γ i- 五、發明説明（9 去除工程’係將前述氧化防止膜當做遮覆膜，於前述 導電性膜之表面露出部形成隔離絕緣膜後，去除前述氧化 防止联； (請先聞讀背面之注意事項再填寫本頁j 第一閉極形成工程’係將前述隔離絕緣膜當做遮覆膜 :，姓刻導電性膜以形成第—閘極； 第二閘絕緣膜形成工程，係在包含前述第一閉極之兩 側壁的前述第一閘絕緣膜上，形成第二開絕緣膜； 第一閘極形成工程，係在包含前述隔離絕緣膜的其周 圍之前述第二閘絕緣膜上的—定部分，形成第二開極；及 分離工程，係將前述第二閘極，前述隔離絕緣膜及 則述第一閘極選擇蝕刻以分別分離前述第一第二閘極， 、π' 以便位置於前述第二閘極之中央部下側的前述基板表面， 露出一定部分。 此時，，行前述氧化防止膜之蝕刻工程，以便該當於 包含源領域形成部的其周圍之一定部分領域的前述導電性 膜表面’露出一定部分。 經濟部智慧財產局員工消費合作社印製 若如上述地要製造非依電性半導體元件時，使鄰接於 源領域之兩個第一閘極互相附著以作成一個大島形狀，然 後以此狀態，透過蝕刻工程使源領域形成部分離於中心， 藉此來進行第一閘極形成工程，因此不會有光蝕刻工程之 進行上之困難，可將第一閘極之線寬作成小於依據設計規 則來設定的大小。更且，在置在與源領域連結的一邊之第 一閘極上之隔離絕緣膜上，不會產生鳥嘴，而僅在置在其 外圍側之第一閘極上之隔離絕緣膜產生鳥嘴狀，藉此可使 13- 405168 A7* 9-V. Explanation of the invention (6) At the same time, the current flowing between the source and the electrode can be reduced, thereby reducing the power consumption, and the ancient capacitor pump is not required when the method is adopted. In another aspect, 'at the time of elimination', a high voltage is applied to the second closed electrode U4a 'so that the electrons stored in the floating gate 104a pass through the electric field between the second gate electrode 114a and the first gate electrode 04a and pass through The second gate insulation film (or track insulation film) Π 2 leaves the second open electrode core side by FN in a track manner to perform data erasing. Therefore, an appropriate voltage is applied to the electrode connected to the memory cell. The bit line and the second gate line are used to decode the presence or absence of the current of the memory cell, thereby decoding the data of the memory cell. At this time, as described above, as long as the non-electrically-dependent memory cell has not formed the channel area by means of the first gate electrode and the channel area by means of the first gate electrode, the electric current does not flow, so the selection of the memory cell transistor The crystal is usually made to have a vth of about 1.0V; where the first gate has a high Vth when it is programmed, and the first gate has a low Vth when it is eliminated (as appropriate, it has a Vth) 〇 Printed by the W Industrial and Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics. At this time, because of the excessive erase of the first gate electrode, even if it has a Vth (the channel is formed even if it is added to the control gate), it will be selected. The transistor is turned off, so regardless of the on / FF of the selected unit, the current can be prevented from flowing. Even if Vth is not strictly managed, the component can be prevented from malfunctioning. [Problems to be Solved by the Invention] However, if the above-mentioned process is applied to manufacture non-electrically-dependent components, this paper rule National Standard (CNS) M specification (21〇X297 mm) -10 " A7 4〇5168 V. Description of the invention (7) Because the gates of the selective transistor for forming the first gate and the second gate are formed respectively, it is impossible to seek storage due to the increase of the total gate length of the storage unit during the manufacturing of the component. The problem of high integration of cells. In order to supplement the shortcomings of this problem, the size of the first gate must be defined to be smaller than the existing size when designing the circuit. However, only the current gate—10 It has an island shape and there is still a limit to the application of the photoetching process. Therefore, the line width of the gate line cannot be made smaller than the previously set design specification. Especially, in the fourth stage of the project, the isolation insulating film is made. During the growth process, the bird's beak (bird, s beak) is generated due to the oxidation process. Therefore, the width of the first gate electrode 104a is larger than the previously set "A1", which not only has the size of "A2", but also The gate width of the selection transistor for the second gate (the part indicated by X on the fifth turn) is also extended to the part that is smaller due to the bird's beak shape of the first gate 104, Therefore, the line width of the gate line is greater than the line width of the rule. * / If the width of the first gate electrode 〇4 & is larger than the design rule as described above, the total gate length of the non-electrical storage unit Then u is increased to 12, and it is impossible to achieve the high integration of semiconductor elements, so it is urgent to countermeasures to improve this problem. Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumer Cooperative, Printed The purpose of this invention is to provide a non-electrical semiconductor Element manufacturing method, so that in the manufacture of non-volatile memory cell transistors, the engineering is changed so that the entire length of the first gate is smaller than the size set by the design rules, so that [Means for solving problems] [Means for solving problems] In order to achieve such a purpose, the first embodiment of the present invention includes a paper size suitable for financial affairs (CNS) Manufacturing 405168 B7 V. Description of the invention (8) The conductive film and the oxidation prevention film formation process are sequentially formed on the semiconductor substrate having the first gate insulating film, and the conductive film and the oxidation prevention film are formed; the etching process is the aforementioned oxidation The prevention film is etched so that only a certain part of the surface of the conductive film is exposed; in the removal process, the oxidation prevention film is used as a masking film, and after the isolation insulating film is formed on the exposed portion of the surface of the conductive film, the oxidation prevention film is removed; A gate formation process uses an isolation insulating film as a masking film, and the aforementioned conductive film is etched to form a first gate; a second gate insulation film formation process is performed on the first gate including the two sidewalls of the first gate. A second gate insulating film is formed on a gate insulating film; a second gate electrode forming process is to form a second gate electrode on a certain part of the tenth gate insulating film that includes the two edges of the isolation insulating film, so that the aforementioned isolation and insulation Only a certain part of the surface of the central portion of the film is exposed; and the separation process is to selectively etch the other isolation insulating film and the aforementioned first gate to separate The first gate electrode is positioned so that only a certain portion of the surface of the substrate is positioned below the surface exposed portion of the isolation insulating film. In order to achieve the stated purpose, the second embodiment of the present invention includes: a conductive film and an emulsification prevention film formation process, which are sequentially formed on a semiconductor substrate provided with a first gate insulating film, and Anti-oxidation film; the "engraving process" is to engrav the aforementioned anti-oxidation film so that only a certain part of the surface of the aforementioned conductive film is exposed;-^ n ^^^^ 1 n I t ml (Please read the precautions on the back before filling (This page) 卞-Γ i- V. Description of the invention (9 Removal process' The above-mentioned oxidation prevention film is used as a masking film, and after the isolation insulating film is formed on the surface exposed portion of the aforementioned conductive film, the foregoing oxidation prevention film is removed; ( Please read the precautions on the back before filling in this page. J The first closed electrode formation project is to use the aforementioned isolation and insulation film as a masking film: the conductive film is engraved to form the first gate electrode; the second gate insulation film is formed A project is formed on the first gate insulating film including the two side walls of the first closed electrode to form a second open insulating film; a first gate formation project is performed on the second second surrounding film including the isolation insulating film -A fixed portion of the insulating film forms a second open electrode; and a separation project is to selectively etch the second gate, the isolation insulating film, and the first gate to separate the first and second gates, respectively, And π 'so that a certain portion is exposed on the surface of the substrate below the center portion of the second gate electrode. At this time, the etching process of the oxidation preventing film is performed so as to include a certain amount of the surrounding area including the source region forming portion. A part of the surface of the aforementioned conductive film is exposed in some fields. When printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to manufacture non-electrical semiconductor components as described above, the two first gates adjacent to the source field are mutually made. Attach to form a large island shape, and then in this state, separate the source region forming part at the center through the etching process, thereby performing the first gate formation process, so there is no difficulty in the progress of the photo-etching process. The line width of the first gate is made smaller than the size set in accordance with the design rules. Moreover, the line width of the first gate placed on the side connected to the source area From the insulating film, no bird's beak, and the bird's beak generated only in the first set on a peripheral side of the gate insulating film of the separator, whereby can 13- 405168 A7
經濟部智慧財產局員工消費合作社印製 因鳥嘴狀而增加第一閘極長度減低到最小之同時，可使第 —閘極間之隔件減少，而達到實現小的存儲單元。 〔發明之實施形態〕 以下，說明本發明之實施形態。 本發明，係於形成非依電性半導體元件之第一閘極時 ’開始時並不把第一閘極製作成分離形態，而是製作成一 個大島形態之後，使用蝕刻工程，以源極領域為中心將之 互相分離’以防止第一閘極之總長度超出設計規則之長度 ，藉此煤求存儲單元之高積趙化者，茲參照第1圖乃至第4 圖具體說明如下》 在此，第1圖係依據本發明第一實施例的非依電性半 導雜元件之構造斷面囷；第2圖（A)至第2圓（G)，係顯示第 1圖之非依電性半導體元件的製造方法之工程順序圖；第3 圖，係依據+發明第二實施例的非依電性半導體元件之構Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Increasing the length of the first gate due to the bird's beak can be reduced to a minimum, and the spacer between the first gate can be reduced to achieve a small storage unit. [Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described. In the present invention, when the first gate of the non-dependent semiconductor element is formed, the first gate is not made into a separated form at the beginning, but is formed into a large island form, and then the etching process is used to form the source field. Separate them from each other as the center 'to prevent the total length of the first gate electrode from exceeding the length of the design rule, so that those who seek to accumulate high storage capacity of the storage unit will refer to Figures 1 to 4 for details. Fig. 1 is a structural cross section 的 of a non-electrically-dependent semiconducting element according to the first embodiment of the present invention; Figs. 2 (A) to 2 (G) show non-electrical-dependent components of Fig. 1 Process sequence diagram of a method for manufacturing a semiconductor device; FIG. 3 is a diagram of the structure of a non-electrical semiconductor device according to a second embodiment of the invention +
‘I 造斷面圊；第4圖（A)至第4圖（G)，係顯示第3圖之非依電 性半導體元件的製造方法之工程順序圖。 首先，說明本發明之第一實施例。 如第1圖所示，具有分離閘型構造之依據本發明的非 依電性半導體元件，係形成較大型之形狀，其在半導體基 板200上之有源極領域形成有第一閘絕緣膜2〇2 ;在該第一 閘絕緣膜202上之一定部分形成有第一閘極2〇4a，以便透 過源領域216互相隔離一規定間隔；在該第一閘極2〇4a上 形成有隔離絕緣膜210 ;在包含前述第一閘極204a之外圍 的一側面之第一閘絕緣膜202上，為了使資料消除而形成 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -14- —^1' nt^l 111 HI ϋϋ In I hi ^^^1 «^^^1 n^i n^i (請先閲讀背面之注$項再填寫本頁) A7‘I manufacture cross section 圊; FIGS. 4 (A) to 4 (G) are process sequence diagrams showing a method for manufacturing a non-electrical semiconductor device shown in FIG. 3. First, a first embodiment of the present invention will be described. As shown in FIG. 1, the non-electrostatic semiconductor element according to the present invention having a split gate type structure is formed in a relatively large shape, and a first gate insulating film 2 is formed in the source region on the semiconductor substrate 200. 〇2; a first gate electrode 204a is formed on a certain part of the first gate insulating film 202 so as to be isolated from each other by a predetermined interval through the source region 216; an isolation insulation is formed on the first gate electrode 204a Film 210; on the first gate insulating film 202 including one side of the periphery of the first gate electrode 204a, for the purpose of erasing data, the paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -14 -— ^ 1 'nt ^ l 111 HI ϋϋ In I hi ^^^ 1 «^^^ 1 n ^ in ^ i (Please read the note on the back before filling this page) A7
A7 405J B7 五、發明説明（η ) n n —J I H Ί! n n I 界-- (請先閲讀背面之注意事項再填寫本頁) 有第二閘絕緣膜（或隧道絕緣膜）212 ;在隔離絕緣膜210上 之一定部分及第二閘絕緣膜之一定部分，形成有第二閘極 214a;被配置成在同一平面上互相隔離一規定間隔之第一 閘極204a ’係共同連結至一形成在基板2〇〇内部之源極領 域216;形成在第一閘極2〇4a下部之通道領域及形成在第 二閘極214a下部之通道領域，係具有在基板2〇〇上互相串 聯連結之構造。此時，前述隔離絕緣膜21〇，：並不在與源 極領域216鄰接之一邊形成鳥嘴狀丨，而是僅在相反側形成 烏嘴狀I。 於第1圖中，由於烏嘴I僅形成在一置在第一閘極204a 上側的隔離絕緣膜之一側，所以第一閘極2〇4a本身之線寬 A減短’進而可實現存儲單元之高積體化。 於第1圖中，符號11係表示工程進行中開始設定的第 一閘極204af總長度；符號12係顯示工程進行完了以後因 烏嘴狀I之產生而增加第一閘極2〇4a之長度的狀態；符號X 係顯示成為第二閘極214a之選擇電晶趙之閘寬度。 因此，前述構造之非依電性存儲單元，一如第2圖（A) 乃至第2圖（G)所示’係經過以下七階段來製造。 經濟部智慧財產局員工消費合作社印製 第一階段如第2圖（A)所示，於半導體基板2〇〇上之一 定部分形成場氧化膜’定義（界定）元件分離領域與活動領 域之後，僅在基板200上之活動領域選擇性地形成厚度7〇 〜150A之第一閘絕緣膜202 » 第二階段如第2圖（B)所示’為了形成一作為漂浮閘使 用之第一閘極’而在第一閘絕緣膜202上形成厚度1〇〇〇〜 本紙張尺度適用中國國家榡準（CNS ) M規格（21〇X297公釐） -15- 405168 at B7 五、發明説明（12 ) 2000A之多晶矽材質之第一導電性膜204，進而在其上依 次形成氮化膜材質之氧化防止臈206»此時，氧化防止膜2〇6 之厚度為200〜1500A。 (請先閲讀背面之注意事項再填寫本頁) 第三階段如第2圖（C)所示，為了以源極領域為中心使 鄰接著之第一閘極互相附著以作成一個大島形狀，而在氧 化防止膜206上形成感光膜圖案208，以便源極領域形成部 及其周圍之規定領域之部分（圖中以符號U標記之部分）之 氧化防止膜206表面露出’進而將感光膜圖案2〇8當作遮覆 膜蝕刻氧化防止膜206。如此來界定第一閘極形成部的話 ’在第5階段形成之向第·一閘極的斷面方向之長度則從第6 圖（C)之“ Α1”變成“ 11”之尺寸，所以具有可不受光蝕 刻工程之進行的影響而輕易進行蝕刻工程之優點。 第四階段如第2圖（D)所示’係去除感光膜圖案，將氧 化防止膜206當做遮覆膜施行氧化工程。其結果，僅在未 被氧化防止膜206所保護之部分，選擇性地形成厚度1〇〇〇 〜2000 Α之隔離絕緣膜210。 經濟部智慧財產局員工消費合作社印製 第五階段為：如第2圖（E)所示，去除氧化防止膜2〇6 ’將1¾離絕緣膜210當做遮覆膜乾触刻第一導電性膜2〇4， 以形成多晶矽材質之第一閘極204a。此時，將第一閉極2〇4a 作成具有一比由形成在隔離絕緣膜3 10兩邊緣側的烏嘴狀 所初始設定的11長度稍微增加之長度12 ^其次，在包含隔 離絕緣膜210及第一閘極204a之第一閘絕緣膜2〇2上形成厚 度200〜400A之第二閘絕緣膜（或隧道絕緣膜）212。此時 ，第二閘絕緣膜212可形成得具有熱氧化膜之單層構造， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 405168 五、 經濟部智慧財產局員工消費合作社印製 發明説明（u 也可形成得積層熱氧化膜及CVD氧化膜之構造。若是隔 離絕緣膜210時，由於其厚度比第二閘絕緣膜212還厚，所 以在此並未圓示形成在其上之絕緣膜的厚度。 第六階段如第2圖（F)所示，為了形成作為控制閘及選 擇電晶體之閘門使用的第二閘極，而在包含隔離絕緣膜2 i 〇 之第二閘絕緣膜212上形成多晶矽或聚矽化物材質之厚度 1000〜2000Λ之第二導電性膜，進而在其上形成一用來界 定第二閘形成部之感光膜圖案208之後，將之作為遮覆膜 而乾式姓刻第二導電性膜。其結果，將隔離絕緣部21〇之 中央部露出一定部分，並在同其兩邊緣部連結之第二閉絕 緣膜212上之一定部分形成多晶矽或聚矽化物材質之第二 閘極214a。 第七階段如第2圖（G)所示’係去除感光膜圊案2〇8a， 在包含第一的極214a，在包含第二閘極214a及隔離絕緣膜 210之第二閘絕緣膜上形成感光膜之後，將之選擇触刻以 形成感光膜圖案208b，以便隔離絕緣臈210之中央部表面 所露出之一定部分。將用以施行高濃度之雜質離子植入工 程而形成之前述感光膜圖案208b作為遮覆膜，藉由自己匹 配方式蝕刻隔離絕緣膜210及第一閘極204a，以便閘絕緣 膜202表面露出一定部分；進而使第一閘極204a分離成在 基板200上互相隔離一規定間隔。接著，將前述感光膜圖 案208b作為遮覆膜，在閘絕緣膜202之表面露出部上離子 植入高濃度之雜質以在基板200内形成源極領域216及汲極 領域（未圖示）之後，去除感光膜圊案208b，完成本工程之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I-------I-I.-衣^-- (請先閲讀背面之注項再填寫本頁) -訂 -17- 405168 B；__ 五、發明説明（14 ) 進行。 當如此地進行工程時，由於第一閘極204a之形成時不 受光蝕刻工程之限制，因此在存儲單元之製造時，為考量 因烏嘴狀而使第一閘極204a之長度會變大事，故而可在工 :程開始階段調整第一閘極204a之總長度。 又，在此情況下，在與源極領域216連結的一邊之第 一閘極204a上側之隔離絕緣膜210上不會產生烏嘴狀I，而 僅在與其外圍側之第一閘極204a上的隔離絕緣膜210產生 烏嘴狀I，藉此可使第一閘極204a之各線寬A與第一閘極 204a間之隔件間隔小於原有之隔件間隔。因此，成為第二 閘極214a之選擇電晶體之閘寬度（第1圖中用X表示之部分） 即使在同一平面上更延長到因第一閘極104a之鳥嘴狀而縮 短之部分，第一閘極204a之線寬也會變成小於習知之線寬 ’所以可減短第一、第二閘極204a、214a之總長度，而能 ιι 實現小存儲單元。 以下，說明關於本發明之第二實施例。 經濟部智慧財產局員工消費合作社印製 關於第二實施例之非依電性半導體元件，一如第3圖 之斷面圖所示，除了以完成存儲單元製造工程之狀態，將 用來擔負控制閘及選擇電晶體之閘任務之第二閘極314a形 成在全表面以替代形成在隔離絕緣膜310上之一定部分以 外’餘則與第一實施例相同，所以在此處省略對於其基本 構造之說明。 第3圖之情況也將鳥嘴狀I僅形成在一置在第一閘極 3〇4a上侧的隔離絕緣膜310之一側，因此可使第一閘極304a -18- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X2.97公釐） 五、發明説明（15) M5168 A7 B7 經濟部智慧財產局員工消費合作社印製 本身之線寬A減短，從而可實現存儲單元之高積體化。 前述圖中符號11係表示工程進行中開始設定的第一閘 極3 04a之總長度；符號12係表示工程進行完了以後因烏嘴 狀I之產生而增加第一閘極304a之長度；符號X係表示成為 第二閘極314a之選擇電晶體之閘寬度。 因此，前述構造之非依電性存儲單元，係如第4圖 至第4圚（G)之工程順序圓所示，經過以下七階段來製造之 。在此，為求方便，乃以不同於第一實施例之工程為中心 而簡略說明其製造方法。 第一階段如第4圊（A)所示，在半導體基板300上之有 限領域形成第一閘絕緣膜302。 第二階段為：如第4圓（B)所示，在第一閘絕緣膜2〇2 上依次形成多晶矽材質之第一導電性膜3〇4及氮化膜材質 之氧化防止膜306。 *1 第三階段如第4圖（c)所示，為了以源極領域為中心使 鄰接著之第一閘極互相附著以形成一個大島形狀，而在氧 化防止膜306上形成感光膜圖案3〇8，以便露出該源極領域 形成部及其周圍之規定領域的部分（在圖上，用符號11標 s己之部分）之氧化防止膜3〇6表面，進而將感光膜圖案3〇8 作為遮覆膜姓刻氧化防止膜3〇6。 第四階段如第4圖（D)所示，去除感光膜圖案3〇8，將 氧化防止膜306作為遮覆膜施行氧化工程，並只在未被氧 化防止膜306所保護之部分選擇性地形成隔離絕緣膜31〇。 第五階段如第4圖（Ε)所示，去除氧化防止膜3〇6，將 (請先閲讀背面之注意事項再填寫本頁) .丨农· -訂 0 H —^1 -19- A7 B7 _4051β8 五、發明説明（μ ) 第一導電性膜304乾蝕刻以形成多晶矽或聚矽化物材質之 第一閘極304a,進而在其全面形成熱氧化膜之單層構造或 積層熱氧化膜與CVD氧化膜之構造的第二閘絕緣膜（或隧 道絕緣膜）312 »此時，第一閘極3〇4a被製作成具有比由形 成在隔離絕緣膜31 〇兩邊緣側之烏嘴狀所開始設定之丨丨之 長度稍微增加的長度12 » 第六階段如第4圖（F)所示，在包含隔離絕緣膜31〇之 第二閘絕緣膜312上形成多晶矽或聚矽化物材質之第二導 電性膜，進而在其上面形成一用來界定第二閘極形成部之 感光膜圖案308a後，將之作為遮覆膜乾蝕刻第二導電性膜 。其結果，在包含隔離絕緣膜310之其周圍之第二閘絕緣 膜312上的一定部分，形成多晶矽或聚石夕化物材質之第二 閘極314a。 第七階舉如第4圖（G)所示，去除感光膜圖案3〇ga，在 包含第二閘極314a之第二閘絕緣膜312上形成感光膜後， 將之選擇蚀刻以形成感光膜圖案308b，以便第二閘極314a 之中央部表面露出一定部分。將感光膜圖案3〇8b作為遮覆 膜’藉自己匹配方式來蚀刻隔離絕緣膜310及第一閘極3〇4a ，以便閘絕緣膜302表面露出一定部分，進而在基板3〇〇上 使第一、第二閘極304a、314a分別分離。其次，將感光膜 圖案3 08b作為遮覆膜，把高濃度之雜質離子植入於閘絕緣 膜302表面露出部上，藉此在基板300内形成源極領域316 及汲極領域（未圖示）之後’去除感光膜圖案308b，而完成 本工程。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 泯· 訂 經濟部智慧財產局員工消費合作社印製 -20- 17 所示，在製造非依電性存儲單元時，也與第一實 施例1同時，可將第—閘極3()43之各線寬度及其總長形成 得小於原有之線寬度，因此可謀求比習知者小之存儲單元 〔發明之效果〕 如上所說明，本發明具有如下之效果。 ⑴透過工程變更，ϋ由光蚀刻工錢第„閘極之線 寬度具有容許之尺寸以下，藉此可將第一閘極之總長度形 成得小於原有之大小； (2)僅在互相分離的隔離絕緣膜之一側形成烏嘴狀， 因此可將因烏嘴狀而增加第一閘極之線寬度之壓縮至最小 ，從而可謀高積體化之存儲單元。 〔圖式之簡單說明〕 第1圓係顯示依據本發明第一實施例之非依電性半導 體元件的構造斷面圖； 第2圊（Α)〜第2圖（G)係顯示第！圖非依電性半導體元 件之製造方法的工程順序圖； 第3圖係顯示依據本發明第二實施例之非依電性半導 體元件之構造斷面圖； 第4圖（Α)〜第4圖（G)係顯示第3圖非依電性半導體元 件之製造方法的工程順序圖； 第5圖係顯示習知非依電性半導體元件之構造斷面圖； 第6圖（Α)〜第6圖（G)係顯示第5圖非依電性半導體元 件之製造方法之工程順序圖。 A7 405168 B7 五、發明説明（18 ) 元件標號對照 202，302...第一閘絕緣膜 204a，304a·.·第一閘極 :210，310…隔離絕緣膜 212，312...第二閘絕緣膜 214a，314a··.第二閘極 ϋ^^ι· —flu^ I — i^i^n ^nv— (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -22-A7 405J B7 V. Description of the invention (η) nn —JIH Ί! Nn I boundary-(Please read the precautions on the back before filling this page) There is a second gate insulation film (or tunnel insulation film) 212; A certain portion of the film 210 and a certain portion of the second gate insulating film are formed with a second gate electrode 214a; the first gate electrodes 204a configured to be isolated from each other at a predetermined interval on the same plane are commonly connected to one formed at The source region 216 inside the substrate 2000; the channel region formed at the lower portion of the first gate 204a and the channel region formed at the lower portion of the second gate 214a have a structure in which the substrate 2000 is connected in series with each other . At this time, the aforementioned isolation insulating film 21o: does not form a bird's beak on one side adjacent to the source region 216, but forms a beak-like I only on the opposite side. In FIG. 1, since the black mouth I is formed only on one side of the insulating insulating film placed on the upper side of the first gate 204a, the line width A of the first gate 204a itself is shortened, thereby enabling storage. High accumulation of units. In the first figure, the symbol 11 indicates the total length of the first gate 204af that is set during the construction process; the symbol 12 indicates that the length of the first gate 204a is increased due to the occurrence of the spiral mouth I after the project is completed. The symbol X indicates the width of the gate of the selected transistor Zhao which becomes the second gate 214a. Therefore, as shown in FIG. 2 (A) and FIG. 2 (G), the non-electrically-dependent memory cell of the foregoing structure is manufactured through the following seven stages. As shown in Figure 2 (A), the first stage of printing by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is to form a field oxide film on a certain portion of the semiconductor substrate 2000. After defining (defining) the field of component separation and the field of activity, The first gate insulating film 202 with a thickness of 70-150A is selectively formed only in the active area on the substrate 200. »The second stage is shown in FIG. 2 (B). In order to form a first gate electrode used as a floating gate 'And the thickness of the first gate insulating film 202 is 1000 ~ This paper size is applicable to China National Standard (CNS) M specification (21 × 297mm) -15- 405168 at B7 V. Description of the invention (12) The first conductive film 204 made of 2000A polycrystalline silicon is further formed thereon with an oxidation prevention film 206 of a nitride film material. At this time, the thickness of the oxidation prevention film 206 is 200 to 1500A. (Please read the precautions on the back before filling in this page.) The third stage is shown in Figure 2 (C). In order to make the adjacent first gates adhere to each other around the source area to form a large island shape, A photosensitive film pattern 208 is formed on the oxidation prevention film 206 so that the surface of the oxidation prevention film 206 of the source region formation portion and a predetermined area around the portion (the part marked with a symbol U in the figure) is exposed, thereby exposing the photosensitive film pattern 2 〇8 is used as a masking film to prevent the oxidation oxidation film 206. If the first gate electrode forming portion is defined in this way, the length of the section direction of the first gate electrode formed in the fifth stage is changed from "Α1" in Fig. 6 (C) to "11". The advantage of easily performing the etching process without being affected by the progress of the photo-etching process. In the fourth stage, as shown in FIG. 2 (D) ', the photosensitive film pattern is removed, and the oxidation prevention film 206 is used as a masking film to perform an oxidation process. As a result, the isolation insulating film 210 having a thickness of 1000 to 2000 A is selectively formed only on the portion not protected by the oxidation prevention film 206. The fifth stage of printing by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is: as shown in FIG. 2 (E), the oxidation prevention film 206 'is removed, and 1¾ off the insulating film 210 is used as a masking film to dry-etch the first conductivity. The film 204 is formed to form a first gate 204a made of polycrystalline silicon. At this time, the first closed electrode 204a is made to have a length 12 ^ slightly longer than the initial length of 11 set by the nipple shape formed on both edge sides of the insulating insulating film 3 10, and secondly, the insulating insulating film 210 is included. A second gate insulating film (or tunnel insulating film) 212 having a thickness of 200 to 400 A is formed on the first gate insulating film 202 of the first gate electrode 204a. At this time, the second gate insulating film 212 can be formed into a single-layer structure with a thermal oxide film. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 405168 5. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The description of the invention (u can also be formed as a structure of a laminated thermal oxide film and a CVD oxide film. If the isolation insulating film 210 is thicker than the second gate insulating film 212, it is not shown here as being formed on it. In the sixth stage, as shown in FIG. 2 (F), in order to form a second gate used as a control gate and a gate for selecting a transistor, a second gate including an isolation insulating film 2 i 〇 is formed. A second conductive film having a thickness of 1000 to 2000 Å made of polycrystalline silicon or polysilicide is formed on the gate insulating film 212, and a photosensitive film pattern 208 defining the second gate forming portion is formed thereon, and then used as a mask. The second conductive film is engraved dry. As a result, the central portion of the isolation insulating portion 21 is exposed to a certain portion, and a polycrystalline portion is formed on a certain portion of the second closed insulating film 212 connected to both edge portions thereof. The second gate 214a made of silicon or polysilicide. In the seventh stage, as shown in FIG. 2 (G), the photoresist film removal process 208a is included, and the first gate 214a and the second gate are included. After forming a photosensitive film on the second gate insulating film of 214a and the isolation insulating film 210, it is selectively etched to form a photosensitive film pattern 208b so as to isolate a certain portion of the surface of the central portion of the insulating film 210 that is exposed. The aforementioned photosensitive film pattern 208b formed by the impurity ion implantation process of a concentration is used as a masking film, and the isolation insulating film 210 and the first gate electrode 204a are etched by the matching method, so that a part of the surface of the gate insulating film 202 is exposed; A gate 204a is separated into a predetermined interval from each other on the substrate 200. Next, using the aforementioned photosensitive film pattern 208b as a masking film, a high-concentration impurity is ion-implanted on the exposed portion of the surface of the gate insulating film 202 to form a substrate 200 After the source region 216 and the drain region (not shown) are formed inside, the photosensitive film case 208b is removed, and the paper size of this project completed is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) I --- ---- II.- 衣 ^-(Please read the note on the back before filling out this page) -Order-17- 405168 B; __ V. Description of the invention (14). When the project is carried out in this way, The formation of the first gate electrode 204a is not restricted by the photo-etching process. Therefore, in the manufacture of the memory cell, in order to consider that the length of the first gate electrode 204a will become large due to the burr shape, it can be used at the beginning of the process: Adjust the total length of the first gate electrode 204a. Also, in this case, a corrugated I will not be formed on the isolation insulating film 210 on the upper side of the first gate electrode 204a on the side connected to the source region 216, and only The insulating insulating film 210 on the first gate electrode 204a on the peripheral side generates a corrugated I, so that the distance between each line width A of the first gate electrode 204a and the first gate electrode 204a is smaller than the original one. Piece interval. Therefore, the gate width of the selection transistor of the second gate electrode 214a (the portion indicated by X in the first figure) is extended to the portion shortened by the bird's beak shape of the first gate electrode 104a even on the same plane. The line width of a gate 204a will also become smaller than the conventional line width, so the total length of the first and second gates 204a and 214a can be shortened, and a small memory cell can be realized. Hereinafter, a second embodiment of the present invention will be described. The consumer electronics cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the non-electrical semiconductor components of the second embodiment, as shown in the sectional view of FIG. 3, except for the state of completing the manufacturing process of the storage unit, which will be used to control The gate and the second gate electrode 314a of the transistor selection task are formed on the entire surface to replace a certain portion formed on the isolation insulating film 310. The rest is the same as the first embodiment, so the basic structure is omitted here. Description. In the case of FIG. 3, the beak-shaped I is also formed only on one side of the insulating insulating film 310 placed on the upper side of the first gate electrode 304a, so that the first gate electrode 304a can be made. China National Standard (CNS) A4 specification (210X2.97 mm) V. Description of invention (15) M5168 A7 B7 The line width A printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is reduced, so that the height of the storage unit can be achieved Integrated. In the figure above, the symbol 11 indicates the total length of the first gate 3 04a that is set during the construction process; the symbol 12 indicates that the length of the first gate 304a is increased due to the occurrence of the spiral mouth I after the project is completed; the symbol X Represents the gate width of the selection transistor which becomes the second gate electrode 314a. Therefore, the non-electrically-dependent memory cell of the foregoing structure is manufactured as shown in the engineering sequence circles in FIGS. 4 to 4 (G), and is manufactured through the following seven stages. Here, for the sake of convenience, the manufacturing method will be briefly described focusing on a process different from the first embodiment. In the first stage, as shown in (4) (A), a first gate insulating film 302 is formed in a limited area on the semiconductor substrate 300. In the second stage, as shown in the fourth circle (B), a first conductive film 30 made of polycrystalline silicon and an oxidation prevention film 306 made of a nitride film are formed on the first gate insulating film 200 in this order. * 1 In the third stage, as shown in FIG. 4 (c), a photosensitive film pattern 3 is formed on the oxidation prevention film 306 in order to make adjacent first gates adhere to each other to form a large island shape with the source region as the center. 〇8, so as to expose the surface of the source region forming part and a predetermined area around the area (the part marked with the symbol 11 on the figure) of the oxidation preventing film 306 surface, and then the photosensitive film pattern 3〇8 The anti-oxidation film 3 was etched as a masking film. In the fourth stage, as shown in FIG. 4 (D), the photosensitive film pattern 30 is removed, and the oxidation prevention film 306 is used as a masking film to perform an oxidation process, and only the portion not protected by the oxidation prevention film 306 is selectively An isolation insulating film 31 is formed. In the fifth stage, as shown in Figure 4 (E), remove the oxidation prevention film 3〇6, (please read the precautions on the back before filling in this page). Nong · -Order 0 H — ^ 1 -19- A7 B7 _4051β8 V. Description of the Invention (μ) The first conductive film 304 is dry-etched to form a first gate electrode 304a made of polycrystalline silicon or polysilicide, and a single-layer structure or a laminated thermal oxide film is formed on the entire surface of the first conductive film 304. CVD oxide film structure of the second gate insulating film (or tunnel insulating film) 312 »At this time, the first gate electrode 304a is made to have a corrugated shape formed on both edge sides of the insulating insulating film 31 〇 Initially set the length of the slightly increased length 12 »In the sixth stage, as shown in FIG. 4 (F), a polycrystalline silicon or polysilicide material is formed on the second gate insulating film 312 including the isolation insulating film 31. After the second conductive film is formed thereon with a photosensitive film pattern 308a for defining a second gate forming portion, the second conductive film is used as a masking film to dry-etch the second conductive film. As a result, a second gate electrode 314a made of polycrystalline silicon or polysilicon material is formed on a certain portion of the second gate insulating film 312 including the isolation insulating film 310 around the second gate insulating film 312. In the seventh step, as shown in FIG. 4 (G), the photosensitive film pattern 30ga is removed, and after a photosensitive film is formed on the second gate insulating film 312 including the second gate electrode 314a, it is selectively etched to form a photosensitive film. Pattern 308b so that a portion of the surface of the central portion of the second gate electrode 314a is exposed. Using the photosensitive film pattern 3008b as a masking film, the isolation insulating film 310 and the first gate electrode 304a are etched by their own matching method, so that a certain portion of the surface of the gate insulating film 302 is exposed, and then the first First, the second gate electrodes 304a and 314a are separated. Next, the photosensitive film pattern 3 08b is used as a masking film, and high-concentration impurity ions are implanted on the exposed portion of the surface of the gate insulating film 302, thereby forming a source region 316 and a drain region (not shown) in the substrate 300. ) After that, the photosensitive film pattern 308b is removed, and the process is completed. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) 泯 · Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs as shown in -20-17, When manufacturing a non-dependent memory cell, at the same time as the first embodiment, the line width of the first gate 3 () 43 and its total length can be formed smaller than the original line width, so it can be compared with the conventional one. [The effect of the invention] As described above, the present invention has the following effects. ⑴ Through engineering changes, ϋThe width of the gate line of the photoetcher is less than the allowable size, so that the total length of the first gate can be made smaller than the original size; (2) One side of the isolation insulating film is formed into a corrugated shape, so the compression of increasing the line width of the first gate due to the corrugated shape can be minimized, so that a highly integrated storage unit can be achieved. [Simplified description of the drawing] The first circle is a cross-sectional view showing the structure of a non-electrostatic semiconductor element according to the first embodiment of the present invention; the second (A) to the second figure (G) show the first! Process sequence diagram of manufacturing method; FIG. 3 is a cross-sectional view showing a structure of a non-electrical-resistant semiconductor element according to a second embodiment of the present invention; and FIGS. 4 (A) to 4 (G) are diagrams showing 3 The engineering sequence diagram of the manufacturing method of the non-electrolytic semiconductor element; FIG. 5 is a cross-sectional view showing the structure of a conventional non-electrolytic semiconductor element; FIGS. 6 (A) to 6 (G) show the fifth Figure Engineering sequence diagram of manufacturing method of non-electrical semiconductor element. A7 405168 B7 、 Explanation of the invention (18) Comparison of component numbers 202, 302 ... First gate insulating film 204a, 304a ... First gate: 210, 310 ... Isolation insulating film 212, 312 ... Second gate insulating film 214a 314a ··. The second gate ϋ ^^ ι · —flu ^ I — i ^ i ^ n ^ nv— (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm) -22-