KR19990059114A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
- Publication number
- KR19990059114A KR19990059114A KR1019970079311A KR19970079311A KR19990059114A KR 19990059114 A KR19990059114 A KR 19990059114A KR 1019970079311 A KR1019970079311 A KR 1019970079311A KR 19970079311 A KR19970079311 A KR 19970079311A KR 19990059114 A KR19990059114 A KR 19990059114A
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- South Korea
- Prior art keywords
- semiconductor device
- manufacturing
- semiconductor substrate
- gas
- silicon nitride
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 아이솔레이션 공정시, 산소의 확산 방지 마스크로 사용되는 실리콘나이트라이드층의 형성으로 인한 반도체 기판의 스트레스를 감소시키는 방법에 관한 것임.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of reducing stress of a semiconductor substrate due to formation of a silicon nitride layer used as an oxygen diffusion prevention mask during an isolation process of a semiconductor device.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
반도체 소자의 아이솔레이션 공정시 실리콘나이트라이드층을 형성함에 있어서 반도체 기판이 스트레스를 받게되고, 이러한 스트레스가 이 후의 고온 공정에서 반도체 기판에 결함을 유발시키는 문제점이 있음.The semiconductor substrate is stressed in forming the silicon nitride layer during the isolation process of the semiconductor device, and such stress causes a defect in the semiconductor substrate in a subsequent high temperature process.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
반도체 소자의 아이솔레이션 형성시 플라즈마를 이용하여 산소의 확산 방지 마스크로 사용되는 실리콘나이트라이드층을 증착함.In the formation of the isolation of the semiconductor device, a silicon nitride layer used as a mask for preventing diffusion of oxygen is deposited by using plasma.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 아이솔레이션 공정.Isolation process of semiconductor device.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 아이솔레이션(isolation) 공정시, 산소(oxygen)의 확산 방지 마스크(mask)로 사용되는 실리콘나이트라이드(silicon nitride)층의 형성으로 인한 반도체 기판의 스트레스(stress)를 감소시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, in the isolation process of a semiconductor device, a semiconductor due to the formation of a silicon nitride layer used as an oxygen diffusion prevention mask. A method of reducing stress in a substrate is provided.
메모리 반도체 소자의 집적도 증가가 필연적으로 요구됨에 따라 아이솔레이션 공정 중의 스트레스 제거는 소자의 특성과 수율 증가에 중요한 영향을 미치고 있다. 특히, 반도체 소자의 아이솔레이션 공정시 실리콘나이트라이드층을 형성함에 있어서 반도체 기판이 스트레스를 받게되고, 이러한 스트레스가 이 후의 고온 공정에서 반도체 기판에 결함을 유발시키는 문제점이 있다.As the increase in the density of memory semiconductor devices is inevitably required, stress elimination during the isolation process has an important effect on increasing the device characteristics and yield. In particular, there is a problem in that the semiconductor substrate is stressed in forming the silicon nitride layer during the isolation process of the semiconductor device, and such stress causes a defect in the semiconductor substrate in a subsequent high temperature process.
도면을 참조하여 종래의 기술에 의한 반도체 소자의 제조 방법을 설명하고자 한다.With reference to the drawings will be described a method of manufacturing a semiconductor device according to the prior art.
도 1은 종래의 기술에 의한 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도로써, 반도체 기판(11) 상부에 확산 방지막으로 실리콘나이트라이드(Si3N4)층(12)을 증착하고, 선택된 영역을 식각하여 패터닝한 후, 노출된 반도체 기판(11)에 필드산화막(13)을 형성한 단면도이다. 그런데 실리콘나이트라이드층(12) 증착시 실리콘나이트라이드층(12)과 반도체 기판(11)의 재질 특성상 반도체 기판(11)의 표면은 스트레스를 받게되고, 이 부분은 후속 열공정에서 손상(damage)을 입어 결함(defect)을 유발시킨다. 이러한 반도체 기판은 GOI 특성 열화 및 접합부의 누설 전류 증가(junction leakage current)를 초래하여 소자의 특성 저하 및 수율을 감소 시킨다.1 is a cross-sectional view illustrating a method of fabricating a semiconductor device according to the related art, in which a silicon nitride (Si 3 N 4 ) layer 12 is deposited on the semiconductor substrate 11 as a diffusion barrier and selected. After etching and patterning a region, a cross-sectional view of the field oxide film 13 is formed on the exposed semiconductor substrate 11. However, when the silicon nitride layer 12 is deposited, the surface of the semiconductor substrate 11 is stressed due to the material properties of the silicon nitride layer 12 and the semiconductor substrate 11, and this portion is damaged during subsequent thermal processes. To cause a defect. Such semiconductor substrates result in degradation of GOI characteristics and junction leakage current of the junction, thereby degrading device characteristics and yields.
본 발명은 확산 방지막으로 사용되는 실리콘나이트라이드층 증착시 반도체 기판과의 계면에 발생하는 스트레스를 방지하여 소자의 특성 및 수율을 향상시키는데 그 목적이 있다.An object of the present invention is to prevent stress generated at the interface with a semiconductor substrate during deposition of a silicon nitride layer used as a diffusion barrier, thereby improving device characteristics and yield.
상술한 목적을 달성하기 위한 반도체 소자의 제조 방법은, 히터가 부착되고 회전이 가능한 고주파 플라즈마 챔버 내의 서셉터 상부에 실리콘나이트라이드층을 증착하기 위한 반도체 기판을 장착하는 단계와, 저온 영역에서 실리콘 소오스 가스 및 질소 소오스 가스를 반응 가스로 유입시키고, 고주파를 인가하여 상기 반응 가스 플라즈마를 발생시킴으로써 상기 반도체 기판 상부에 실리콘나이트라이드층을 증착하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A semiconductor device manufacturing method for achieving the above object comprises the steps of mounting a semiconductor substrate for depositing a silicon nitride layer on the susceptor in a high frequency plasma chamber to which the heater is attached and rotatable; And depositing a silicon nitride layer on the semiconductor substrate by introducing a gas and a nitrogen source gas into the reaction gas and applying a high frequency to generate the reaction gas plasma.
도 1은 종래의 기술에 의한 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Sectional drawing shown for demonstrating the manufacturing method of the semiconductor element by a prior art.
도 2는 본 발명에 따른 반도체 소자의 제조 방법을 구현하기 위한 플라즈마 챔버의 단면도.2 is a cross-sectional view of a plasma chamber for implementing the method of manufacturing a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
11 : 반도체 기판 12 : 실리콘나이트라이드층11 semiconductor substrate 12 silicon nitride layer
13 : 필드 산화막 21 : 챔버13: field oxide film 21: chamber
22 : 서셉터 23 : 반도체 기판22: susceptor 23: semiconductor substrate
24 : 고주파 인가 장치 25 : 전극24: high frequency application device 25: electrode
26 : 히터26: heater
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2는 본 발명에 따른 반도체 소자의 제조 방법을 구현하기 위한 플라즈마 챔버의 단면도로써, 실리콘나이트라이드층 증착시 종래의 고온 LPCVD를 이용하지 않고, 저온 PECVD(Plasma enhanced CVD)를 이용하여 반도체 기판의 스트레스를 방지 하고자 한다.FIG. 2 is a cross-sectional view of a plasma chamber for implementing a method of manufacturing a semiconductor device according to the present invention, wherein a silicon substrate is deposited using a low temperature PECVD (Plasma enhanced CVD) instead of a conventional high temperature LPCVD. I want to prevent stress.
먼저 도면에 도시된 것과 같이, 챔버(21) 내부의 서셉터(22) 상부에 반도체 기판(23)을 장착한 후, 진공 펌프로 적정한 압력을 유지시킨다. 이후 고주파 인가 장치(24)에 100 W ∼ 400 W의 전력을 인가하여 전극(25)과 반도체 기판(23) 간에 전계를 형성하고, 챔버 내부로 유입된 실리콘 소오스 가스, 즉 사일렌(SiH4) 및 디클로로사일렌(SiCl2H2)와 질소 소오스 가스, 즉 질산(NH3) 및 질소(N2) 반응 가스를 활성화시켜 플라즈마를 발생시킨다. 이 때 실리콘 소오스 가스와 질소 소오스 가스의 화학량론적 비율인 3 : 4 보다 실리콘 소오스 가스가 리치(rich)한 조성을 갖도록 소오스 가스의 유량비를 제어한다. 서셉터(22)는 히터(26)로부터의 열을 반도체 기판(23)으로 전달하여 반도체 기판(23)을 가열시키고, 활성화된 반응 가스는 200 ℃ ∼ 400 ℃의 저온 영역 및 3 Torr 이하의 압력에서 반도체 기판(23)의 상부 표면에 증착된다. 증착되는 실리콘나이트라이드층의 두께 균일도를 위해 서셉터(22)를 회전시킨다. 이 때 반도체 기판(23)과 서셉터(22)는 밀착되어 반응 가스의 흐름이 없으므로 반도체 기판(23)의 뒷면에는 실리콘나이트라이드층이 증착되지 않는다.First, as shown in the figure, the semiconductor substrate 23 is mounted on the susceptor 22 inside the chamber 21, and then a proper pressure is maintained by a vacuum pump. Thereafter, electric power of 100 W to 400 W is applied to the high frequency application device 24 to form an electric field between the electrode 25 and the semiconductor substrate 23, and a silicon source gas introduced into the chamber, that is, silica (SiH 4 ). And dichloroxylene (SiCl 2 H 2 ) and a nitrogen source gas, ie, a nitric acid (NH 3 ) and nitrogen (N 2 ) reaction gas, to generate a plasma. At this time, the flow rate ratio of the source gas is controlled so that the silicon source gas has a richer composition than the stoichiometric ratio of silicon source gas and nitrogen source gas 3: 4. The susceptor 22 transfers heat from the heater 26 to the semiconductor substrate 23 to heat the semiconductor substrate 23, and the activated reaction gas is a low temperature region of 200 ° C. to 400 ° C. and a pressure of 3 Torr or less. At the upper surface of the semiconductor substrate 23. The susceptor 22 is rotated for thickness uniformity of the deposited silicon nitride layer. At this time, since the semiconductor substrate 23 and the susceptor 22 are in close contact with each other and there is no flow of the reaction gas, the silicon nitride layer is not deposited on the back surface of the semiconductor substrate 23.
본 발명은 화학기상증착(CVD) 공정 진행 후 발생하는 스트레스가 소자의 특성 및 수율에 영향을 미치는 모든 화학기상 증착막, 즉, 폴리실리콘(polysilicon)막, 인시투 도프트 폴리실리콘(in-situ doped polysilicon막, CVD 산화(oxide)막, 및 BPSG막 등에 적용할 수 있으며, 열 공정의 손상에 의해 소자 특성이 영향을 받는 금속층의 확산 방지막인 나이트라이드막에도 적용할 수 있다.According to the present invention, all chemical vapor deposition films, that is, polysilicon film, in-situ doped polysilicon (in-situ doped), in which stress generated after a chemical vapor deposition (CVD) process affects device characteristics and yield The present invention can be applied to a polysilicon film, a CVD oxide film, a BPSG film, or the like, and can be applied to a nitride film, which is a diffusion preventing film of a metal layer whose device characteristics are affected by damage to a thermal process.
상술한 바와 같이 본 발명에 의하면, LPCVD 장치에서 실리콘 및 질소 반응 가스 중의 활성화 장벽 에너지가 낮아져 반응 가스 비의 조절에 의해 용이하게 실리콘이 리치(rich)한 막을 형성할 수 있다. 동시에 서셉터와 반도체 기판을 밀착시켜 반도체 기판 뒷면에는 실리콘나이트라이드막이 증착되지 않게 하므로 반도체 기판에 스트레스로 인한 결함 발생을 방지할 수 있다. 또한 후속 공정인 실리콘나이트라이드층 식각 및 필드 산화막 형성시 반도체 기판 내부의 결정 결함 존재 가능성을 낮추게 되어, GOI 특성 및 접합부 누설 전류 특성이 개선되고 소자의 특성 및 수율이 향상되는 탁월한 효과가 있다.As described above, according to the present invention, the activation barrier energy in the silicon and nitrogen reaction gas is lowered in the LPCVD apparatus, so that the silicon-rich film can be easily formed by controlling the reaction gas ratio. At the same time, the susceptor and the semiconductor substrate are closely adhered to each other so that the silicon nitride film is not deposited on the back side of the semiconductor substrate, thereby preventing defects caused by stress on the semiconductor substrate. In addition, it is possible to reduce the possibility of crystal defects in the semiconductor substrate during the subsequent etching of the silicon nitride layer and the formation of the field oxide layer, thereby improving GOI characteristics, junction leakage current characteristics, and improving device characteristics and yield.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970079311A KR100444611B1 (en) | 1997-12-30 | 1997-12-30 | Method for manufacturing semiconductor device to reduce stress of substrate by forming silicon nitride layer using plasma |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970079311A KR100444611B1 (en) | 1997-12-30 | 1997-12-30 | Method for manufacturing semiconductor device to reduce stress of substrate by forming silicon nitride layer using plasma |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990059114A true KR19990059114A (en) | 1999-07-26 |
| KR100444611B1 KR100444611B1 (en) | 2004-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970079311A KR100444611B1 (en) | 1997-12-30 | 1997-12-30 | Method for manufacturing semiconductor device to reduce stress of substrate by forming silicon nitride layer using plasma |
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| Country | Link |
|---|---|
| KR (1) | KR100444611B1 (en) |
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1997
- 1997-12-30 KR KR1019970079311A patent/KR100444611B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR100444611B1 (en) | 2004-11-16 |
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