KR19990059084A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990059084A KR19990059084A KR1019970079281A KR19970079281A KR19990059084A KR 19990059084 A KR19990059084 A KR 19990059084A KR 1019970079281 A KR1019970079281 A KR 1019970079281A KR 19970079281 A KR19970079281 A KR 19970079281A KR 19990059084 A KR19990059084 A KR 19990059084A
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- insulating film
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- high density
- density plasma
- interlayer insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Power Engineering (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 층간 절연막 증착 공정 중에 발생하는 하부 금속 배선의 물리적인 식각을 방지하기 위한 방법에 관한 것임.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for preventing physical etching of a lower metal wiring occurring during an interlayer insulating film deposition process.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
고밀도 플라즈마 방법으로 층간 절연막을 증착하는 공정에서 하부 금속 배선의 상단 모서리 부분이 고밀도 플라즈마에 직접 노출되어 물리적인 식각이 일어나는 문제점이 있음.In the process of depositing the interlayer insulating film by the high density plasma method, there is a problem in that the upper edge portion of the lower metal wiring is directly exposed to the high density plasma to cause physical etching.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
금속 배선 상부에 버퍼 역할을 하는 얇은 절연막을 형성하여, 고밀도 플라즈마 방법으로 층간 절연막을 증착하는 공정에서 발생하는 하부 금속 배선의 물리적인 식각을 방지함.By forming a thin insulating film to act as a buffer on the upper metal wiring, to prevent the physical etching of the lower metal wiring generated in the process of depositing the interlayer insulating film by a high density plasma method.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 층간 절연막 형성 공정.Interlayer insulating film formation process of a semiconductor element.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 층간 절연막 증착 공정 중에 발생하는 하부 금속 배선의 물리적인 식각을 방지하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for preventing physical etching of a lower metal wiring occurring during an interlayer insulating film deposition process.
고밀도 플라즈마 공정 기술은 층간 메움 특성이 개선되고, 일정 비율 이상의 두께까지 증착 공정을 실시하는 경우 하부 패턴의 부분 평탄화가 이루어지는 장점이 있어 많은 반도체 소자의 제조 공정에 적용되고 있다. 그러나 고밀도 플라즈마 방법으로 층간 절연막을 증착하는 공정에서 하부 금속 배선의 상단 모서리 부분이 고밀도 플라즈마에 직접 노출되어 물리적인 식각이 일어나면서 금속 배선에 많은 손상과 동시에 소자의 신뢰성 문제를 야기시키고 있다. 또한 이 부분에서의 식각 문제는 심한 경우 금속 배선의 측면부와 층간 절연막과의 박리 현상을 야기시켜 소자 제조 공정에 많은 문제점이 있다.The high-density plasma process technology has been applied to many semiconductor device manufacturing processes because the interlayer filling property is improved and partial planarization of the lower pattern is performed when the deposition process is performed to a thickness of a predetermined ratio or more. However, in the process of depositing the interlayer insulating film by the high density plasma method, the upper edge portion of the lower metal wiring is directly exposed to the high density plasma, causing physical etching, causing a lot of damage to the metal wiring and causing device reliability problems. In addition, the etching problem in this area causes severe peeling between the side portion of the metal wiring and the interlayer insulating film, which causes many problems in the device manufacturing process.
도면을 통하여 종래의 기술 및 그 문제점을 설명하고자 한다. 도 1은 종래의 기술에 의한 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도로써, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11) 상부에 금속 배선(12)을 형성하고 층간 절연막(13)을 고밀도 플라즈마 공정으로 증착한 단면도이다. 그러나 고밀도 플라즈마 방법으로 층간 절연막(13)을 증착하는 공정의 초기 단계에서 금속 배선(12)의 상단 모서리 부분(12A)이 고밀도 플라즈마에 직접 노출되게 되어 도면에 도시된 것과 같은 물리적인 식각이 일어난다. 이와 같이 식각된 금속 배선 물질이 다른 부분에 재 증착될 뿐만 아니라, 절연막 내 깊은 준위 포획(deep-level trap for electron and/or hole)의 자리로 작용하여 소자의 전기적인 특성에도 영향을 주게된다.The prior art and its problems will be described with reference to the drawings. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the related art, in which a metal wiring 12 is formed on a substrate 11 on which various elements for forming a semiconductor device are formed, and an interlayer insulating film 13 is formed. ) Is a sectional view of vapor deposition by high density plasma process. However, in the initial stage of the process of depositing the interlayer insulating film 13 by the high density plasma method, the upper edge portion 12A of the metal wiring 12 is directly exposed to the high density plasma, thereby causing physical etching as shown in the drawing. The etched metal wiring material is not only re-deposited in other parts but also serves as a deep-level trap for electron and / or holes in the insulating layer, thereby affecting the electrical characteristics of the device.
따라서 본 발명에서는 이러한 문제점을 해결하기 위해 금속 배선 상부에 버퍼 역할을 하는 절연막을 형성하여 고밀도 플라즈마로부터 금속 배선을 보호하고자 한다.Therefore, in order to solve this problem, the present invention intends to protect the metal wires from the high density plasma by forming an insulating film acting as a buffer on the metal wires.
본 발명은 금속 배선 간의 층간 절연막 및 최종 보호막 형성시 하부의 금속 배선이 고밀도 플라즈마에 직접 노출되지 않도록 하여 금속 배선의 손상을 방지하는데 그 목적이 있다.An object of the present invention is to prevent damage to metal wires by preventing the lower metal wires from being directly exposed to high density plasma when forming an interlayer insulating film and a final protective film between metal wires.
상술한 목적을 달성하기 위한 반도체 소자의 제조 방법은, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판 상부에 금속 배선을 형성한 후, 금속 배선을 포함하는 전체 구조 상부에 상부면보다는 모서리 부분이 더 두껍고, 측면의 하단부 보다는 절연막 측면의 상단부가 더 두껍게 형성되도록 플라즈마 증착법을 이용하여 절연막을 증착하는 단계와, 상기 절연막을 포함하는 전체 구조 상부에 고밀도 플라즈마 증착법을 이용하여 층간 절연막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the method of manufacturing a semiconductor device for achieving the above object, after forming the metal wiring on the substrate on which the various elements for forming the semiconductor device is formed, the corner portion is more than the upper surface on the entire structure including the metal wiring Depositing an insulating film using a plasma deposition method so as to be thicker and forming an upper end portion of the insulating film thicker than a lower end of the side surface, and forming an interlayer insulating film using a high density plasma deposition method on the entire structure including the insulating film. Characterized in that made.
도 1은 종래의 기술에 의한 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도.BRIEF DESCRIPTION OF THE DRAWINGS Sectional drawing shown for demonstrating the manufacturing method of the semiconductor element by a prior art.
도 2(a) 및 도 2(b)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도.2 (a) and 2 (b) are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
11 및 21 : 반도체 기판 12 및 22 : 금속 배선11 and 21: semiconductor substrate 12 and 22: metal wiring
13 및 24 : 층간 절연막 23 : 절연막13 and 24: interlayer insulation film 23: insulation film
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 및 도 2(b)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 단면도이다.2 (a) and 2 (b) are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2(a)에 도시된 것과 같이, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(21) 상부에 금속 배선(22)을 형성한 후, 금속 배선(22)을 포함하는 전체 구조 상부에 얇은 절연막(23)을 증착한다. 이후 공정으로 고밀도 플라즈마를 이용한 층간 절연막 및 최종 보호막 형성 공정을 진행하면 고밀도 플라즈마 내의 이온 및 원자의 충돌에 의한 물리적인 식각이 절연막(23) 만을 대상으로 일어나게 된다. 이 때 고밀도 플라즈마 증착시 발생되는 초기 물리적인 식각에 의한 절연막(23)의 손실은 증착되는 조건에 의하여 변화된다. 그런데, 식각 속도 대 증착 속도(etch rate/deposition rate)가 0.4 보다 큰 일부 과도한 경우에서는 1,000 Å까지도 절연막(23) 손실이 있을 수 있지만, 일반적으로는 크게 500 Å을 넘지 않는 특성을 보인다.As shown in FIG. 2 (a), after the metal wirings 22 are formed on the substrate 21 on which various elements for forming a semiconductor device are formed, a thin film is formed on the entire structure including the metal wirings 22. The insulating film 23 is deposited. Subsequently, when the interlayer insulating film and the final passivation layer forming process using the high density plasma are performed, physical etching due to the collision of ions and atoms in the high density plasma occurs only for the insulating film 23. At this time, the loss of the insulating film 23 due to the initial physical etching generated during the high-density plasma deposition is changed by the deposition conditions. However, in some excessive cases where the etch rate / deposition rate is greater than 0.4, the insulating film 23 may be lost even up to 1,000 mW, but generally does not exceed 500 mW.
한편, 절연막(23)의 형성 방법으로는, 열처리에 따른 금속 배선(22)의 산화 공정을 실시하여 금속 배선 표면을 산화시키고 이를 희생 절연막으로 사용할 수도 있다. 그러나 이러한 방법은 충분한 절연막(23)의 두께를 확보하기 어려우므로, 고밀도 플라즈마를 이용하는 공정이 많이 적용되는 다층 금속 배선 공정에서는 플라즈마를 이용한 절연막(23)을 증착하여 그 희생 절연막의 역할을 충분히 수행할 수 있도록 한다. 본 발명에서는 실리콘 산화막(SiOxHy) 또는 실리콘 질화산화막(SiOxNyHz)을 절연막(23)으로 사용하였다.On the other hand, as a method of forming the insulating film 23, an oxidation process of the metal wiring 22 by heat treatment may be performed to oxidize the metal wiring surface and use it as a sacrificial insulating film. However, since this method is difficult to secure a sufficient thickness of the insulating film 23, in the multilayer metal wiring process in which a process using a high density plasma is applied, the insulating film 23 using plasma can be deposited to sufficiently perform the role of the sacrificial insulating film. To help. In the present invention, a silicon oxide film (SiO x H y ) or a silicon nitride oxide film (SiO x N y H z ) is used as the insulating film 23.
또한 물리적인 이온 및 원자의 충돌에 의한 식각은 금속 배선(22)의 위치에 따라 식각 특성이 달라지는데, 일반적인 플라즈마 절연막(23)은 금속 배선(22)에서의 표면 피복성(step coverage)이 열악하여 금속 배선 측면부의 상단부(23C)와 하단부(23D)에서의 증착된 두께가 다르게 된다. 그러나 이러한 단점이 고밀도 플라즈마를 이용한 층간 절연막 증착시 초기 단계에서 고밀도 플라즈마에 의한 물리적인 식각 손실로 인하여 개선된다. 즉, 절연막(23)의 상단 모서리 부분(23A)이 상단부(23B)보다 두껍게 형성되고 절연막(23) 측면의 상단부(23C)가 하단부(23D)보다 두껍게 형성되지만, 고밀도 플라즈마에 의한 층간 절연막 증착이 진행 되면서 절연막(23)의 상단부 모서리(23A) 및 측면의 상단부(23C) 부분이 식각되어, 절연막(23)의 적용 유무에 의존하지 않고 금속 배선(22)에 의한 그 기하학적인 패턴의 특성에만 의존하는 층간 메움 특성 및 국부적인 평탄화를 확보할 수 있다. 이의 단면도를 도 2(b)에 도시하였다.In addition, the etching characteristics due to the collision of physical ions and atoms are different depending on the position of the metal wiring 22. In general, the plasma insulating film 23 has poor surface coverage in the metal wiring 22. The thicknesses deposited at the upper end portion 23C and the lower end portion 23D of the metal wiring side portion are different. However, this drawback is improved due to the physical etching loss caused by the high density plasma in the initial stage in the deposition of the interlayer insulating film using the high density plasma. That is, although the upper edge portion 23A of the insulating film 23 is formed thicker than the upper end 23B, and the upper end 23C of the side surface of the insulating film 23 is formed thicker than the lower end 23D, interlayer insulating film deposition by high density plasma As it proceeds, the upper edge 23A of the insulating film 23 and the upper 23C portion of the side surface are etched, not depending on whether the insulating film 23 is applied, but only on the characteristics of the geometric pattern by the metal wiring 22. The interlayer filling characteristic and local planarization can be ensured. A cross-sectional view thereof is shown in FIG. 2 (b).
도 2(b)에 도시된 것과 같이, 고밀도 플라즈마를 이용하여 층간 절연막(24)을 형성한 경우 층간 절연막(24)에는 응축 응력(compressive stress)이 존재하는데 반하여, 금속 배선(22)의 경우에는 인장 응력(tensile stress)이 존재하게 된다. 이러한 응력의 차이에 의하여 금속 배선(22)과 층간 절연막(24)의 계면부에서는 박리 현상이 발생하게 되는데, 비교적 적은 압축 응력을 가지고 있는 절연막(23)을 형성함으로써 위와 같은 현상을 방지하여 소자의 신뢰성을 확보할 수 있다.As shown in FIG. 2B, when the interlayer insulating film 24 is formed using a high density plasma, a compressive stress exists in the interlayer insulating film 24, whereas in the case of the metal wiring 22. Tensile stress is present. Due to such a difference in stress, a peeling phenomenon occurs at the interface between the metal wiring 22 and the interlayer insulating film 24. By forming the insulating film 23 having a relatively low compressive stress, the above phenomenon is prevented. Reliability can be secured.
상술한 바와 같이 본 발명에 의하면, 금속 배선 및 고밀도 플라즈마를 이용한 층간 절연막 간의 박리현상을 획기적으로 개선시킬 수 있고, 층간 절연막 증착의 초기 단계에서 발생하였던 금속 배선 상단부 모서리 부분의 식각에 의한 소자의 신뢰성 열화를 개선할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the peeling phenomenon between the metal wiring and the interlayer insulating film using the high density plasma can be remarkably improved, and the reliability of the device due to the etching of the upper edge portion of the metal wiring that occurred in the initial stage of the interlayer insulating film deposition. There is an excellent effect to improve the deterioration.
Claims (6)
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| KR100547242B1 (en) * | 1999-12-22 | 2006-02-01 | 주식회사 하이닉스반도체 | A method of forming intermetal dielectric layer for preventing void |
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| JPS63161624A (en) * | 1986-12-25 | 1988-07-05 | Ulvac Corp | Plasma vapor growth method |
| JPH01207931A (en) * | 1988-02-16 | 1989-08-21 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH03247767A (en) * | 1990-02-26 | 1991-11-05 | Fuji Electric Co Ltd | Formation of insulating film |
| JPH04132220A (en) * | 1990-09-21 | 1992-05-06 | Tokyo Ohka Kogyo Co Ltd | Plasma taper etching method |
| JPH098138A (en) * | 1995-06-20 | 1997-01-10 | Nippon Steel Corp | Semiconductor device and its manufacture |
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| KR970077331A (en) * | 1996-05-28 | 1997-12-12 | 김광호 | Interlayer insulating film formation method of semiconductor device |
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