KR19990058292A - MOS transistor and its manufacturing method - Google Patents
MOS transistor and its manufacturing method Download PDFInfo
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- KR19990058292A KR19990058292A KR1019970078391A KR19970078391A KR19990058292A KR 19990058292 A KR19990058292 A KR 19990058292A KR 1019970078391 A KR1019970078391 A KR 1019970078391A KR 19970078391 A KR19970078391 A KR 19970078391A KR 19990058292 A KR19990058292 A KR 19990058292A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 16
- 238000009413 insulation Methods 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
채널 영역에 측벽 산화막을 가진 트랜치를 형성한 모스 트랜지스터 및 그 제조 방법에 관한 것으로, 채널 영역에 트랜치를 형성한 후 양 측벽에 최상단이 접합층 깊이 정도에 이르는 스페이스 산화막을 형성하여 소스/드레인 영역과 채널 영역을 격리함으로써 단 채널 효과를 억제하여 소자의 안정성 및 신뢰성을 향상시킨다.The present invention relates to a MOS transistor in which a trench having sidewall oxide films is formed in a channel region, and a method of manufacturing the same. A trench oxide is formed in the channel region, and a space oxide film having a depth of about the junction layer is formed on both sidewalls. Isolation of the channel region suppresses short channel effects, improving device stability and reliability.
Description
본 발명은 모스 트랜지스터 및 그 제조 방법에 관한 것으로, 더욱 상세하게는 채널 영역에 측벽 산화막을 가진 트랜치를 형성한 모스 트랜지스터 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method of manufacturing the same, and more particularly, to a MOS transistor in which a trench having a sidewall oxide film is formed in a channel region, and a method of manufacturing the same.
일반적으로 모스(MOS) 트랜지스터는 필드 효과 트랜지스터의 일종으로, 반도체 기판에 형성된 소스, 드레인 영역과, 이 소스, 드레인 영역이 형성된 기판 상에 게이트 산화막과 게이트가 형성된 구조를 가진다.In general, a MOS transistor is a type of field effect transistor, and has a source and a drain region formed in a semiconductor substrate, and a structure in which a gate oxide film and a gate are formed on a substrate on which the source and drain regions are formed.
또한, 소스 및 드레인 영역의 안쪽에 농도가 엷은 LDD 영역을 둔 구조의 모스 트랜지스터가 주로 사용되고 있다.In addition, a MOS transistor having a structure having a thin LDD region inside the source and drain regions is mainly used.
상기와 같은 모스 트랜지스터는 채널의 종류에 따라 N 채널 모스 트랜지스터와 P 채널 모스 트랜지스터로 나눌 수 있으며, 상기 각 채널의 모스 트랜지스터가 하나의 기판에 형성되는 경우 이를 CMOS(complementary metal oxide semiconductor) 트랜지스터라 한다.The MOS transistor may be divided into an N-channel MOS transistor and a P-channel MOS transistor according to the type of channel. When the MOS transistor of each channel is formed on one substrate, it is called a complementary metal oxide semiconductor (CMOS) transistor. .
그러면, 첨부된 도 3을 참조로 하여 종래의 일반적인 모스 트랜지스터의 구조에 대하여 설명하면 다음과 같다.Referring to the attached FIG. 3, the structure of a conventional general MOS transistor will be described.
도 3에서 알 수 있는 바와 같이 모스 트랜지스터는 P형 또는 N형 단결정 반도체 기판(1)에 P형 불순물 또는 N형 불순물이 매입된 웰(3)이 형성되어 있으며, 반도체 기판(1)의 웰(3) 경계부 표면에는 트랜치(2)가 선택적으로 마련되어 소자 분리가 이루어진다.As can be seen in FIG. 3, in the MOS transistor, a well 3 in which P-type impurities or N-type impurities are embedded is formed in a P-type or N-type single crystal semiconductor substrate 1, and a well ( 3) A trench 2 is selectively provided on the boundary surface to separate the elements.
그리고, 웰(3) 상의 소자 영역인 채널 영역에는 게이트 산화막(4)과 게이트 전극(5)이 형성되어 있으며, 각 게이트 전극(5)의 측벽에는 스페이스 절연막(7)이 형성되어 있다. 또한, 게이트 전극(4)의 양 끝단과 트랜치(2) 사이의 반도체 기판(1)에는 웰(3)과 반대 도전형을 갖는 N형 불순물 또는 P형 불순물이 매입된 소스/드레인 영역(6)이 각각 형성되어 있다.A gate oxide film 4 and a gate electrode 5 are formed in the channel region, which is an element region on the well 3, and a space insulating film 7 is formed on the sidewall of each gate electrode 5. In addition, the semiconductor substrate 1 between the both ends of the gate electrode 4 and the trench 2 has a source / drain region 6 in which an N-type impurity or a P-type impurity having a conductivity type opposite to that of the well 3 is embedded. These are formed, respectively.
상기와 같이 구성된 종래의 일반적인 모스 트랜지스터의 제조 방법을 도 3을 참조하여 간략히 설명하면 다음과 같다.A method of manufacturing a conventional general MOS transistor configured as described above will be briefly described with reference to FIG. 3 as follows.
반도체 기판(1) 상에 패드 산화막과 질화막을 연달아 적층한 후 감광막을 도포하고, 마스크를 이용하여 감광막을 노광 현상한 다음 드러난 질화막 및 패드 산화막을 식각하여 제거하고, 다시 드러난 반도체 기판을 일정 깊이로 식각하여 반도체 기판(1)의 소자 분리 영역인 트랜치(T)를 형성한다. 이어, 감광막을 제거하고 트랜치(T)를 포함한 반도체 기판(1) 상부면에 절연막(2)을 두껍게 증착하여 트랜치(T)를 메운다.After stacking the pad oxide film and the nitride film successively on the semiconductor substrate 1, applying a photoresist film, exposing and developing the photoresist film using a mask, etching and removing the exposed nitride film and the pad oxide film, and removing the exposed semiconductor substrate to a predetermined depth. Etching forms a trench T, which is an isolation region of the semiconductor substrate 1. Subsequently, the photoresist film is removed and a thick insulating film 2 is deposited on the upper surface of the semiconductor substrate 1 including the trench T to fill the trench T.
이후, 절연막(2)이 형성된 반도체 기판(1) 상에 감광막을 도포한 후, 감광막을 노광 현상하여 트랜치(T) 상부의 절연막(2) 위에 감광막 패턴을 남긴 다음, 이를 마스크로 절연막(2)을 식각하여 트랜치 절연막 패턴을 형성한다. 그리고, 감광막을 제거한 다음 트랜치 절연막 패턴을 CMP(chemical mechanical polishing)를 이용하여 평탄화한 다음 질화막과 패드 산화막을 제거한다.Thereafter, after the photoresist film is applied onto the semiconductor substrate 1 on which the insulation film 2 is formed, the photoresist film is exposed and developed to leave a photoresist pattern on the insulation film 2 above the trench T, and then the insulation film 2 is used as a mask. Is etched to form a trench insulating film pattern. After removing the photoresist layer, the trench insulation layer pattern is planarized using chemical mechanical polishing (CMP), and then the nitride layer and the pad oxide layer are removed.
이후, 반도체 기판(1)을 세척하고, 소자 영역에 P형 또는 N형의 불순물 이온을 주입하고 확산하여 불순물 농도의 균일성이 높은 P 또는 N 웰(3)을 형성한다.Thereafter, the semiconductor substrate 1 is washed, and P-type or N-type impurity ions are implanted and diffused into the device region to form a P or N well 3 having high uniformity of impurity concentration.
그리고, 반도체 기판(1) 또는 웰(3) 상에 게이트 산화막(4)을 형성하고, 그 위에 다결정 실리콘으로 게이트 전극(5)을 형성한다.Then, the gate oxide film 4 is formed on the semiconductor substrate 1 or the well 3, and the gate electrode 5 is formed of polycrystalline silicon thereon.
이후, 게이트 전극(5)을 마스크로 하여 웰(3)과 반대 도전형을 갖는 불순물을 웰(3)에 이온 주입하여 소스/드레인 영역(6)을 각각 형성한 다음, 반도체 기판(1) 전면에 걸쳐 저압 화학 기상 증착법(LPCVD : low pressure chemical vapor deposition)으로 절연막을 증착시킨 후 이방성 식각하여 게이트 전극(5)의 측벽에 스페이스 절연막(7)을 형성한다.Subsequently, the source / drain regions 6 are formed by ion implanting impurities into the well 3 with the gate electrode 5 as a mask, and impurities having opposite conductivity types to the well 3, and then the entire surface of the semiconductor substrate 1. An insulating film is deposited by low pressure chemical vapor deposition (LPCVD) over and then anisotropically etched to form a space insulating film 7 on the sidewall of the gate electrode 5.
그리고, 층간 절연막을 증착한 뒤, 식각하여 콘택트 홀을 형성하고, 스퍼터링법 등에 의해 도전막을 증착하고 패터닝하여 전극을 형성함으로써 모스 트랜지스터를 완성한다.After the deposition of the interlayer insulating film, the contact hole is etched to form a contact hole, the conductive film is deposited and patterned by sputtering or the like to form an MOS transistor.
이와 같은 방법으로 모스 트랜지스터를 형성할 경우 반도체 소자의 미세화에 따라 채널 길이 1
또한, 단채널 효과에 의해 드레인 전압의 상승과 더불어 드레인 부근의 공핍층이 소스 영역까지 미쳐, 그 결과 전압에 의해 제어되지 않는 전류인 공간전하 제한 전류가 대량으로 유출하여 전계 효과 트랜지스터의 기능을 잃어버리는 펀치 스루(punch through) 현상이 발생하여 반도체 소자의 전기적 특성을 저하시킨다.In addition, due to the short-channel effect, the drain voltage increases and the depletion layer near the drain reaches the source region. As a result, a large amount of space charge limiting current, which is not controlled by the voltage, flows out in large quantities, and the function of the field effect transistor is lost. A throw-through punch through phenomenon occurs to deteriorate the electrical characteristics of the semiconductor device.
본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 트랜지스터 소자의 미세화에 따른 단 채널 효과를 억제하는 데 있다.The present invention has been made to solve such a problem, and its object is to suppress short channel effects due to miniaturization of transistor elements.
도 1은 본 발명의 일 실시예에 따른 모스 트랜지스터를 도시한 단면도이고,1 is a cross-sectional view illustrating a MOS transistor according to an embodiment of the present invention.
도 2a ∼도 2e는 본 발명의 일 실시예에 따른 모스 트랜지스터의 제조 공정 순서도이고,2A to 2E are flowcharts of a manufacturing process of a MOS transistor according to an embodiment of the present invention.
도 3은 종래의 모스 트랜지스터를 도시한 단면도이다.3 is a cross-sectional view illustrating a conventional MOS transistor.
상기와 같은 목적을 달성하기 위하여, 본 발명은 절연막이 매입된 제 1트랜치에 의해 소자 영역이 정의된 반도체 기판의 채널 영역에 제 2트랜치를 형성한 다음 제 2트랜치 양 측벽에 스페이스 산화막을 형성하여 소스/드레인 영역과 채널 영역을 격리시키는 것을 특징으로 한다.In order to achieve the above object, the present invention forms a second trench in the channel region of the semiconductor substrate in which the device region is defined by the first trench in which the insulating film is embedded, and then forming a space oxide film on both sidewalls of the second trench. It is characterized by isolating the source / drain region and the channel region.
이하, 첨부된 도면을 참조로 하여 본 발명에 따른 바람직한 일 실시예를 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 1은 본 발명의 일 실시예에 따른 모스 트랜지스터를 단면도를 도시한 것으로, 그 단면 구조를 설명하면 다음과 같다.1 is a cross-sectional view of a MOS transistor according to an embodiment of the present invention, the cross-sectional structure will be described as follows.
P형 또는 N형 단결정 반도체 기판(10)에 P형 불순물 또는 N형 불순물이 매입된 웰(12)이 형성되어 있으며, 반도체 기판(10)의 웰(12) 경계부 표면에는 절연막(11)이 매입된 제 1트랜치(T1)가 선택적으로 마련되어 소자가 분리된다.A well 12 in which P-type impurities or N-type impurities are embedded is formed in the P-type or N-type single crystal semiconductor substrate 10, and the insulating film 11 is embedded in the boundary surface of the well 12 of the semiconductor substrate 10. First trenches T1 are selectively provided to separate the devices.
그리고, 웰(12) 상의 소자 영역에는 게이트 산화막(17)과 게이트 전극(18)이 형성되어 있으며, 게이트 전극(18)의 측벽에는 스페이스 절연막(20)이 형성되어 있다.The gate oxide film 17 and the gate electrode 18 are formed in the element region on the well 12, and the space insulating film 20 is formed on the sidewall of the gate electrode 18.
게이트 산화막(17)의 양 끝단과 제 1트랜치(T1) 끝단 사이의 반도체 기판(10)에는 웰(12)과 반대 도전형을 갖는 불순물이 매입된 소스/드레인 영역(19)이 각각 형성되어 있다.In the semiconductor substrate 10 between the both ends of the gate oxide layer 17 and the end of the first trench T1, source / drain regions 19 in which impurities having opposite conductivity types to the well 12 are embedded are formed, respectively. .
또한, 게이트 산화막(17)의 하측 웰(12)의 채널 영역에는 양측에는 스페이스 산화막(14)이 형성되며, 스페이스 산화막(14) 사이의 하부에는 실리콘 질화막(15)이 형성되며, 그 내부는 폴리 실리콘(16)이 매입된 제 2트랜치(T2)가 형성되어 있다.In addition, a space oxide film 14 is formed on both sides of the channel region of the lower well 12 of the gate oxide film 17, and a silicon nitride film 15 is formed below the space between the space oxide films 14. The second trench T2 in which the silicon 16 is embedded is formed.
상기와 같이 구성된 모스 트랜지스터의 제조 과정을 첨부된 도 2a ∼2e를 참조하여 상세히 설명하면 다음과 같다.The manufacturing process of the MOS transistor configured as described above will be described in detail with reference to FIGS. 2A to 2E.
먼저, 반도체 기판(10) 상에 패드 산화막과 질화막을 연달아 적층한 후 감광막을 도포하고, 마스크를 이용하여 감광막을 노광 현상한 다음 드러난 질화막 및 패드 산화막을 식각하여 제거하고, 다시 드러난 반도체 기판을 일정 깊이로 식각하여 반도체 기판(10)의 소자 분리 영역인 제 1트랜치(T1)를 형성한다. 이어, 감광막을 제거하고 제 1트랜치(T1)를 포함한 반도체 기판(10) 상부면에 절연막(11)을 두껍게 증착하여 제 1트랜치(T1)를 메운다.First, the pad oxide film and the nitride film are successively stacked on the semiconductor substrate 10, and then a photosensitive film is coated, the photosensitive film is exposed and developed using a mask, the exposed nitride film and the pad oxide film are etched and removed, and the exposed semiconductor substrate is fixed. Etching to a depth to form a first trench (T1) that is an isolation region of the semiconductor substrate 10. Subsequently, the photoresist layer is removed and a thick insulating film 11 is deposited on the upper surface of the semiconductor substrate 10 including the first trench T1 to fill the first trench T1.
이후, 절연막(11)이 형성된 반도체 기판(10) 상에 감광막을 도포한 후, 감광막을 노광 현상하여 제 1트랜치(T1) 상부의 절연막(11) 위에 감광막 패턴을 남긴 다음, 이를 마스크로 나머지 절연막(11)을 식각하여 트랜치 절연막 패턴을 형성한다. 그리고, 감광막을 제거한 다음 트랜치 절연막 패턴을 CMP(chemical mechanical polishing)를 이용하여 평탄화한 다음 질화막과 패드 산화막을 제거한다.Subsequently, after the photoresist film is coated on the semiconductor substrate 10 on which the insulation film 11 is formed, the photoresist film is exposed and developed to leave a photoresist pattern on the insulation film 11 on the upper portion of the first trench T1. (11) is etched to form a trench insulating film pattern. After removing the photoresist layer, the trench insulation layer pattern is planarized using chemical mechanical polishing (CMP), and then the nitride layer and the pad oxide layer are removed.
그리고, 도 2a에서와 같이 정의된 소자 영역에 P형 불순물(이온) 또는 N형 불순물(이온)을 주입하고 열처리함으로써 P 또는 N형의 웰(12)을 형성하고, 반도체 기판(10) 상에 감광막(13)을 도포한 뒤 일반적인 사진 식각 공정에 의해 채널이 형성될 영역을 정의하기 위해 감광막(13) 패턴을 형성한다. 그리고, 감광막(13) 패턴을 레지스터로 반도체 기판(10)을 식각하여 채널 영역에 제 2트랜치(T2)를 형성한다.Then, a P-type or N-type well 12 is formed by injecting a P-type impurity (ion) or an N-type impurity (ion) into the device region defined in FIG. 2A and performing heat treatment, and then, on the semiconductor substrate 10 After the photoresist layer 13 is applied, a photoresist layer 13 pattern is formed to define a region where a channel is to be formed by a general photolithography process. The second substrate T2 is formed in the channel region by etching the semiconductor substrate 10 using the photoresist pattern 13 as a resistor.
그리고, 도 2b에서와 같이 남은 감광막(13)을 제거하고, 반도체 기판(10) 상에 저압 화학 기상 증착법(LPCVD : low pressure chemical vapor deposition) 또는 상압 화학 기상 증착법(APCVD : atmospheric pressure chemical vapor deposition)으로 산화막(14)을 증착한 다음, 산화막(14)을 식각하여 스페이스 산화막(14)을 형성한다.Then, as shown in FIG. 2B, the remaining photoresist film 13 is removed, and the low pressure chemical vapor deposition (LPCVD) or atmospheric pressure chemical vapor deposition (APCVD) is performed on the semiconductor substrate 10. After the oxide film 14 is deposited, the oxide film 14 is etched to form a space oxide film 14.
이때, 제 2트랜치(T2) 내부에 형성되는 스페이스 산화막(14)은 최상단이 도 2c에서와 같이 깊이가 L이 되도록 식각하여 형성한다.In this case, the space oxide layer 14 formed in the second trench T2 is formed by etching the top end thereof to have a depth L as shown in FIG. 2C.
이후, 도 2d에서와 같이 제 2트랜치(T2)를 실리콘으로 다시 채우기 위해 화학 기상 증착법(CVD)으로 폴리 실리콘(16)을 증착한다. 이때, 폴리 실리콘(16)을 증착하기 전에 후속 공정인 CMP 공정시 반도체 기판(10)의 손상을 방지하기 위하여 실리콘 질화막(15)을 증착한다.Thereafter, as illustrated in FIG. 2D, polysilicon 16 is deposited by chemical vapor deposition (CVD) to refill the second trench T2 with silicon. At this time, the silicon nitride film 15 is deposited in order to prevent damage to the semiconductor substrate 10 during the subsequent CMP process before depositing the polysilicon 16.
그리고, 폴리 실리콘(16)이 형성된 반도체 기판(10) 상에 감광막을 도포한 후, 감광막을 노광 현상하여 제 2트랜치(T2) 상부의 폴리 실리콘(16) 위에 감광막 패턴을 남긴 다음, 이를 마스크로 나머지 폴리 실리콘(16)을 식각하여 제 2트랜치(T2) 절연막 패턴을 형성한다. 그리고, 감광막을 제거한 다음 도 2e에서와 같이 제 2트랜치(T2) 절연막 패턴을 CMP를 이용하여 제 2트랜치(T2) 영역에만 폴리 실리콘(16)이 남도록 평탄화한 다음 실리콘 질화막(15)을 제거한다.Then, after the photoresist is coated on the semiconductor substrate 10 on which the polysilicon 16 is formed, the photoresist is exposed and developed to leave a photoresist pattern on the polysilicon 16 above the second trench T2. The remaining polysilicon 16 is etched to form a second trench T2 insulating layer pattern. After removing the photoresist film, the second trench T2 insulating film pattern is planarized such that polysilicon 16 remains only in the second trench T2 region by using CMP, and then the silicon nitride film 15 is removed as shown in FIG. 2E. .
이후, 반도체 기판(10)을 세척하고, 도 1에서와 같이 반도체 기판(10) 또는 웰(12) 상에 열산화를 통하여 게이트 산화막(16)을 형성하고, 그 위에 다결정 실리콘을 증착하여 패터닝함으로써 게이트 전극(17)을 형성한다.Thereafter, the semiconductor substrate 10 is washed, the gate oxide film 16 is formed on the semiconductor substrate 10 or the well 12 through thermal oxidation, as shown in FIG. 1, and polycrystalline silicon is deposited and patterned thereon. The gate electrode 17 is formed.
이후, 게이트 전극(17)을 마스크로 하여 웰(12)과 반대 도전형을 갖는 불순물을 웰(12)에 이온 주입하여 소스/드레인 영역(18)을 각각 형성한 다음, 반도체 기판(10) 전면에 걸쳐 저압 화학 기상 증착법(LPCVD : low pressure chemical vapor deposition)으로 산화막을 증착시킨 후 이방성 식각하여 게이트 전극(17)의 측벽에 스페이스 절연막(19)을 형성한다.Subsequently, the source / drain regions 18 are formed by ion implanting impurities into the wells 12 with the gate electrode 17 as a mask and having impurities opposite to the wells 12, and then the entire surface of the semiconductor substrate 10. An oxide film is deposited by low pressure chemical vapor deposition (LPCVD) over and then anisotropically etched to form a space insulating film 19 on the sidewall of the gate electrode 17.
그리고, 층간 절연막을 증착한 후, 식각하여 콘택트 홀을 형성하고, 스퍼터링법 등에 의해 도전막을 증착하고 패터닝하여 전극을 형성함으로써 모스 트랜지스터를 완성한다.After the deposition of the interlayer insulating film, the contact hole is etched to form a contact hole, and the conductive film is deposited and patterned by sputtering or the like to form an MOS transistor.
이와 같이 본 발명은 채널 영역에 트랜치를 형성한 후 양 측벽에 최상단이 접합층 깊이 정도에 이르는 스페이스 산화막을 형성하여 소스/드레인 영역과 채널 영역을 격리함으로써 단 채널 효과가 억제되어 소자의 안정성 및 신뢰성을 향상시킬 수 있다.As described above, in the present invention, after forming a trench in the channel region, a space oxide film having a top end at a depth of about the junction layer is formed on both sidewalls to isolate the source / drain region and the channel region so that the short channel effect is suppressed, thereby ensuring stability and reliability of the device. Can improve.
Claims (6)
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| KR1019970078391A KR100292152B1 (en) | 1997-12-30 | 1997-12-30 | Mos transistor and fabricating method thereof |
| US09/223,236 US6200841B1 (en) | 1997-12-30 | 1998-12-30 | MOS transistor that inhibits punchthrough and method for fabricating the same |
| US09/595,851 US6489651B1 (en) | 1997-12-30 | 2000-06-16 | MOS transistor that inhibits punchthrough |
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| US7541571B2 (en) | 2005-02-11 | 2009-06-02 | Samsung Electronics., Co., Ltd. | Image sensor having first and second charge transmitters |
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