KR19990058047A - Transmission speed discrimination device - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

Transmission equipment of communication device.

I. The technical problem to be solved by the invention

Transmission speed detection device in transmission equipment.

All. Summary of Solution of the Invention

The speed determination device of the transmission equipment resets the counter by a clock generator for generating and supplying a clock to the edge detector and the counter, an edge detector for detecting the edge of the transmission signal, and a detection win pulse applied from the edge detector. A counter for countering a supplied clock, a decoder for decoding a counter value of the counter, and a speed detector for detecting a speed according to the output of the decoder and outputting a speed determination signal to a controller of the transmission equipment. Speed discrimination device.

la. Important uses of the invention

All transmission equipment.

Description

Transmission speed discrimination device

The present invention relates to a transmission speed determining apparatus of a wired / wireless transmission apparatus, and more particularly, to an apparatus for automatically determining a transmission speed.

In general, a wired or wireless transmission device is a device that connects a terminal and an exchange system to perform voice calls and data transmission and reception. The wired or wireless transmission device transmits and receives voice signals and various data at various speeds. When the transmission speed changed in the transmission device, the operator had to check it and adjust the speed of the transmission device to match the transmission speed by operating a switch. Therefore, the unmanned operation becomes difficult in the case of the transmission equipment, and it was difficult to change the transmission speed determined at the time of installation of the transmission equipment.

Accordingly, an object of the present invention is to provide an apparatus for determining a transmission speed in a wired or wireless transmission device.

Another object of the present invention is to provide a device for automatically adjusting a transmission speed by determining a transmission speed in a wired or wireless transmission device.

After achieving the above objects, the present invention provides a speed generator for determining the speed of a transmission equipment, a clock generator for generating and supplying a clock to an edge detector and a counter, the edge detector for detecting an edge of a transmission signal, and the edge detector. A counter unit for resetting the counter by the detection Winpulse applied from the counter and counting the supplied clock, a decoding unit for decoding the counter value of the counter unit, and detecting a speed in accordance with the output of the decoding unit to control the transmission device. And a speed detector for outputting a speed determination signal.

1 is a block diagram of an apparatus for determining a transmission speed of a transmission apparatus according to the present invention.

2 is a detailed circuit diagram according to a preferred embodiment of the present invention.

3 is a timing diagram of the edge detector;

4 is a timing diagram of the counter unit;

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an apparatus for determining a transmission speed of a transmission apparatus according to the present invention.

The transmission signal input to the transmission equipment will be described on the assumption that a positive pulse is input as a bipolar digital signal. The clock generator 50 generates a reference clock used in the transmission equipment and outputs the reference clock to the edge detector 10 and the counter 20. The edge detector 10 detects an edge of the digital transmission signal input according to the clock signal received from the clock generator 50, generates a detection one pulse, and outputs the detected one pulse to the counter 20. When the detection one pulse is received from the edge detector 10, the counter 20 counters the number of clocks received from the clock generator 50 to the decoder 30 until the next detection one pulse is received. The decoder 30 decodes the received signal in response to the counter value received from the counter 20 and outputs it to the speed detector 40. The speed detector 40 determines a speed according to the received decoded signal, and outputs the determined speed to the controller 60. The control unit 60 performs overall control of the transmission device, and operates the transmission device in response to the speed detection signal received from the speed detection unit 40.

2 is a detailed circuit diagram according to a preferred embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to FIG. 2.

First, the configuration and operation of the edge detector 10 will be described. The input transmission signal is input to a first flip-flop (hereinafter referred to as F / F1) which is a deflip-flop, and the clock signal is a second flip-flop (hereinafter referred to as F / F2) to the clock stage of the F / F1. Is input to the clock stage. In addition, the output terminal Q of the F / F1 is connected to the input terminal D of the F / F2. It is also input to the end gate 101 to generate a detection one pulse from the output of the F / F1 and the output of the F / F2.

3 is a timing diagram of the edge detector.

In the following description, the transmission signal is any one of 256Kbps, 512Kbps, 1024Kbps, and 2048Kbps, and the frequency of the clock signal will be described assuming 36.864MHz to help the understanding of the present invention.

When the detection signal transitions high at the time T1, the F / F1 recognizes it at time T2 in synchronization with a clock signal and transitions to high. 3, the output delay time of the F / F1 is not shown. Therefore, the F / F2 transitions high at the time T3 by the delay time of the F / F1. In addition, the output of the F / F1 and the end gate 101 outputting the AND of the F / F2 are output high after a predetermined delay time. When the detection signal transitions to the low state at the time T4, the output of the F / F1 transitions to the low state at the time T5, so that the output of the end gate 101 also transitions to the low phase after a predetermined delay time. The output of the F / F2 is output to the low state at the time of the T6. Accordingly, the final output of the edge detector 10 remains high from the time point T3 to the time point T4 in accordance with the output of the end gate 101. Therefore, the rising edge of the transmission signal is detected based on the output value of the end gate to generate a detection one pulse.

Referring to FIG. 2 again, the counter unit is configured to perform a counter by receiving a clock signal from an end gate 102 for providing a clock applied to a first counter CH1 and an output terminal of Q03 of the first counter CH1. And a NAND gate 103 for generating an output signal by inputting signals from the Q10 output terminal and the Q11 output terminal of the second counter. The detection one pulse output from the end gate 101 is input to the counter restart stage of the counter unit 20. Therefore, the first counter CH1 and the second counter CH2 are reset to restart the counter. The counter may be configured as 74HC393. This will be described with reference to FIG. 4.

4 is a timing diagram of the counter unit.

The transmission signal is input and transitions to a high state at time T7. Further, since the first counter CH1 and the second counter CH2 of the counter unit are reset by the detection one pulse, the output of Q10 and the output of Q11 of the second counter are low. Therefore, the NAND gate 103 remains high. In addition, the AND gate 102, which inputs the NAND gate 103 and the detection signal and the clock signal, transitions high at time T8, the transmission signal maintains a high state, and the clock while the NAND gate 103 maintains a high state. Transition to high and low states according to signal. Accordingly, the clock terminal of the first counter CH1 of the counter unit 20 detects a falling edge and starts the counter. Therefore, the first counter starts the counter from the time T9. In addition, since the Q03 output terminal of the first counter is connected to the clock terminal of the second counter, the number counted by the first and second counters is limited to 48. In addition, the output of the end gate 102 transitions to the low state at the time T10 when the transmission signal transitions to the low state. Therefore, the counter is executed only in the section in which the transmission signal is high.

Decoder 30 connects the Q02 output terminal of the first counter CH1 to the Q20 input terminal of the decoder 30 and the output terminal of Q03 to the input terminal of the decoder Q21. The Q10 output terminal of the second counter CH2 is connected to the Q22 input terminal of the decoder 30, and the output terminal of the Q13 is connected to the Q23 input terminal. Therefore, the internal logic of the A output terminal and the B output terminal of the decoder 30 may be shown as Equation 1 below.

If the state detected by the decoder 30 by the equation 1 and the characteristics of the counter is displayed, it can be shown as Table 1 below.

Counter value A output B output 0-11 One One 12 to 23 One 0 24 to 47 0 One 48 0 0

The value determined by Table 1 is input to the speed detector 40 of FIG. Since the clock signal is assumed to be 36.864 MHz, the transmission signal has a speed of 1024 Kbps. For example, the time from the rising edge to the falling edge of the transmission signal Same as Therefore, the calculated value is about 488ns. This corresponds to 18 cycles of the supplied clock. Therefore, when the transmission rate is transmitted at 1024Kbps it satisfies Table 1 above.

In the present invention, the step of detecting the speed in the configuration of the speed detector is configured in three steps to reduce the error while preventing the wrong speed from being detected by the transmitted signal noise.

Referring to FIG. 2, the speed detector 40 is connected from the A output terminal received from the decoder 30 to the de-input terminal of the third flip-flop F / F3, and the output terminal of the F / F 3 is the fourth flip-flop F / F4. The input terminal of the F / F4 is input to the de-input terminal of the fifth flip-flop. In addition, the output of F / F3, the output of F / F4 and the output of F / F5 are input to OR-GATE 105 having three inputs and simultaneously to NAND gate 106. An output of the OR gate 105 is input to an S-end of an RS flip-flop F / F9, and an input of the NAND gate 106 is input to an Al-end of the F / F9. Accordingly, the output of the F / F9 outputs the speed determination signal according to the A output to the controller 60.

The B output terminal of the decoder 30 is connected to the de-input terminal of the sixth flip-flop F / F6, the output terminal of the F / F6 is connected to the de-input terminal of the seventh flip-flop F / F7, and the output terminal of the F / F7 is It is connected to the de-input terminal of the eighth flip-flop F / F8. In addition, the output terminal of the F / F6, the output terminal of the F / F7, and the output terminal of the F / F8 are respectively input to the OR gate 108 having three inputs, and are simultaneously input to the input terminal of the NAND gate 107. In addition, the output of the OR gate 108 is input to the al stage of the second RS flip-flop F / F10, and the output of the NAND gate 107 is input to the S stage. Accordingly, the output of the F / F10 determines the speed of the signal output from the decoder 30 and outputs it to the controller 60.

In addition, the NAND gate 104 for applying clock signals of the six de-flip-flops F / F3, F / F4, F / F5, F / F6, F / F7, and F / F8 has an output of the NAND gate 103 and the transmission. The clock signal is applied to the six de-flip flops by the output of the signal. Table 2 shows the relationship between the input and the output of the NAND gate.

Transmission signal Q11 Q12 103 outputs 104 outputs 0 No change in output No change in output No change in output × One 0 0 One 0 One 0 One One One One One 0 One One One One One 0 One

As shown in Table 2, the transmission signal is inverted, and a clock is applied to the six de- flip-flops every one cycle. In addition, since the output of the NAND gate 104 changes from an output of 0 to an output of 1 every cycle, the detection of the transmission signal is configured to be detected after three cycles.

As described above, since the transmission speed can be detected by the wired / wireless transmission equipment used in the communication system, the user does not need to perform a separate switch operation. In addition, there is an advantage that the transmission equipment can be miniaturized and light weight because there is no need to use mechanical clutch parts. In addition, the speed can be automatically adjusted in the transmission equipment has the advantage that unmanned operation is possible.

Claims (7)

In the speed determination device of the transmission equipment, A clock generator for generating and supplying a clock to the edge detector and the counter; The edge detector for detecting an edge of a transmission signal; A counter unit for resetting a counter and counting a clock supplied by a detection win pulse applied from the edge detector; A decoding unit for decoding a counter value of the counter unit; And a speed detector for detecting a speed according to the output of the decoder and outputting a speed determination signal to a controller of the transmission equipment. The method of claim 1, wherein the edge detector, And a first flip flop for detecting an edge of a transmission signal input to the de-input terminal by a clock received from the clock generator. The method of claim 2, A second flip flop for detecting an edge by receiving a clock signal from the output signal of the first flop and the clock generator; And a first end gate for outputting and outputting the signals of the first flip flop and the second flip flop. The method of claim 1, wherein the counter unit, An AND gate that inputs and outputs a clock signal supplied from the clock generator, the transmission signal, and a NAND signal as an input of an output of the lower two bits Q10 and Q11 of the second counter; A first counter which resets a counter in response to an output of the edge detector, and counters a clock signal of the AND gate; The second counter which uses the output of the most significant bit Q03 of the first counter as a clock signal and resets the counter value by an output signal of the edge detector; And a first NAND gate for NAND output of the lower two bits (Q10, Q11) of the second counter. The method of claim 4, wherein the decoder, The outputs of the upper two bits Q02 and Q03 of the first counter are respectively input to the lower two bits Q20 and Q21 of the decoder, and the signals of the lower two bits Q01 and Q11 of the second counter are respectively input. And two (A, B) output signals as inputs of the upper two bits (Q22, Q23) of the decoder as shown in Equation 2 below. The method of claim 5, wherein the speed detection unit, An output of the first NAND gate, a second NAND gate to NAND the transmission signal, A first signal output flip-flop unit for outputting a speed detection signal by inputting the first output A of the decoder to at least one serially connected flip-flop using the output of the second NAND gate as a clock; And a second output flip-flop unit configured to output the speed detection signal by inputting the output of the second NAND gate as a clock and inputting the second output B of the decoder to at least one serially connected flip-flop. Speed discrimination device. The method of claim 6, A third NAND gate NAND for outputting each flip-flop of the first flip-flop unit; A first ora gate for illuminating each flip flop output of the first flip flop portion; A first R flip-flop for inputting an output of the OR gate to an S stage S, a signal of the NAND gate to an R stage, and outputting a speed detection signal; A fourth NAND gate NAND for outputting each flop flop of the second flip-flop portion; A second ore gate for illuminating each flip-flop output of the second flip-flop portion; And a second RS flip-flop for inputting an output of the OR gate to an S stage S and an input of the NAND gate signal to an AL stage R to output a speed detection signal. Discrimination device.