KR970002963B1 - Code detecting circuit of digital signal transmission system - Google Patents

Abstract

A code detection circuit of a digital signal transmission system is disclosed. The code detection circuit of the digital signal transmission comprises: a counter control means(10) for generating enable and count reset signals and detecting a specific code by controlling a counting operation in response to a carry signal; a first counting means(20) for counting the number of same level values of first bits in the specific code; and a second counting means(40) for the number of same level values of second bits in the specific code. Thereby, the code detection circuit may appropriately detect a code of a digital signal using a couter.

Description

Code Detection Circuit in Digital Signal Transmission System

The present invention relates to a code detection circuit in a digital signal transmission system, and more particularly, to a code detection circuit suitable for detecting a code of a digital signal using a counter.

Generally, in a system for transmitting / receiving a digital signal, for example, an HDTV or another digital video transmission device, a specific portion of the beginning of a section is used to indicate a certain section of a signal to be transmitted or received, i.e., to indicate the start of a predetermined section. Send a code (hereinafter referred to as a specific code). In this case, the specific code given is only a small part of the signal data, so that the code has a long fixed length. For example, such a code used for the start recognition of a section has a form of 0 (or 1) followed by 1 (or 0) followed by 0 (or 1).

As described above, the MPEG (Motion Picture Expert Group) method belongs to these headers in a system that transmits a specific code to start recognition of a predetermined period of data. PSC (Picture Start Code) and SSC (Slice Start Code) have. If such a code is represented in hexadecimal, the PSC is 00000100 (32 bits), and the SSC is 000001 (24 bits). Therefore, in the case of transmitting a specific code having such a long length to recognize the start of a predetermined period, gate logic capable of receiving an input corresponding to each code length is needed to detect the specific code having such a long length. Done. In addition, when configuring the gate logic having many inputs as described above, it is difficult to configure in one stage, and thus, it is necessary to configure in multiple stages.

As shown above, a typical example of gate logic having a long code length and having many inputs is shown in FIG. 3.

In the figure, reference numeral 40 denotes an inverter portion composed of an inverter corresponding to the number of bits, and 50 is connected to an output side of the inverter portion 40 and a NAND gate portion composed of four NAND gates 52, 54, 56, and 58. 60 denotes an OR gate portion connected to the output side of the NAND gate portion 50 and composed of two OR gates, and 70 denotes a NOR gate connected to the output side of the OR gate portion 60.

Therefore, the conventional code detection circuit for detecting a specific code transmitted for the start recognition of a predetermined period of data with such a configuration has a complicated circuit configuration since the gate logic is connected in multiple stages for parallel processing of signals as described above. In addition, since the input signal data passes through logic formed in multiple stages, a time delay occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art, and an object thereof is to provide a code detection circuit in a digital signal transmission system that is easy to design and can suppress time delay.

In order to achieve the above object, the present invention is a code detection circuit in a digital signal transmission system for detecting a specific code transmitted for the start recognition of a predetermined period of data when transmitting and receiving a digital signal, the input of the binary code Counter control means for generating an enable signal and a count reset signal for a count operation based on data, and detecting said specific code by controlling an alternating count operation based on a carry signal; When the specific code is input as the input data, the number of the same level values of successive higher bits of the specific code is counted in response to the enable signal from the counter control means, and from the counter control means. An upper bit counter that is reset based on the reset signal to generate a carry signal; And counting the number of equal level values of successive lower bits of the specific code in response to an enable signal from the counter control means based on the input data and the carry signal generated in the higher bit counter. Provided is a code detection circuit in a digital signal transmission system comprising a lower bit counter that is reset based on a reset signal from a counter control means.

1 is a block diagram of a code detection circuit in a digital signal transmission system according to a preferred embodiment of the present invention.

FIG. 2 is a detailed block diagram showing an example of a detailed configuration of the counter controller shown in FIG.

3 is a block diagram of a code detection circuit in a conventional digital signal transmission system.

* Explanation of symbols for main parts of the drawings

10: counter control unit 20, 30: counter

40: inverter section 50: NAND gate section

52, 54, 56, 58: NAND gate 60: OR gate portion

62, 64: OR gate 70: NOR gate

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, a preferred embodiment of a code detection circuit in a digital signal transmission system according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a code detection circuit in a digital signal transmission system according to a preferred embodiment of the present invention.

In the figure, reference numerals 20 and 30 refer to the upper and lower bits of the specific code to be detected at the time of input of the transmitted data, and if the counting value reaches a predetermined value, the upper and lower bits for generating a carry are counted. Each counter represents a counter, and reference numeral 10 controls the high and low bit counters 20 and 30 based on the input data, and specifies a specific code based on a carry signal from the high and low bit counters 20 and 30. Is a counter control unit, and these components, that is, the upper and lower bit counters 20 and 30 and the counter control unit 10, constitute a substantial configuration of the present invention.

In addition, although the detailed illustration of the same figure is omitted, the upper and lower bit counters 20 and 30 may determine the number of internal flip-flops according to the consecutive number of zeros (or l) of codes to be detected.

Next, an operation process of the code detection circuit in the digital signal transmission system according to the present invention having the configuration as described above will be described.

First, when the entire system is operated and data is input to the counter control unit 10, the counter control unit 10 resets both the upper bit and lower bit counters 20 and 30 when the input data is 1 (or 0). When the input data is 0 (or 1), the upper bit counter 20 is enabled to count the number of consecutive 0s (or 1s).

In addition, the counter control unit 10 sends a reset signal to the upper bit counter 20 when l (or 0) data is input at a counter value smaller than the number of consecutive zeros of the upper bits in the code to be detected. The counter value is cleared, and then the high bit counter 20 is enabled again when 0 (or 1) data is input. If the upper bit counter 20 counts more than the number of zeros (or ls) to be detected, a carry is generated until one (or zero) data is input from the upper bit counter 20 and the counter controller ( 10, and when 1 (or 0) data is input again, the counter control unit 10 enables the upper bit counter 20 and the lower bit counter 30. FIG. In addition, when the number of consecutive 0s (or 1s) is counted in the lower bit counter 30 and the number of 0s (or 1s) to be detected is reached, the lower bit counter 30 generates a carry and outputs it to the counter controller 10. .

As described above, when the data is input, the counter controller 10 generates the carry by enabling the upper and lower bit counters 20 and 30 corresponding to the input data, respectively, as described above, thereby generating a carry. The specific code transmitted for the start recognition of the section is detected. When the specific code is detected, all counters are cleared again, and the above-described process is repeated to continuously detect the specific code.

On the other hand, as described above, according to the present invention, the counter control unit 10 for detecting the specific code by controlling the operations of the counters 20 and 30 can be configured as shown in FIG.

Referring to FIG. 2, the counter controller 10 of the present invention may include one flip-flop (F / F) 110, four end gates 120, 130, 140, and 150, and one ora gate l60. Include.

Here, for the convenience of explanation and improvement of understanding, it is assumed in the following embodiment that the start code input to the counter control unit 10, that is, the flip-flop 110, has a value of "00000000 10000000 00000000 00000000".

First, when data is input to the counter controller 10, that is, a start code is input, the input start code is delayed through the flip-flop 110. In this case, when the output of the flip-flop 110 is "0", Each output of the AND gate 120 and the AND gate 150 having one input terminal connected to the output of the flip-flop 110 has a level of "0". Therefore, the output of the OR gate 160 having one input terminal connected to the output of the AND gate 120 and the other input terminal connected to the output of the AND gate 150 also becomes "0" level.

Therefore, the upper bit counter 20 having its reset terminal rst connected to the output of the OR gate 160 and the lower bit count 30 having its reset terminal rst connected to the output of the AND gate 120 are Since all "0" levels are applied to each reset terminal, the counters 20 and 30 are reset.

At this time, the "1" level output of the AND gate 140 whose one input terminal is connected to the output of the flip-flop 110 and the other input terminal is connected to the output of the upper bit counter 20 is the upper bit counter 20. The upper bit counter 20 is enabled by being applied to the enable terminal ena, while one input terminal is connected to the output of the flip-flop 110 and the other input terminal is connected to the output of the upper bit counter 20. Connected to the other input terminal and connected to the output of the lower bit counter 30, the "0" level output of the AND gate 130 is applied to the enable terminal ena of the lower bit counter 30 so that the lower bit counter ( 30) remains disabled.

Therefore, only the upper bit counter 20 performs a count operation, and according to the operation of the upper bit counter 20, the value of consecutive "0" of the input data is counted. At this time, the upper bit counter 20 should be set to count eight "0" s, for example, when the start code is as described above.

On the other hand, when input data "1" is input before eight input data "0" is input, both the output of the AND gate 120 and the output of the OR gate 160 become "1" level. As a result, " 1 " level is applied to each reset terminal rst of each counter 20 and 30, and the " 0 " level output of the AND gate 140 is enabled terminal of the upper bit counter 20. As shown in FIG. While the upper bit counter 20 is disabled by being input to (ena), the "0" level output of the AND gate 130 is lowered by being input to the enable terminal ena of the lower bit counter 30. Bit counter 30 remains disabled.

Then, when " 0 " is input as the input data value, the high order counter 20 is reset as described above, so that the count operation is performed again. At this time, the previous count value in the upper bit counter 20 is cleared.

Next, when the input data " 1 " is input after counting eight consecutive " 0 " values of the input data, the upper bit counter 20 generates a carry signal, which is then inputted. It continues until data "0" is entered.

That is, when the input data "1" is input, the upper bit counter 20 is in a disabled state, and outputs a "1" level carry signal through its output terminal. At this time, the lower bit counter 30 maintains the disabled state, and the reset terminal rst of the upper bit counter 20 is changed from the "0" level to the "0" level.

Then, when the input data "0" is input, the output of the AND gate 150 is at the "1" level, so that the "1" level is applied to the reset terminal rst of the higher bit counter 20 as it is. Since the output of the AND gate 140 maintains the "0" level, the "0" level signal is maintained at the enable terminal ena of the upper bit counter 20. At the same time, since the output of the AND gate 120 varies from the "1" level to the "0" level, the lower bit counter 30 is reset, and since the output of the AND gate 130 also becomes the "1" level, the lower bit The counter 30 is enabled. Accordingly, the lower bit counter 30 counts input data "0" in this state, and as an example, when the start code is as described above, the lower bit counter 30 is set to count 23 "0". Should be.

On the other hand, when the input data "1" is input before 23 input data "0" is input in the above-described situation, the output of the AND gate 120 becomes the "1" level, so that each counter 20, 30 Is applied to the reset terminal rst of the " 1 " level, and the " 0 " level outputs of the two AND gates 130 and 140 are respectively input to the enable terminals ena of the respective counters 20 and 30, respectively. As a result, both counters 20 and 30 are disabled. Then, when the input data "0" is input, as described above, both counters 20 and 30 are reset (at this time, the previous count value is cleared) to start the counting operation again. At this time, since all data values inputted so far are not related to the start code to be detected according to the present invention, as described above, the data starts from the count of the input data " 0 "

On the other hand, when 23 input data "0" are input, the low bit counter 30 generates a "1" level carry signal, and the "1" level carry signal generated from the AND gate ( 120 and the AND gate 130. Therefore, by inputting the signal of level "0" to the enable terminal ena of the lower bit counter 30, the lower bit counter 30 is in a disabled state to end the counting operation and to detect the detection signal of the level "1". Output

Then, when input data " 0 " is inputted, the AND gate 120 has an output of " 0 " level, and the output of the AND gate 150 also has a " 0 " level, so that the lower bit counter 30 Reset.

That is, the specific code transmitted for the start recognition of the predetermined section of the data is detected from the input data through the above-described process, and when the specific code is detected, all counters are cleared again, and the above-described process is repeated continuously. The specific code is detected.

As described above, according to the present invention, in detecting a specific code transmitted for the start recognition of a predetermined period during transmission and reception of a digital signal, a specific code having a large number of 0 (or 1) data in a row and having many bits is detected. By using the counter means, not only the design is simpler than the conventional device but also the time delay problem caused by the multi-stage gate logic in the conventional device can be completely solved.

Claims (2)

A code detection circuit in a digital signal transmission system that detects a specific code transmitted for the start recognition of a predetermined period of data when transmitting and receiving a digital signal, the code detection circuit being enabled for a count operation based on input data of a binary code. Counter control means for generating a signal and a count reset signal and detecting the specific code by controlling an alternating count operation based on a carry signal; When the specific code is input as the input data, the number of the same level values of successive higher bits of the specific code is counted in response to the enable signal from the counter control means, and from the counter control means. An upper bit counter that is reset based on the reset signal to generate a carry signal; And counting the number of equal level values of successive lower bits of the specific code in response to an enable signal from the counter control means based on the input data and the carry signal generated in the higher bit counter. A code detection circuit in a digital signal transmission system comprising a lower bit counter that is reset based on a reset signal from a counter control means. 2. The apparatus of claim 1, wherein the counter control means comprises: a flip-flop for latching the input data according to a clock from the outside; one input terminal is connected to an output of the flip flop, and the other input terminal is connected to an output of the lower bit counter. A first AND gate coupled to provide a reset signal for the lower bit counter; A second AND gate having one input terminal connected to an output of the flip flop and the other input terminal connected to an output of the upper bit counter; An oar gate having one input terminal connected to an output of the first AND gate and the other input terminal connected to an output of the second AND gate to provide a reset signal for the higher bit count; A third AND gate having one input terminal connected to an output of the flip-flop and the other input terminal connected to an output of the upper bit counter to provide an enable signal for the upper bit counter; And one input terminal is connected to the output of the flip-flop, the other input terminal is connected to the output of the upper bit counter, and the other input terminal is connected to the output of the lower bit counter to provide the enable signal for the lower bit counter. A code detection circuit in a digital signal transmission system comprising: a fourth end gate provided.