JPH07283844A - Waveform control circuit - Google Patents

Abstract

PURPOSE:To provide a waveform control circuit capable of making a voltage level formed by connecting each of sine waves of plural periods sent from a slave set of a telephone set to a master set as a radio signal into the level where the master set measures the period of the sine waves accurately. CONSTITUTION:An output of a single flip-flop in which each sine wave changes at a specific level in each output from a shift register means 9 is given to an interrupt generating circuit 11. Thus, every time each sine wave reaches a specific level after lapse of one period, the interrupt generating circuit 11 detects an output change of the flip-flop to generate an interrupt signal and a CPU 7 detects the interrupt signal to generate a control signal CTL 2 varying a frequency of a clock signal CK. Thus, the frequency of the clock signal CK applied to the shift register means 9 is varied at a specific level of the sine wave. That is, each of sine waves outputted serially becomes a consecutive waveform connected at the specific level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform control circuit,
In particular, the present invention relates to a waveform control circuit suitable for wirelessly transmitting dial information (information in which staircase waves having different frequencies approximate to a sine wave are combined for each cycle) from a child device of a telephone to a parent device.

[0002]

2. Description of the Related Art At present, as a telephone used in each home, a cordless type in which a base unit and a handset are combined is becoming mainstream. Here, the master unit is connected to the exchange side of the central office via a telephone line. When making an outside line call using the master unit, operate the numeric keypad (0-9) for transmitting the telephone number provided on the master unit itself, and perform DT corresponding to the numeric keypad.
It is only necessary to transmit the MF wave (combined wave of two types of sine waves having different frequencies) to the exchange side via the telephone line. Then, the exchange side decodes the DTMF wave and determines the telephone number transmitted from the master unit. As a result, the user of the base unit can talk to the desired destination.

On the other hand, the slave unit is not connected to the master unit via a signal line. Therefore, when an external line call is performed using the slave, the ten-key operation information of the slave must first be wirelessly transmitted to the master. Then, the master unit decodes the ten-key operation information of the slave unit, and thereafter transmits the DTMF wave from the master unit to the exchange side in the same manner as the above operation, thereby enabling an outside call.

When transmitting the numeric keypad operation information from the slave unit to the master unit by radio, the numeric keypad operation information is generally divided into 4-bit digital data. Specifically, the numeric keys “0” to “9” are digital data “0000”.
Is equivalent to "1001". Furthermore, "0" of digital data corresponds to a sine wave having a frequency f1, and "1" of digital data corresponds to a sine wave having a frequency f2 (= 2f1). As a result, the ten-key operation information is information in which the sine wave of the frequency f1 or f2 is serially connected for four cycles depending on the type of ten-key. For example, when the numeric keypad “9” is operated, a sine wave of frequency f2 and a frequency f
A sine wave having a frequency of 1 and a sine wave having a frequency of f1 and a sine wave having a frequency of f2 are sequentially connected and wirelessly transmitted from the child device to the parent device.

FIG. 3 is a diagram showing a conventional waveform control circuit for generating the continuous sine wave. In FIG.
(1-1) to (1-16) are commonly connected at one end.
There are 6 resistors. Reference numeral (2) is a clock generator, which generates a clock signal CK by dividing the oscillation signal OSC by a predetermined frequency in accordance with an instruction from a microcomputer or the like. For example, the clock generator (2) is configured such that a plurality of T flip-flops (not shown) are cascade-connected and the number of connection stages of the plurality of T flip-flops can be switched according to the instruction. . Therefore,
The clock generator (2) can generate clock signals CK having different frequencies. (3-1) to (3-16) are
The Q (output) terminal at the front stage is a D flip-flop cascade-connected to the D (data) terminal at the rear stage, and the R (reset) terminal is connected to the source of the reset signal RST,
The C (clock) terminal is connected to the output of the clock generator (2). Furthermore, the final stage D flip-flop (2-
The Q terminal of 16) is connected to the D terminal of the first stage D flip-flop (2-1) via the inverter (4).
That is, the D flip-flops (3-1) to (3-16) are configured to circulate the shift data. The Q terminals of the D flip-flops (3-1) to (3-16) are connected to the resistors (1-1) to (1-16) via the inverters (5-1) to (5-16). Is connected to the other end of. According to the above configuration, the resistances (1-1) to (1-1)
Although a sine wave can be output from the common connection point of 6), this sine wave is formed by approximating a staircase wave.

The operation of FIG. 3 will be described below with reference to the waveform chart of FIG. Note that FIG. 4 shows a staircase wave corresponding to a sine wave, and for convenience of explanation, the change level of the staircase wave is constant. First, when the D flip-flops (3-1) to (3-16) are reset at time t0, the outputs of the inverters (5-1) to (5-16) all become high level. As shown in 4, resistance (1-1)
The maximum voltage Vdd is generated at the common connection point of (1-16). Then, at time t1, when the clock signal CK rises, the D flip-flops (3-1) to (3-1)
The data of the Q terminal of (3-15) is applied to the D terminals of the subsequent D flip-flops (3-2) to (3-16) and the data of the Q terminal of the final D flip-flop (3-16) is applied. The data is fed back to the D terminal of the first stage D flip-flop (3-1) via the inverter (4). From this, all the outputs of the remaining inverters (5-2) to (5-16) become high level except that the output of the inverter (5-1) becomes low level, and the resistors (1-1) to (1-). It is possible to generate a lower voltage from the common connection point of 16). As described above, the D flip-flops (3-1) to (3-16) repeat the shift operation based on the rising edge of the clock signal CK 32 times, whereby the D flip-flops (3-1) to (3-1).
The 16-bit output data of 6) makes one round until the state gives the staircase wave level at time t0, and a staircase wave for one cycle can be generated. The values of the resistors (1-1) to (1-16) are selected so that the staircase wave in FIG. 4 approximates a sine wave. In particular,
Value of resistance (1-1) (1-16), resistance (1-2) (1
-15) value, resistance (1-3) (1-14), ...
The values of the resistors (1-8) and (1-9) are set equal to each other.

Therefore, the frequency of the clock signal CK obtained from the clock generator (2) is controlled by the instruction of the microcomputer or the like to generate a serial waveform in which one cycle of step waves having different frequencies approximate to a sine wave are combined. I was able to do it. As a result, the parent machine recognizes the ten-key operation information of the child machine.

[0008]

Here, a staircase wave (hereinafter referred to as a sine wave) different in frequency approximate to a sine wave is
In the case of serially generating one cycle by combining the cycles, it is originally desirable to connect the sine waves at the same voltage level so that the master unit can surely recognize the frequencies of the staircase waves. For example, one cycle of each sine wave may be started from the midpoint voltage Vdd and ended at the midpoint voltage Vdd, and each sine wave may be connected with the midpoint voltage Vdd.

Generally, the master unit takes in the sine wave information transmitted from the slave unit to an inverter having a threshold voltage of Vdd / 2, and based on the output change from the low level to the high level of the inverter, the center point is set. The voltage Vdd / 2 is detected, and the time from this time until the output of the inverter changes from low level to high level again is counted. This counting content represents one cycle of the sine wave having the frequencies f1 and f2. Therefore, assuming that one cycle of a sine wave of frequency f1 or f2 is T1 and T2 (> T1), respectively, T1 <
The count content representing the time t having the relationship of t <T2 is prepared in advance. Then, the count content actually counted is compared with the prepared count content, and when the actual count content is smaller than the prepared count content, it is determined that it is a sine wave of the frequency f1, and the actual count content is Is larger than the prepared count content, it is determined to be a sine wave of frequency f2.

However, the microcomputer instructing to change the frequency of the sine wave has no means for detecting what voltage level the sine wave is at a certain time. That is, the voltage for connecting the sine waves of one cycle unit is not always set to the midpoint voltage Vdd / 2. As a result, when the sine waves are connected at voltage levels other than the midpoint voltage Vdd / 2, even if the master unit measures the cycle of this sine wave with the midpoint voltage Vdd / 2 as the reference, the frequency f1 The time from the midpoint of the sine wave of (or f2) to the midpoint of the sine wave of the next frequency f1 (or f2) is counted, and therefore, one correct cycle of the sine wave of the frequency f1 or f2 is determined. There was a problem that could not be counted. Therefore, there is a problem that the master unit cannot correctly detect the cycle of each sine wave and the ten-key operation information of the slave unit cannot be correctly transmitted to the exchange side.

Therefore, according to the present invention, the master unit can accurately measure the cycle of the sine wave with respect to the voltage level at which the sine waves of a plurality of cycles are wirelessly transmitted from the slave unit of the telephone to the master unit. An object of the present invention is to provide a waveform control circuit capable of controlling the level.

[0012]

The present invention has been made to solve the above-mentioned problems, and is characterized by a clock generating means for generating a clock signal based on an oscillation signal, Shift register means, which is formed by connecting a plurality of flip-flops in series so as to feed back the output of the final stage to the input of the first stage, circulates data in synchronization with the clock signal, and one end of each of the outputs of the shift register means And a common connection at the other end, which detects a change in the predetermined output of the ladder resistor means for generating a sine wave voltage according to the change in the contents of the shift register means from the common connection point and the predetermined output of the shift register means. An interrupt generating means for generating an interrupt signal for changing the frequency of the clock signal, and a control signal for detecting the interrupt signal and changing the frequency of the clock signal In that with the control means.

[0013]

According to the present invention, among the outputs of the plurality of flip-flop means constituting the shift register means, the single flip-flop output which changes at the position where each sine wave has a specific level is used as the interrupt generation means. Connecting. As a result, each time each sine wave reaches a specific level after one cycle, the interrupt generation means detects an output change of the flip-flop and generates an interrupt signal, and then the control means generates the interrupt signal. A signal is detected and a control signal for varying the frequency of the clock signal is generated. Therefore, the frequency of the clock signal applied to the shift register means is varied at a specific level of the sine wave. That is, each sine wave that is serially output is a continuous waveform that is connected at a specific level.

[0014]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a waveform control circuit of the present invention. still,
FIG. 1 is provided on a chip that constitutes a microcomputer, and the microcomputer is assumed to be built in the handset side of the telephone.

In FIG. 1, reference numeral (6) is a clock generator which divides the oscillation signal OSC by a predetermined frequency to generate a clock signal for operating the components inside the microcomputer. The clock generator (6)
Is configured such that a plurality of T flip-flops are cascade-connected and the number of connection stages of the T flip-flops can be switched according to an instruction from the CPU. (7) is C
The PU is for controlling the operation of each component inside the microcomputer. Reference numeral (8) is an AND gate, and the opening / closing control signal CTL1 output from the CPU (7) is applied to one input, and the clock signal CK output from the clock generator (6) is applied to the other input. .
That is, the AND gate (8) outputs the clock signal CK when the opening / closing control signal CTL1 is at the high level based on the instruction to output the sine wave waveform. (9) is 1
This is a shift register in which data input / output lines of six D flip-flops are cascade-connected, and the inverted output (* Q) of the final D flip-flop is connected to the data input (D) of the first D flip-flop. . The clock signal CK output from the AND gate (8) is applied to the C terminals of the 16 D flip-flops, and the reset signal RST is applied to the R terminals. That is, the 16 D flip-flops are reset by the clock signal C
The data shift operation is performed in synchronization with the rise of K. (1
0) is a ladder resistor network composed of 16 resistors, one end of each resistor is commonly connected, and the other end side is connected to each Q terminal of 16 D flip-flops.

FIG. 2 is a diagram showing details of the shift register (9) and the ladder resistor network (10) shown in FIG. Since FIG. 2 has the same configuration as FIG. 3, the same reference numerals are given and the description of the same portions is omitted. By the way, in the present embodiment, 4 to be transmitted from the child device to the parent device.
Each sine wave (numerical key operation information) for a period is the midpoint voltage V
It shall be connected with dd / 2 as the boundary and be continuous. Further, in FIG. 4, the staircase becomes Vdd / 2 after resetting when the D flip-flops (3-1) to (3-16) perform eight shift operations based on the clock signal CK. is there. That is, it is when the output of the D flip-flop (3-8) rises from the low level to the high level. Therefore,
In order to detect the rising change of the output Q8 of the D flip-flop (3-8), the output Q8 of the D flip-flop (3-8) is connected to the interrupt generating circuit described later.

Returning to FIG. 1, reference numeral (11) is an interrupt generating circuit, which detects a rising change in the output of the D flip-flop (3-8), that is, each sine wave from the Vdd side to the midpoint voltage Vdd /
When the state becomes 2, the interrupt signal for generating a sine wave to be connected next is generated. (1
Reference numeral 2) is a ROM, which has an area in which a main program for normally operating the microcomputer is stored and an area in which a subroutine program that jumps when the ten keys of the slave unit are operated is stored. ing. (13) is a RAM, which writes / reads the arithmetic processing result of the CPU (7) and writes 4-bit information corresponding to the ten-key operation of the slave unit according to the program instruction of the ROM (12). Is.

An example of the operation of FIG. 1 will be described below. In other words, consider a case where an outside line call is made using a child device. In this case, as described in the section of the prior art, it is necessary to serially transfer four cycles of the sine wave corresponding to the numeric keypad from the slave unit to the master unit. For example, when the number "6" of the numeric keypad is operated, the operation of the number "6" is detected by the CPU (7), and the ROM (12) interrupts the processing of the main program and jumps to the subroutine program. And
According to the program instruction of the ROM (12), 4-bit data "0110" corresponding to "6" is transferred from the internal register of the CPU (7) to the RAM (1
3) is written to the specific address, the shift register (9) is reset, and the open / close control signal CTL1 becomes high level.

Next, by the program command of the ROM (12), 4 written in a specific address of the RAM (13).
The least significant bit "0" of the bit data is taken into the CPU (7), and as a result, the clock signal C is output from the CPU (7).
K is the frequency corresponding to the data “0” (for example, 200H
z), the clock control signal CTL2 is generated. As a result, a 200 Hz clock signal CK is applied to the C terminal of the shift register (9), and a staircase wave that approximates the staircase wave shown in FIG. 4 to a sine wave is output from the ladder resistor network (10). Even if an interrupt signal is generated at the first rising change of the D flip-flop (3-8) at time t2, the CPU (7) is programmed not to accept the interrupt signal. That is, a sine wave having a frequency of 200 Hz corresponding to the data “0” is started from time t2. Then, until the sine wave reaches time t3, R
The OM (12) returns to the main program.

Next, at time t3, when the output of the D flip-flop (3-8) rises, the interrupt generation circuit (1
An interrupt signal is generated from 1), and this interrupt signal is sent to the CPU.
Detected in (7), the ROM (12) interrupts the main program processing and jumps again to the subroutine program. Then, by the program instruction of the ROM (12), the lower second bit "1" of the 4-bit data written in the specific address of the RAM (13) is the CPU (7).
Is taken into the clock C, and as a result, the clock C from the CPU (7)
K is the frequency corresponding to the data "1" (for example, 400H
z), the clock control signal CTL2 is generated. As a result, the clock signal CK of 400 Hz is applied to the C terminal of the shift register (9), and a sine wave having a frequency twice that of the sine wave having the frequency from the time t2 to the time t3 is generated from the time t3. The ROM (12) returns to the main program until the output of the D flip-flop (3-8) rises again.

Next, when the output of the D flip-flop (3-8) rises again, an interrupt signal is generated from the interrupt generation circuit (11), and this interrupt signal is detected by the CPU (7), R
The OM (12) interrupts the main program and jumps again to the subroutine program. And ROM (1
By the program instruction of 2), the lower 3rd bit "1" of the 4-bit data written in the specific address of the RAM (13) is taken into the CPU (7), and as a result, C
A clock control signal CTL from the PU (7) that sets the clock signal CK to a frequency of 400 Hz corresponding to the data "1".
2 continues to occur. As a result, the 400 Hz clock signal CK is applied to the C terminal of the shift register (9), and a sine wave having a frequency twice that of the immediately preceding sine wave is generated. The ROM (12) returns to the main program again until the output of the D flip-flop (3-8) rises again.

Finally, when the output of the D flip-flop (3-8) rises again, an interrupt signal is generated from the interrupt generation circuit (11), and this interrupt signal is detected by the CPU (7),
The ROM (12) interrupts the main program and jumps again to the subroutine program. And ROM
By the program instruction of (12), the most significant bit "0" of the 4-bit data written in the specific address of the RAM (13) is taken into the CPU (7), and as a result,
A clock control signal CT from the CPU (7) which sets the clock signal CK to a frequency of 200 Hz corresponding to the data "0".
L2 occurs. As a result, the 200 Hz clock signal CK is applied to the C terminal of the shift register (9), and a sine wave having a frequency 1/2 times that of the immediately previous sine wave is generated. From the above, it is possible to reliably connect the sine waves having the frequencies corresponding to “0” and “1” at the level of the midpoint voltage Vdd / 2. Since the ROM (12) has finished connecting the sine waves having the frequencies corresponding to the 4-bit data, the open / close control signal CTL1 is set to the low level, and the process returns to the main program.

Then, the above-mentioned 4-bit data "011
The sine wave serially output for 4 cycles corresponding to "0" is taken into the master unit, and the midpoint voltage Vdd / 2 is used as a reference in the same manner as the operation described in the section of the problem to be solved by the invention. The cycle determination is performed, and as a result, it is possible to reliably determine what numeric keypad was operated. As described above, in the case of serially transmitting four cycles of sine waves from the slave unit to the master unit, the voltage level for connecting the sine waves can be arbitrarily set according to the specifications of the cycle detection unit of the master unit. That is, on the chip of the microcomputer, the interrupt generation circuit (1
It is sufficient to select an arbitrary output of the shift register (9) connected to 1) and perform mask wiring. In this embodiment,
The sine wave is connected by the midpoint voltage Vdd / 2 according to the specifications of the parent device, but needless to say, the present invention is not limited to this.

The interrupt generation circuit (11) is configured to detect a rising change in the output of the D flip-flop (3-8), but detects a falling change and generates an interrupt signal. So that each sine wave of one cycle is
It is also possible to connect them with the middle point voltage Vdd / 2 when rising from the middle point voltage Vdd / 2. The interrupt generation circuit (11) may detect both the rising change and the falling change of the output of the D flip-flop (3-8) and generate an interrupt signal. The sine waves can be connected by the midpoint voltage Vdd / 2 every half cycle.

[0025]

According to the present invention, the master unit accurately measures the cycle of the sine wave at the voltage level at which the sine waves of a plurality of cycles are wirelessly transmitted from the slave unit of the telephone to the master unit. Therefore, there is an advantage that the master unit side can surely determine the operation information of the slave unit.

[Brief description of drawings]

FIG. 1 is a diagram showing a waveform control circuit of the present invention.

FIG. 2 is a diagram showing a main part of FIG.

FIG. 3 is a diagram showing a conventional waveform control circuit.

FIG. 4 is a waveform diagram showing a staircase wave generated in FIGS. 1 and 3.

[Explanation of symbols]

 (6) Clock generator (7) CPU (9) Shift register (10) Ladder resistor network (11) Interrupt generation circuit (12) ROM (13) RAM

Claims (3)

[Claims] 1. A clock generation means for generating a clock signal based on an oscillating signal, and a plurality of flip-flops connected in series so as to feed back an output of a final stage to an input of a first stage, which are synchronized with the clock signal. Shift register means for circulating data by connecting one end to each output of the shift register means and the other end in common, and a sine wave is formed from the common connection point according to the change of the contents of the shift register means. Ladder resistance means for generating an approximated staircase voltage, interrupt generation means for detecting a change in a predetermined output of the shift register means, and generating an interrupt signal for varying the frequency of the clock signal, A waveform control circuit comprising: a control unit that detects an embedded signal and generates a control signal that varies the frequency of the clock signal. 2. The waveform control circuit according to claim 1, wherein the interrupt generating means detects a change in a predetermined output of the shift register means when the staircase voltage reaches a specific level. 3. The waveform control circuit according to claim 2, wherein the frequency of the staircase voltage can be varied at a specific level of the staircase voltage.