JPH02164134A - Parity counting circuit - Google Patents

Abstract

PURPOSE:To decide the parity of the entire serial input data by providing a 1st parity counting means counting the parity from the head of the serial input data till one preceding bit of the final bit and a 2nd parity counting means counting the parity of the final bit. CONSTITUTION:The 1st parity counting circuit composed of a JK FF circuit 10, a D FF circuit 20 and an inverter 30 counts the parity from the leading bit of a serial input data till one preceding bit to the final bit and the count is latched at the rise of a timer pulse. On the other hand, the timer pulse and the clock are ANDed by an AND circuit 40 and the data of the final bit is latched at a D FF 21 at the rise of the pulse. An EX-OR circuit 50 exclusively ORs the output of the D FF circuit 20 and the output of the D FF circuit 21. The result is a parity counted value of all bits of the serial input data and indicates '0' when number of '1s' in the input data is an even number and indicates '1' when number of '1s' in the input data is an odd number.

Description

[Detailed Description of the Invention] [Summary] Regarding a parity counting circuit for a serially input data string, an object of the present invention is to provide a parity counting circuit that can perform parity counting for all bits of a serially input data string. and a first parity counting means for counting the parity up to one bit before the final bit of the serially input data string, a second parity counting means for counting the parity of the remaining final bit, and a first parity counting means for counting the parity of the remaining final bit. 1. A parity counting circuit comprising: a determining means for performing a parity count of all bits of a data string inputted from the output of the second parity counting means and the output of the second parity counting means.

[Industrial Application Field] The present invention relates to a parity counting circuit for serially input data strings.

If noise or momentary interruption occurs on the transmission path, data transmitted from the transmitting side will not be correctly transmitted to the receiving side.

A parity count method is widely used in boat fishing as a method of checking whether data has been received correctly.

In conventional parity counting circuits, the first bit of data is used for a frame synchronization signal and is therefore not subject to parity counting.

However, as communication networks become more sophisticated and complex, a parity counting circuit capable of parity counting of all bits of data length is required.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating a time chart of the conventional example.

The example in Fig. 4 is J in which input terminals J and K are connected in parallel.
K flip-flop circuit (hereinafter referred to as FF circuit) 10
, inverter 30 that inverts the timer pulse, and JKFF
It also includes a DFF circuit 20 for latching the output of the circuit.

The operation of the above circuit is as shown in FIG.
Serial data is input to the input terminals J and K connected in parallel of the circuit 10, and a clock signal is input to the clock terminal CK.

The timer pulse is a pulse that determines the time to perform the parity check.

The timer pulse is inverted by the inverter 30 and input to the reset terminal R of the JKFF circuit 10.

The JKFF circuit 10 is reset by this human power and does not operate during the time of this pulse width.

When the timer pulse inverted by the inverter 30 becomes "1", the JKFF circuit 10 starts operating, and every time "1" in the serial manual data arrives, the output Q becomes "1" and "0".
'' is repeated, and if the number of 1's in the input data is an even number, the output Q will be 0, and if the number is odd, the output Q will be 1.

By inputting the output Q of this JKFF circuit 10 to the input terminal of the DFF circuit 20 and inputting the timer pulse to the clock terminal, the output Q of the DFF circuit 20 will maintain its state until the next timer pulse arrives. Hold.

[Problem to be solved by the invention]

In the circuit described above, the timer pulse is transferred to the inverter 30.
Since the JKFF circuit 10 does not operate while this input is "0", the first bit of the serial input data is not subject to parity counting. Become.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parity counting circuit capable of performing parity counting of all bits of a serially inputted data string.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 1 is a first parity counting means that counts the parity from the beginning of serial input data to one bit before the final bit, and 2 is the final bit of serial input data. 3 is a determining means for determining the parity of the entire serial input data from the contents of the first parity counting means and the second parity counting means; This is a means to solve this problem.

[For production]

The first parity counting means 1 counts the number of "1"s in the serial input data from the first bit to one bit before the last bit, and if the number of "1"s is even, the output is "1". If the number of ``0'' and ``1'' is an odd number, the output is set as ``1''.

The second parity counting means 2 counts the number of "1"s in only the last bit, and if the number of "l"s is an even number, its output is "0", and if the number of "1"s is an odd number, its output is Let be "l".

The determining means 3 sets the output of the determining means 3 to "0" when the contents of the first counting means and the second counting means 2 are "even number" and "even number", and when they are "odd number" and "odd number", respectively. In addition, by setting the output of the determining means 3 to "l" when the number is "odd" or "even" and "even" or "odd," it becomes possible to count the parity of the entire serial input data.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating a time chart of an embodiment of the present invention.

The embodiment of the present invention shown in FIG. 2 uses a JKFF circuit 10 and a DFF as the first parity counting means explained in FIG.
The circuit 20 and the inverter 30, the DFF circuit 21 and the AND circuit 40 as the second counting means 2, the EX-OR circuit 50 and the inverter 3 as the determining means 3.
1 and a DFF circuit 22.60.

The operation of this circuit is as shown in the time chart of FIG.

The operation of the first parity count by the JKFF circuit 10, the DFF circuit 20, and the inverter 30 is the same as the conventional example explained in FIG. 5, but only the timing of the timer pulse is different. It should come to the last bit.

With this circuit, from the first bit of serial input data,
Count the parity up to 1 bit before the final bit,
The count value is latched at the rising edge of the timer pulse.

On the other hand, the AND circuit 4 performs the logical product of the timer pulse and the clock.
The final bit data is latched by the DFF 21 at the rising edge of this pulse.

An EX-OR circuit 50 calculates the exclusive OR of the output of the DFF circuit 20 and the DFF circuit 21. In other words, when each output is "(even number), (even number)", "(odd number), (odd number)", it is "even number", "(even number), (odd number)", "(odd number), (even number)" Outputs an odd number when .

The inverter 31 and DFF 22 determine the timing of latching the output of the EX-OR circuit, and a pulse obtained by inverting the timer pulse by the inverter 30 and a pulse obtained by inverting the clock are input to the DFF 22, and one cycle of the clock is input to the DFF 22. Generates a pulse that is an inversion of the timer pulse delayed by a minute.

By inputting the output of the EX-OR circuit 50 to the input terminal of the DFF circuit 60 and the output of the DFF circuit 22 to the clock terminal, the EX-OR circuit 50 is input until the next timer pulse is input.
The output of the OR circuit 50 is latched by the DFF circuit 60.

This result becomes the parity count value of all bits of the serial manual data, and indicates "0" if the number of "1"s in the input data is "even", and "1" if it is "odd number j".

〔Effect of the invention〕

According to the present invention as described above, it is possible to provide a parity counting circuit that targets all bits of serial input data for parity counting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart of an embodiment of the present invention, and FIG. 4 is a conventional block diagram. A block diagram illustrating an example, and FIG. 5 a diagram illustrating a time chart of a conventional example are shown, respectively. In the figure, l is the first parity counting means, 2 is the second parity counting means, 3 is the judgment means, 10 is the JKFF circuit, 20.2L22.60 is the DFF circuit, 30.31 is the inverter, 40 is the AND circuit , 50 is an EX-OR circuit, respectively. Figure 2: A block diagram explaining the present invention in detail Figure 1: A block diagram explaining the conventional example Figure 4: A block diagram explaining the present invention in detail

Claims (1)

[Scope of Claim] A parity counting circuit for a serially input data string, comprising a first parity counting means ( 1), a second parity counting means (2) that counts the parity of the remaining final bit, and an output of the first parity counting means (1) and the second parity counting means (2). ) A parity counting circuit characterized in that it comprises a determining means (3) for performing a parity count of all bits of a data string inputted from the output of the circuit.