KR19990056144A - Timing delay circuit of reset signal in key phone system - Google Patents

Abstract

The technical field to which the invention described in the claims belongs.

A reset circuit of a key phone system.

The technical problem that foot is going to solve

Provided is a circuit that can delay the timing of a reset signal in a key phone system.

C. Summary of the Solution

In a circuit for delaying the timing of the reset signal, the conventional power supply " on " reset circuit includes a latch for delaying the timing of the reset signal and an output signal of the latch when the line card is mounted, " logic " Low " to output the logic " low " signal to delay the timing of the reset signal.

D. Significant Uses of the Invention

Used to delay the timing of the reset signal.

Description

Timing delay circuit of reset signal in key phone system

The present invention relates to a key phone system, and more particularly to a reset circuit of the key phone system.

In general, in the conventional key phone system, the reset signal generated when the power is turned “on” is applied to the main Jaarcard processor and the line card processor to initialize each card.

FIG. 1 is a circuit diagram illustrating a power-on " on " reset circuit of a conventional key phone system. Referring to FIG. 1, when a power supply voltage Vcc is applied, a time constant by a resistor R1 and a capacitor C1 is applied. A reset signal is generated by the R1 x C1 to the key phone system and applied to the main control card processor and the processor of each line card. Accordingly, the main control card processor and the processor of each line card are initialized.

However, in the above-described conventional reset circuit, since the reset signal whose timing is determined only by the time constant R1 x C1 is applied to the processor of each line card through the main control card processor, the timing of the reset signal is long or short. In the processor, there is a problem that an error may occur in the reset operation by the reset signals of the same timing.

As described above, since the reset signals are collectively generated and applied when the power is "on," there is a problem that an error may occur in the reset operation in line card processors having different reset timings.

Accordingly, an object of the present invention is to provide a circuit capable of delaying reset timing for each line card processor.

1 is a configuration diagram of a reset circuit of a conventional key phone system;

2 is a block diagram of a timing delay circuit of a reset signal in a key phone system according to an exemplary embodiment of the present invention.

The present invention for achieving the above object is a circuit for delaying the timing of the reset signal, the conventional power supply " on " And a diode (Diode) for outputting the logic "low" signal to delay the timing of the reset signal when the output signal of -Latch is in the "0" state, that is, the logic "low".

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

2 is a circuit diagram illustrating a timing delay circuit of a reset signal according to an exemplary embodiment of the present invention. Referring to FIG. 2, the reset signal time constant R1 × C1 is first determined by the resistor R1 and the capacitor C1. The first diode D1 makes a discharge path so that discharge can occur quickly when the power supply voltage Vcc is "off". The latch 200 has a "1" state, that is, a logic "high" or "0" state, that is, logic when the clock signal input to the clock input terminal CLK is enabled in a "1" state, that is, a logic "high." The input signal D0 of "low" is output to the output terminal Q. The second diode D2 is " on " when the signal output from the output terminal Q of the latch 200 is in the " 0 " Delay x C1). In addition, if the signal output from the output terminal Q of the latch 200 is in a "1" state, that is, a logic "high" signal, it is "off" so that the logic "high" signal is a time constant (R1 x C1) of a reset signal. Blocking does not affect.

Therefore, the processor of the main control card of the key phone system can delay the timing of the reset signal applied to each line card processor by applying a "0" status signal to the latch.

As described above, the present invention desires the timing of the reset signal applied to each line card processor by applying a "0" status signal to the latch in addition to the reset signal generated when the power is "on" in the key phone system. This can be delayed as much as possible so that an error does not occur in the reset operation in each line card.

Claims (1)

In a circuit for delaying the timing of a reset signal in a keyphone system, A power supply voltage for supplying power to the key phone system; A resistor and a capacitor connected in series with the power supply voltage to determine a time constant of the reset signal; A first diode connected in parallel to the resistor to form a discharge path for promoting a discharge when the power supply voltage is “off”; A latch connected between the resistor and the capacitor and outputting a signal input to an input terminal to an output terminal when a clock signal is enabled; And a second diode which selectively outputs the output signal of the latch to delay the timing of the reset signal.