KR19990053968A - Device isolation film formation method of semiconductor device and its structure - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for forming a device isolation film of a semiconductor device which prevents a decrease in reliability of a gate oxide film, and a structure thereof. The PSL device isolation film is formed by defining an active region and a device isolation region on a semiconductor substrate. A poly spacer for preventing active recess is formed on both sidewalls of the upper protruding portion of the device isolation layer. And forming a sacrificial oxide layer by oxidizing the semiconductor substrate including the poly spacer, and etching the sacrificial oxide layer and the device isolation layer by an etch back process to planarize the upper surface of the device isolation layer. At this time, the width of the upper portion of the device isolation layer is relatively wider than the width of the lower portion. According to such a device isolation film formation method and structure of the semiconductor device, the etch back etching margin of the device isolation film at the boundary between the active region and the device isolation region can be increased by using the poly spacer for preventing the active recess, and thus the active recess. Can be prevented and the reliability deterioration of the gate oxide film can be prevented.

Description

A method of forming field oxide of semiconductor device and a structure formed according to

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation layer (field oxide) of a semiconductor device and a structure thereof, and more particularly, to a device isolation film of a semiconductor device which prevents a decrease in the reliability of a gate oxide. A method of formation and its structure.

In general, LOCOS (LOCal Oxidation of Silicon) in the device isolation film forming method of a semiconductor device has been widely used because of its simple process.

However, in order to reduce excessive bird's beaks generated at the edges of device isolation layers as device spacing becomes smaller, device isolation layers or device isolation layers having other structures have emerged by the modified LOCOS method.

That is, poly-Si buffered LOCOS (hereinafter referred to as 'PBL') or poly-spacer LOCOS (hereinafter referred to as 'PSL') or shallow trench isolation (hereinafter referred to as 'STI'). And so on.

In particular, the device isolation film by the PSL method is most widely used in devices having fewer processes than the STI method, easy to process, and an isolation width of sub-half micrometers.

1 is a cross-sectional view showing a device isolation film 22a of a conventional semiconductor device.

Referring to FIG. 1, unlike the device isolation film of the conventional LOCOS method, the PSL device isolation film 22a of the conventional semiconductor device does not have an excessively large bird big.

However, the PSL device isolation film 22a almost inevitably has an active recess 26 at the boundary between the device isolation region (field region) and the device formation region (active region) after the device isolation film forming process is performed. ) Is generated.

This concentrates thinning phenomenon and stress of the gate oxide layer 28 formed in a subsequent process in the active recess 26 region, thereby weakening the reliability of the gate oxide layer 28.

Further, in the current trend of forming a thinner gate oxide film thickness in response to the demand for low voltage and higher speed characteristics for the device, a decrease in the reliability of the gate oxide film 28 due to the active recess is a serious problem. .

2A to 2E are cross-sectional views sequentially illustrating a method of forming the device isolation film 22a of a conventional semiconductor device.

Referring to FIG. 2A, in the method of forming the device isolation film 22a of the conventional semiconductor device, first, the pad oxide film 12 and the silicon nitride film 14 are formed on the semiconductor substrate 10, and the device isolation region 16 is formed. The silicon nitride film 14 and the pad oxide film 12 are etched to expose a portion of the semiconductor substrate 10.

2B to 2C, after the thin oxide film 18 is formed on the semiconductor substrate 10 of the device isolation region 16, the pad oxide film 12 and the pad isolation layer 12 are formed on the device isolation region 16. The poly spacer 20 is formed to contact the silicon nitride film 14.

Next, referring to FIG. 2D, the device isolation layer 22 is formed in the device isolation region 16 including the poly spacer 20. After removing the silicon nitride film 14 and the pad oxide film 12 in the element formation region, a sacrificial oxide 24 is formed on the entire surface of the semiconductor substrate 10.

In this case, the sacrificial oxide layer 24 removes silicon nitride layers, called white ribbons or silicon nitride spots, formed at the interface between the pad oxide layer 12 and the semiconductor substrate 10 when the device isolation layer 22 is formed. It is formed to.

Subsequently, the sacrificial oxide film 24 and the field oxide film 22 are etched back to form the PSL device isolation layer 22a as shown in FIG. 2E.

In this case, the active recess 26 inevitably caused at the boundary point between the PSL device isolation layer 22a and the element formation region may have a thickness of the device isolation layer 22 of reference numeral 25 in FIG. 2D. This is caused by having a weak thickness margin over time.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and it is possible to prevent active recesses in the PSL device isolation film forming process, and thus to improve the reliability of the gate oxide film. The purpose is to provide.

1 is a cross-sectional view showing a device isolation film of a conventional semiconductor device;

2A to 2E are cross-sectional views sequentially showing a method of forming a device isolation film of a conventional semiconductor device;

3 is a cross-sectional view showing a device isolation film of a semiconductor device according to an embodiment of the present invention;

4A through 4E are cross-sectional views sequentially illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 102: pad oxide film

14 silicon nitride film 16 device isolation region

18: thin oxide film 20: poly spacer

22, 104: device isolation layer 24, 108: sacrificial oxide film

22a, 104a: device isolation layer 26: active recess

28, 112: gate oxide film 106: polysilicon film

106a: Poly spacer 114: F-POLY membrane

(Configuration)

According to the present invention for achieving the above object, a method of forming a device isolation film of a semiconductor device comprises the steps of: forming an active region and a device isolation region on a semiconductor substrate to form a PSL device isolation film; Forming a poly spacer for preventing active recess on both side walls of the protruding portion of the device isolation layer, the device isolation layer having a structure protruding from both sides thereof; Oxidizing the semiconductor substrate including the poly spacer to form a sacrificial oxide film on the semiconductor substrate; Etching the sacrificial oxide layer and the device isolation layer by an etch back process to planarize an upper surface of the device isolation layer.

In a preferred embodiment of this method, the poly spacer is formed of a doped polysilicon film.

In a preferred embodiment of this method, the polysilicon film has a thickness of about 500 GPa or less.

In a preferred embodiment of this method, the thickness of the sacrificial oxide film at the poly spacer formation site is about 1000 GPa or less.

In a preferred embodiment of this method, the width of the upper portion of the device isolation layer etched by the etch back process is relatively wider than the width of the lower portion thereof.

According to the present invention for achieving the above object, the device isolation film structure of the semiconductor device is a width of the upper portion of the PSL device isolation film in the structure of the PSL device isolation film formed by defining the active region and the device isolation region of the semiconductor device. a) is relatively wider than the width b of the lower portion thereof, and a boundary between the active region and the device isolation layer is formed parallel to the surface of the active region.

(Action)

The device isolation film formation method and structure of the semiconductor device according to the present invention prevent active recesses in the PSL device isolation film formation step, thereby preventing the reliability of the gate oxide film formed in the subsequent step.

(Example)

Referring to FIG. 4E, the method and structure of the device isolation film 104a of the novel semiconductor device according to the embodiment of the present invention define an active region and a device isolation region on the semiconductor substrate 100 to define a PSL device isolation film ( 104). Then, active spacer prevention poly spacers 106a are formed on both sidewalls of the upper protruding portion of the device isolation layer 104. After the sacrificial oxide layer 108 is formed by oxidizing the semiconductor substrate 100 including the poly spacer 106a, the sacrificial oxide layer 108 and the device isolation layer 104 are etched by an etch back process to etch the device isolation layer. Planarizing the top surface of 104. In this case, the width a of the upper portion of the device isolation layer 104 is relatively wider than the width b of the lower portion of the device isolation layer 104. With such a method and structure of forming the device isolation film 104a of the semiconductor device, the etch back etching margin of the device isolation film at the boundary between the active region and the device isolation region can be increased by using the poly spacer 106a for preventing the active recess. Therefore, the active recess can be prevented and the reliability deterioration of the gate oxide film can be prevented.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 to 4.

3 is a cross-sectional view illustrating a device isolation layer 104a of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, in the structure of the PSL device isolation film 104a according to the embodiment of the present invention, the width a of the upper portion of the device isolation film 104a is the width b of the lower portion of the device isolation film 104a. Relatively wider. The boundary between the active region and the device isolation region is formed parallel to the surface of the active region. That is, it does not have an active recess. The device isolation film 104a includes a gate oxide film 112 formed in the active region.

The method of forming the element isolation film 104a of the semiconductor device as described above is as follows.

4A through 4E are cross-sectional views sequentially illustrating a method of forming the device isolation film 104a of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, in the method of forming the device isolation film 104a of the semiconductor device, the PSL device isolation film 104 is formed by defining an active region and a device isolation region on the semiconductor substrate 100. At this time, the pad oxide layer 102 remains in the active region.

More specifically, a pad oxide film 102 having a thickness of about 240 mW is formed on the semiconductor substrate 100, and then an active silicon nitride film having a thickness of about 1500 mW is formed on the pad oxide film 102 (not shown). To form. The silicon nitride film and the pad oxide film 102 are etched and patterned to expose the upper surface of the semiconductor substrate 100 in the device isolation region.

Next, a thin oxide film having a thickness of about 80 kV is formed on the exposed semiconductor substrate 100, and a poly spacer (not shown) is formed on both sidewalls of the exposed portion using a polysilicon film (not shown). Not shown).

Thereafter, the semiconductor substrate 100 and the poly spacer of the exposed portion are oxidized to form the device isolation layer 104 and to remove the silicon nitride layer.

In this case, the device isolation layer 104 has a structure in which both sides thereof protrude in the shape of an ear or a telephone receiver. Such a structure appears because a poly spacer is used for the element isolation region in the PSL forming step.

In FIG. 4B, the polysilicon film 106 is formed on the pad oxide film 102 including the device isolation film 104 at a thickness of 500 kPa or less, for example, about 350 kPa. In this case, the polysilicon film 106 may be doped with n-type impurity ions or the like in order to facilitate oxidation during the subsequent sacrificial oxide film 108 process.

Next, referring to FIG. 4C, the polysilicon layer 106 is etched to form poly spacers 106a on both sidewalls of the protruding portions of the device isolation layer 104.

In FIG. 4D, the sacrificial oxide film 108 is formed on the semiconductor substrate 100 by oxidizing the semiconductor substrate 100 including the poly spacer 106a.

In this case, the sacrificial oxide film 108a at the portion where the poly spacer 106a is formed has a thickness of about 1000 GPa or less, for example, about 700 GPa or less. On the other hand, the sacrificial oxide film 108b of the active region is formed to have a thickness of about 300 kV relatively smaller than that of the sacrificial oxide film 108a of the poly spacer 106a forming region because the existing pad oxide film 102 exists.

The sacrificial oxide film 108a at the boundary portion 110 of the active region and the device isolation layer 104 increases the etch margin for this portion 110 during the subsequent etch back process.

Finally, when the sacrificial oxide layer 108 and the device isolation layer 104 are etched to etch back to planarize the upper surface of the device isolation layer 104, as shown in FIG. 4E, the PSL device having no active recess is shown. The separator 104a is completed.

In this case, the width a of the upper portion of the device isolation layer 104a is wider than the width b of the lower portion of the device isolation layer 104a. As indicated by the reference numeral 111, as both upper portions of the device isolation layer 104a become positive, isolation effects on a subsequent ion implantation process, for example, a channel stop ion implantation process, may be obtained. Increase

Again, referring to FIG. 3, the increase in the width of the upper portion of the device isolation film 104a increases the margin of space (c) in a critical process such as the formation of the F-POLY film 114 of the flash memory product. Let's do it.

The method of forming the device isolation film 104a of the semiconductor device and the structure thereof as described above increase the thickness of the sidewall oxide film of the PSL device isolation film 104a, so that the boundary between the active region and the device isolation film 104 during the subsequent etch back process ( Ensure sufficient etching margin of 110).

The present invention can prevent active recesses occurring at the boundary portion between the active region and the device isolation film, thereby preventing the reliability of the gate oxide film from decreasing. In addition, there is an effect that can improve the sequestration characteristics for subsequent ion implantation, and increase the F-POLY space margin.

Claims (6)

Defining an active region and a device isolation region on the semiconductor substrate 100 to form a PSL device isolation film 104; The device isolation layer 104 has a structure in which both sides thereof protrude, Forming active spacer preventing poly spacers 106a on both sidewalls of the protruding portions of the device isolation layer 104; Oxidizing the semiconductor substrate (100) including the poly spacer (106a) to form a sacrificial oxide film (108) on the semiconductor substrate (100); And etching the sacrificial oxide film (108) and the device isolation film (104) by an etch back process to planarize an upper surface of the device isolation film (104). The method of claim 1, And the poly spacer (106a) is formed of a doped polysilicon film (106). The method of claim 2, And the polysilicon film (106) has a thickness of about 500 GPa or less. The method of claim 1, The thickness of the sacrificial oxide film (108a) at the site where the poly spacer (106a) is formed is about 1000 GPa or less. The method of claim 1, And a width (a) of an upper portion of the device isolation layer (104a) etched by the etch back process is relatively wider than a width (b) of the lower portion thereof. In the PSL device isolation film structure formed by defining an active region and a device isolation region of a semiconductor device, The width a of the upper portion of the PSL device isolation layer 104a is relatively wider than the width b of the lower portion thereof. A boundary portion between the active region and the device isolation layer 104a is formed in parallel with the surface of the active region.