KR19990050862A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- KR19990050862A KR19990050862A KR1019970070053A KR19970070053A KR19990050862A KR 19990050862 A KR19990050862 A KR 19990050862A KR 1019970070053 A KR1019970070053 A KR 1019970070053A KR 19970070053 A KR19970070053 A KR 19970070053A KR 19990050862 A KR19990050862 A KR 19990050862A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title description 15
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims 2
- 230000001590 oxidative effect Effects 0.000 claims 2
- 239000000969 carrier Substances 0.000 abstract description 5
- 239000004020 conductor Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 게이트전극 에지부 아래에도 다수의 LDD영역을 형성함으로써, 핫 캐리어를 방지하여 소자의 신뢰성을 향상시키기 위한 반도체소자를 제공하기 위한 것으로써, 반도체기판과, 상기 반도체기판상의 소정부분에 형성된 제 1 두께를 갖는 게이트절연막상에 형성된 게이트전극과, 상기 게이트전극 양측면에 차례로 형성된 다수층의 도전성측벽들과, 상기 도전성측벽들과 상기 반도체기판 사이에 형성된 제 2 두께를 갖는 게이트절연막과, 상기 각 도전성측벽들에 상응하는 반도체기판 표면내에 형성된 다수의 LDD영역들과, 상기 도전성측벽들중 최외각 도전성측벽 양측의 반도체기판 표면내에 형성된 소오스 및 드레인 불순물영역을 포함하여 구성되는 것을 특징으로 한다.The present invention is to provide a semiconductor device for improving the reliability of the device to prevent hot carriers by forming a plurality of LDD regions under the gate electrode edge, which is formed on the semiconductor substrate and a predetermined portion on the semiconductor substrate. A gate electrode formed on the gate insulating film having a first thickness, a plurality of conductive side walls formed on both sides of the gate electrode, a gate insulating film having a second thickness formed between the conductive side walls and the semiconductor substrate, and And a plurality of LDD regions formed in the semiconductor substrate surface corresponding to each of the conductive side walls, and source and drain impurity regions formed in the semiconductor substrate surface on both sides of the outermost conductive side wall among the conductive side walls.
Description
본 발명은 반도체소자에 관한 것으로 특히, 핫-캐리어 효과를 방지하는데 적당한 반도체소자및 이의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to semiconductor devices suitable for preventing the hot-carrier effect and a method of manufacturing the same.
일반적으로 반도체 집적회로에 있어서, 성능이 우수하면서 고집적화된 반도체집적회로를 얻기 위해 반도체 집적회로를 구성하는 트랜지스터의 사이즈를 줄이기 위한 연구가 계속되고 있다.BACKGROUND ART In general, in semiconductor integrated circuits, research for reducing the size of a transistor constituting a semiconductor integrated circuit has been continued to obtain a highly integrated semiconductor integrated circuit having excellent performance.
이러한 노력의 결과로 반도체 집적회로의 제조기술이 서브 마이크론(sub-micron)수준으로 스케일 다운(scale down)되기에 이르렀다.As a result of these efforts, the manufacturing technology of semiconductor integrated circuits has been scaled down to sub-micron level.
반도체소자의 축소크기는 수평치수의 축소와 아울러 이에 비례한 수직치수의 축소가 이루어져야 여러소자의 특성들과의 균형을 이룰 수 있다.The reduction size of the semiconductor device must be balanced with the characteristics of the various devices only when the horizontal dimension is reduced and the vertical dimension is proportionally reduced.
즉, 소자의 크기가 줄어들면 예컨대, 트랜지스터에 있어서 소오스와 드레인간의 간격이 가까워지면 원하지 않는 소자의 특성변화가 발생하게 되는데 그 대표적인 것이 숏 채널(short channel)효과이다.In other words, when the size of the device is reduced, for example, when the gap between the source and the drain in the transistor is close, unwanted characteristics change of the device may occur. The representative example is the short channel effect.
숏 채널효과를 해결하기 위해서는 수평치수(게이트 길이)의 축소와 아울러 수직치수(게이트절연막의 두께, 접합깊이 등)를 줄여야하며, 또한 이에따라 인가전압을 낮추고 기판의 도핑농도를 높이며 특히 채널영역의 도핑 프로파일을 조절하여야 한다.In order to solve the short channel effect, it is necessary to reduce the horizontal dimension (gate length) and to reduce the vertical dimension (thickness of the gate insulating film, the junction depth, etc.). The profile should be adjusted.
그러나 소자의 동작전원은 그 소자를 사용하는 전자제품에서 요구하는 값을 만족시켜야 하므로 반도체소자의 치수는 축소되고 있지만 아직 반도체를 사용하는 전자제품에서 요구하는 동작전원은 감소되지 않고 있기 때문에 반도체소자 특히, NMOS트랜지스터의 경우 소오스와 드레인 사이의 간격이 줄어들게 됨에 따라 발생하는 숏 채널효과로 인하여 소오스에서 인가된 전자가 드레인 근처의 급격한 고전계에 의해 가속되어 발생하는 핫 캐리어(hot carrier)에 취약한 구조를 가지게 된다.However, since the operating power of the device must satisfy the value required by the electronic product using the device, the dimensions of the semiconductor device are being reduced, but the operating power required by the electronic product using the semiconductor has not been reduced yet. In the case of NMOS transistors, due to the short channel effect that occurs as the gap between the source and the drain decreases, the structure of the NMOS transistor is susceptible to hot carriers, which are accelerated by the high electric field near the drain. Have.
이러한 핫 캐리어는 숏 채널과 높은 인가전압에서 기인한 드레인 접합 근처에서 매우 높은 전계가 그 원인이다.This hot carrier is caused by a very high electric field near the drain junction due to the short channel and high applied voltage.
이하, 종래 반도체소자 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a conventional semiconductor device manufacturing method will be described with reference to the accompanying drawings.
도 1a 내지 1d는 종래기술에 따른 반도체소자 제조방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 1a에 도시한 바와같이, 선택적으로 필드산화막(도시되지 않음)이 형성된 반도체기판(11)상의 활성영역에 게이트절연막(12)을 형성한다.As shown in Fig. 1A, a gate insulating film 12 is formed in an active region on a semiconductor substrate 11 on which a field oxide film (not shown) is selectively formed.
그리고, 상기 게이트절연막(12)상에 게이트전극용 폴리실리콘층(13)과 캡절연막(14)을 차례로 형성한다.The polysilicon layer 13 for the gate electrode 13 and the cap insulation layer 14 are sequentially formed on the gate insulation layer 12.
이어, 도 1b에 도시한 바와같이, 상기 캡절연막(14)상에 포토레지스트(도시되지 않음)를 도포한 후, 노광 및 현상공정으로 상기 포토레지스트를 패터닝한다.Subsequently, as shown in FIG. 1B, a photoresist (not shown) is applied on the cap insulating film 14, and then the photoresist is patterned by an exposure and development process.
상기 패터닝된 포토레지스트를 마스크로 이용한 식각공정으로 상기 캡 절연막(14), 폴리실리콘층(13)을 차례로 제거하여 게이트전극(13a)을 형성한다.The gate insulating layer 13a is formed by sequentially removing the cap insulating layer 14 and the polysilicon layer 13 by an etching process using the patterned photoresist as a mask.
이후, 도 1c에 도시한 바와같이 상기 게이트전극(13a)을 마스크로 이용한 불순물 이온주입으로 상기 게이트전극(13a)양측의 기판(11)표면내에 LDD영역(15)을 형성한다.Thereafter, as illustrated in FIG. 1C, the LDD region 15 is formed in the surface of the substrate 11 on both sides of the gate electrode 13a by impurity ion implantation using the gate electrode 13a as a mask.
이어서, 상기 게이트전극(13a)을 포함한 반도체기판(11)전면에 절연층을 형성한 후, 상기 절연층을 에치백하여 도 1d에 도시한 바와같이 상기 게이트전극(13a)양측면에 절연측벽(1a)을 형성한다.Subsequently, after the insulating layer is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 13a, the insulating layer is etched back to form insulating side walls 1a on both sides of the gate electrode 13a as shown in FIG. ).
그리고, 상기 절연측벽(16) 및 게이트전극(13a)을 마스크로 이용한 불순물 이온주입으로 소오스 및 드레인 불순물영역(17,17a)을 형성한다.The source and drain impurity regions 17 and 17a are formed by implanting impurity ions using the insulating side wall 16 and the gate electrode 13a as a mask.
그러나 상기와 같은 종래 반도체소자 제조방법은 소자가 집적화됨에 따라 채널길이가 감소하게 되고, 이로인해 핫 캐리어 효과를 초래하여 소자의 신뢰성을 저하시키는 문제점이 있었다.However, the conventional method of manufacturing a semiconductor device as described above has a problem in that the channel length is reduced as the device is integrated, thereby causing a hot carrier effect to reduce the reliability of the device.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로써, 계단형상의 게이트절연막과, 소오스 및 드레인접합 근처의 도핑농도를 다중으로하여 핫 캐리어를 방지하는데 적당한 반도체소자 및 이의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a stepped gate insulating film, a semiconductor device suitable for preventing hot carriers by multiple doping concentrations near source and drain junctions, and a method of manufacturing the same. There is a purpose.
도 1a 내지 1d는 종래기술에 따른 반도체소자 제조방법을 설명하기 위한 공정단면도1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 2는 본 발명에 따른 반도체소자의 구조단면도2 is a structural cross-sectional view of a semiconductor device according to the present invention.
도 3a 내지 3g는 본 발명에 따른 반도체소자 제조방법을 설명하기 위한 공정단면도3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11,21 : 반도체기판 27,30,33 : 제 1, 제 2, 제 3 도전성측벽11, 21 semiconductor substrate 27, 30, 33: first, second, third conductive side wall
25,28,31 : 제 1, 제 2, 제 3 LDD영역25, 28, 31: 1st, 2nd, 3rd LDD region
상기의 목적을 달성하기 위한 본 발명의 반도체소자는 반도체기판과, 상기 반도체기판상의 소정부분에 형성된 제 1 두께를 갖는 게이트절연막상에 형성된 게이트전극과, 상기 게이트전극 양측면에 차례로 형성된 다수층의 도전성측벽들과, 상기 도전성측벽들과 상기 반도체기판 사이에 형성된 제 2 두께를 갖는 게이트절연막과, 상기 각 도전성측벽들에 상응하는 반도체기판 표면내에 형성된 다수의 LDD영역들과, 상기 도전성측벽들중 최외각 도전성측벽 양측의 반도체기판 표면내에 형성된 소오스 및 드레인 불순물영역을 포함하여 구성되고, 본 발명의 반도체소자 제조방법은 반도체기판상의 소정부분에 제 1 두께를 갖는 게이트절연막을 형성한 후, 상기 게이트절연막상에 캡절연막을 갖는 게이트전극을 형성하는 공정과, 상기 게이트전극의 양측면에 차례로 다수층의 도전성측벽들을 형성하는 공정과, 상기 각 도전성측벽들에 상응하는 반도체기판의 표면내에 다수의 LDD영역들을 형성하는 공정과, 상기 도전성측벽들중 최외각의 도전성측벽 양측의 반도체기판 표면표면내에 소오스 및 드레인 불순물영역을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.A semiconductor device of the present invention for achieving the above object is a semiconductor substrate, a gate electrode formed on a gate insulating film having a first thickness formed on a predetermined portion on the semiconductor substrate, and a plurality of layers of conductive formed in turn on both sides of the gate electrode A gate insulating film having sidewalls, a second thickness formed between the conductive sidewalls and the semiconductor substrate, a plurality of LDD regions formed in the surface of the semiconductor substrate corresponding to the respective conductive sidewalls, and the most of the conductive sidewalls. And a source and drain impurity region formed in the surface of the semiconductor substrate on both sides of the outer conductive side wall, and the method of manufacturing a semiconductor device of the present invention comprises forming a gate insulating film having a first thickness on a predetermined portion on the semiconductor substrate, and then Forming a gate electrode having a cap insulating film on the film, and both side surfaces of the gate electrode; Forming a plurality of conductive side walls in turn, forming a plurality of LDD regions in the surface of the semiconductor substrate corresponding to the respective conductive side walls, and a surface of the semiconductor substrate on both sides of the outermost conductive side walls among the conductive side walls. And forming a source and a drain impurity region in the surface.
이하, 본 발명의 반도체소자 및 이의 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a semiconductor device and a method of manufacturing the same will be described with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체소자의 구조단면도이다.2 is a structural cross-sectional view of a semiconductor device according to the present invention.
도 2에 도시한 바와같이, 제 1 두께를 갖는 게이트절연막상에 형성된 게이트전극(24)과, 상기 게이트전극(24)양측에 형성된 제 1 도전성측벽(27)과, 상기 제 1 도전성측벽(27)의 측면에 형성된 제 2 도전성측벽(30)과, 상기 제 2 도전성측벽(30)의 측면에 형성된 제 3 도전성측벽(33)과, 상기 제 1, 제 2, 제 3 도전성측벽(27,30,33)에 상응하는 반도체기판(21)의 표면내에 형성된 제 1, 제 2, 제 3 LDD영역(25,28,31)과, 상기 제 3 도전성측벽(33)양측의 반도체기판(21)표면내에 형성된 소오스 및 드레인 불순물영역(34,34a)을 포함하여 구성된다.As shown in Fig. 2, the gate electrode 24 formed on the gate insulating film having the first thickness, the first conductive side wall 27 formed on both sides of the gate electrode 24, and the first conductive side wall 27 2nd conductive side wall 30 formed in the side surface of (), the 3rd conductive side wall 33 formed in the side surface of the said 2nd conductive side wall 30, and the said 1st, 2nd, 3rd conductive side wall (27, 30). Surface of the semiconductor substrate 21 on both sides of the first, second and third LDD regions 25, 28 and 31 formed in the surface of the semiconductor substrate 21 corresponding to And source and drain impurity regions 34 and 34a formed therein.
여기서, 상기 제 1, 제 2, 제 3 도전성측벽(27,30,33)들과 상기 반도체기판(21)사이에는 상기 제 1 두께를 갖는 게이트절연막보다 더 두꺼운 게이트절연막이 형성된다.Here, a gate insulating film thicker than the gate insulating film having the first thickness is formed between the first, second and third conductive side walls 27, 30 and 33 and the semiconductor substrate 21.
그리고, 상기 제 2 LDD영역(28)의 접합깊이 및 불순물농도는 제 1 LDD영역(25)보다 더 깊고 크다.The junction depth and impurity concentration of the second LDD region 28 are deeper and larger than those of the first LDD region 25.
상기 제 3 LDD영역(31)의 접합깊이 및 불순물농도는 상기 제 2 LDD영역(28)보다 더 깊고 크다.The junction depth and impurity concentration of the third LDD region 31 are deeper and larger than that of the second LDD region 28.
또한, 상기 제 1, 제 2, 제 3 도전성측벽(27,30,33)들은 폴리실리콘으로 이루어진다.In addition, the first, second and third conductive side walls 27, 30, 33 are made of polysilicon.
이와같이 구성된 본 발명의 반도체소자 제조방법을 설명하면 다음과 같다.Referring to the semiconductor device manufacturing method of the present invention configured as described above is as follows.
도 3a 내지 3g는 본 발명의 반도체소자 제조방법을 설명하기 위한 공정단면도이다.3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
도 3a에 도시한 바와같이, 반도체기판(21)상에 제 1 게이트절연막(22)을 형성한다.As shown in FIG. 3A, a first gate insulating film 22 is formed on the semiconductor substrate 21.
상기 제 1 게이트절연막(22)상에 폴리실리콘층과 절연층을 차례로 증착한 후 선택적으로 제거하여 캡절연막(23)을 갖는 게이트전극(24)을 형성한다.A polysilicon layer and an insulating layer are sequentially deposited on the first gate insulating film 22 and then selectively removed to form a gate electrode 24 having a cap insulating film 23.
이어, 상기 게이트전극(24)을 마스크로 이용한 불순물 이온주입으로 상기 게이트전극(24)양측의 반도체기판(21)표면내에 제 1 LDD영역(25)을 형성한다.Subsequently, the first LDD region 25 is formed in the surface of the semiconductor substrate 21 on both sides of the gate electrode 24 by impurity ion implantation using the gate electrode 24 as a mask.
그리고, 상기 게이트전극(24)을 포함한 기판(21)전면에 절연층을 형성한 후, 에치백하여 상기 게이트전극(24)의 양측면에 제 1 절연측벽(26)을 형성하고, 산화공정을 실시한다.After the insulating layer is formed on the entire surface of the substrate 21 including the gate electrode 24, the substrate is etched back to form first insulating side walls 26 on both sides of the gate electrode 24, and an oxidation process is performed. do.
따라서, 상기 캡절연막(23)과, 상기 제 1 절연측벽(26)하부의 제 1 게이트절연막(22)의 두께가 상기 산화공정에 의해 증가하게 된다.Therefore, the thickness of the cap insulating film 23 and the first gate insulating film 22 under the first insulating side wall 26 is increased by the oxidation process.
이때, 상기 제 1 절연측벽(26)은 실리콘질화막으로 이루어진다.At this time, the first insulating side wall 26 is made of a silicon nitride film.
이어, 도 1c에 도시한 바와같이 상기 제 1 절연측벽(26)을 제거한 후, 상기 게이트전극(24)을 포함한 기판(21)전면에 도전성물질을 증착한 후, 에치백하여 제 1 절연측벽(26)이 제거된 위치에 제 1 도전성측벽(27)을 형성한다.Subsequently, as shown in FIG. 1C, after the first insulating side wall 26 is removed, a conductive material is deposited on the entire surface of the substrate 21 including the gate electrode 24, and then etched back to form the first insulating side wall ( The first conductive side wall 27 is formed at the position where 26 is removed.
이때, 상기 제 1 절연측벽(26)은 인산을 이용한 습식(wet)처리를 함으로써 제거된다.At this time, the first insulating side wall 26 is removed by wet treatment using phosphoric acid.
이어, 상기 제 1 도전성측벽(27) 및 게이트전극(24)을 마스크로 이용한 불순물 이온주입을 통해 제 2 LDD영역(28)을 형성한다.Subsequently, the second LDD region 28 is formed by implanting impurity ions using the first conductive side wall 27 and the gate electrode 24 as a mask.
이때, 상기 제 2 LDD영역(28)을 형성하기 위해 주입되는 불순물의 농도는 상기 제 1 LDD영역(25)을 형성하기 위해 주입되는 불순물의 농도보다 더 크다.In this case, the concentration of the impurity implanted to form the second LDD region 28 is greater than the concentration of the impurity implanted to form the first LDD region 25.
이어서, 도 3d에 도시한 바와같이 상기 제 1 도전성측벽(27)을 포함한 반도체기판(21)전면에 절연층을 형성한 후 에치백하여 상기 제 1 도전성측벽(27)의 측면에 제 2 절연측벽(29)을 형성한다.Subsequently, as shown in FIG. 3D, an insulating layer is formed on the entire surface of the semiconductor substrate 21 including the first conductive side wall 27, and then etched back to form a second insulating side wall on the side of the first conductive side wall 27. (29) is formed.
이때, 상기 제 2 절연측벽(29)은 상기 제 1 절연측벽(26)과 마찬가지로 실리콘질화막으로 이루어진다.In this case, the second insulating side wall 29 is made of a silicon nitride film similarly to the first insulating side wall 26.
이와같이 제 2 절연측벽(29)을 형성한 후, 산화공정을 실시한다.Thus, after forming the 2nd insulating side wall 29, an oxidation process is performed.
따라서, 상기 제 2 절연측벽(29)하부의 게이트절연막은 상기 제 1 도전성측벽(27)하부의 게이트절연막보다 더 증가하게 되며, 상기 캡절연막(23)의 두께도 산화공정에 의해 더 증가하게 된다.Accordingly, the gate insulating film under the second insulating side wall 29 is increased more than the gate insulating film under the first conductive side wall 27, and the thickness of the cap insulating film 23 is further increased by the oxidation process. .
이어, 도 3e에 도시한 바와같이, 상기 제 2 절연측벽(29)을 인산을 이용한 습식(wet)처리를 통해 제거한 후, 전면에 도전성물질을 증착한다.Subsequently, as shown in FIG. 3E, the second insulating side wall 29 is removed by wet treatment using phosphoric acid, and then a conductive material is deposited on the entire surface.
그리고, 상기 도전성물질을 에치백하여 상기 제 1 도전성측벽(27)의 측면에 제 2 도전성측벽(30)을 형성한다.The conductive material is etched back to form a second conductive side wall 30 on the side of the first conductive side wall 27.
이어, 상기 제 2 도전성측벽(30) 및 게이트전극(24)을 마스크로 이용한 불순물 이온주입을 통해 제 3 LDD영역(31)을 형성한다.Subsequently, a third LDD region 31 is formed by implanting impurity ions using the second conductive side wall 30 and the gate electrode 24 as a mask.
이때, 상기 제 3 LDD영역(31)을 형성하기 위해 주입된 불순물의 농도는 상기 제 2 LDD영역(28)을 형성하기 위해 주입된 불순물의 농도보다 더 높다.In this case, the concentration of impurities implanted to form the third LDD region 31 is higher than the concentration of impurities implanted to form the second LDD region 28.
이어서, 도 3f에 도시한 바와같이, 상기 제 2 도전성측벽(30)을 포함한 기판(21)전면에 절연층을 형성한 후, 에치백하여 상기 제 2 도전성측벽(30)의 측면에 제 3 절연측벽(32)을 형성한다.Subsequently, as shown in FIG. 3F, an insulating layer is formed on the entire surface of the substrate 21 including the second conductive side wall 30, and then etched back to form a third insulating layer on the side surface of the second conductive side wall 30. The side wall 32 is formed.
그리고, 산화공정을 수행하면, 상기 제 3 절연측벽(32)하부의 게이트절연막은 상기 제 2 도전성측벽(30)하부의 게이트절연막보다 더 증가하고, 동시에 상기 캡절연막(23)의 두께도 증가하게 된다.When the oxidation process is performed, the gate insulating film under the third insulating side wall 32 increases more than the gate insulating film under the second conductive side wall 30, and at the same time, the thickness of the cap insulating film 23 also increases. do.
이어, 도 3g에 도시한 바와같이, 상기 제 3 절연측벽(31)을 상기 제 2 절연측벽(29)제거시와 동일한 공정으로 제거한 후, 제 2 도전성측벽(30)을 포함한 기판(21)전면에 도전성물질을 증착한다.3G, the front surface of the substrate 21 including the second conductive side wall 30 is removed after the third insulating side wall 31 is removed in the same process as when the second insulating side wall 29 is removed. Deposit conductive material on the substrate.
그리고, 상기 도전성물질을 에치백하여 상기 제 2 도전성측벽(30)의 측면에 제 3 도전성측벽(33)을 형성한다.The conductive material is etched back to form a third conductive side wall 33 on the side of the second conductive side wall 30.
이어, 상기 제 3 도전성측벽(33) 및 게이트전극(24)을 마스크로 이용한 불순물 이온주입으로 상기 제 3 도전성측벽(33)양측의 반도체기판(21)내에 소오스 및 드레인 불순물영역(34,34a)을 형성하면, 본 발명에 따른 반도체소자 제조공정이 완료된다.Subsequently, source and drain impurity regions 34 and 34a are formed in the semiconductor substrate 21 on both sides of the third conductive side wall 33 by impurity ion implantation using the third conductive side wall 33 and the gate electrode 24 as a mask. After forming, the semiconductor device manufacturing process according to the present invention is completed.
여기서, 상기 제 1, 제 2, 제 3 도전성물질은 폴리실리콘이며, 상기 제 2 LDD영역(28)의 접합깊이는 제 1 LDD영역(25)보다 더 깊고, 상기 제 3 LDD영역(31)은 제 2 LDD영역(28)보다 더 깊게 형성된다.Here, the first, second and third conductive materials are polysilicon, and the junction depth of the second LDD region 28 is deeper than that of the first LDD region 25, and the third LDD region 31 is It is formed deeper than the second LDD region 28.
그리고, 상기 제 1, 제 2, 제 3 도전성측벽(27,30,33)하부의 게이트절연막은 상기 게이트전극(24)하부보다 더 두껍게 형성된다.The gate insulating film under the first, second, and third conductive side walls 27, 30, and 33 is formed to be thicker than the bottom of the gate electrode 24.
이상 상술한 바와같이, 본 발명의 반도체소자 및 이의 제조방법은 다음과 같은 효과가 있다.As described above, the semiconductor device and its manufacturing method of the present invention have the following effects.
첫째, 게이트전극의 하부보다 게이트전극 양측의 게이트절연막의 두께를 더 두껍게 형성하고, 다중 LDD영역을 형성함으로써 핫 캐리어를 방지하는 효과가 있다.First, the thickness of the gate insulating film on both sides of the gate electrode is made thicker than the lower portion of the gate electrode, and the multiple LDD regions are formed to prevent hot carriers.
둘째, 도전성측벽들을 게이트전극으로 사용하기 때문에 결과적으로 게이트전극으로 사용되는 도전성측벽 하부까지도 다수의 LDD영역을 형성하는 것과 같은 효과를 갖게되어 전계의 감소에 따른 핫 캐리어를 방지할 수 있다.Second, since the conductive side walls are used as the gate electrodes, the bottom portion of the conductive side walls used as the gate electrodes can be formed as a result of forming a plurality of LDD regions, thereby preventing hot carriers due to the reduction of the electric field.
Claims (8)
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| KR100504432B1 (en) * | 1998-12-31 | 2005-09-26 | 주식회사 하이닉스반도체 | Gate electrode formation method of semiconductor device |
| KR100866112B1 (en) * | 2002-06-28 | 2008-10-30 | 매그나칩 반도체 유한회사 | Method for fabricating of semiconductor device |
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| KR100504432B1 (en) * | 1998-12-31 | 2005-09-26 | 주식회사 하이닉스반도체 | Gate electrode formation method of semiconductor device |
| KR100866112B1 (en) * | 2002-06-28 | 2008-10-30 | 매그나칩 반도체 유한회사 | Method for fabricating of semiconductor device |
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