KR19990049837A - Data processing method of digital video disc drive - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

The present invention relates to a data processing method of a digital video disc drive.

I. The technical problem that the invention is trying to solve

This prevents the data from being deleted as the ATP does not request the data transfer on time.

All. Summary of Solution of the Invention

Generating a data transfer command if there is a data transfer request within a certain period of time from the atta; otherwise, generating a standby command; otherwise, demodulating 16-8 data read from the digital video disc; Deinterleaving the demodulated data and storing the demodulated data in a memory; reading the demodulated data stored in the memory if there is no waiting command; and correcting the error data if there is no waiting command; Re-storing, reading and descrambling the data stored in the memory when the data transfer command occurs without the wait command, and outputting the data as an atta, until the data transfer command is generated each time the wait command occurs. And maintaining the memory state at that time. The.

la. Important uses of the invention

Used for digital video disc drives.

Description

Data processing method of digital video disc drive

The present invention relates to a digital video disc drive, and more particularly, to a data processing method of a digital video disc drive.

The digital video disc is one of digital moving picture disc media, and is a next-generation high-definition and high-definition multimedia storage device capable of recording a digital picture of MPEG-2 (Moving Picture Experts Group) -2 for two hours or more.

The configuration of a digital video disc drive that reads and reproduces various kinds of information recorded on the digital video disc as described above has been disclosed in Korean Patent Application No. 96-22968 filed with the Korean Intellectual Property Office.

Referring to Fig. 1, which shows a block diagram of a data processor 100 of a conventional digital video disc drive, the configuration and operation of a conventional data processor will be described in detail.

The reproduction data EFM and the system clock PLCK are input to the 32-bit shift register 102. The shift register 102 outputs the reproduced data EFM in parallel to 32 bits, and the parallel output is input to the synchronous detection unit 104. The synchronization detector 104 detects synchronization by searching whether the output of the shift register 102 matches a predetermined synchronization pattern, and outputs the synchronization detection signal according to the data error correction unit 112 and the memory controller 114. To provide. The output of the shift register 102 is input to the 16-8 demodulator 106 in units of 16 bits. The 16-8 demodulator 106 demodulates the 16-bit reproduction data EFM into 8-bit data and outputs the demodulated data. This is because the data recorded on the disk 100 has been modulated 8-16.

Here, data is recorded in the disk 100 in units of sectors. The data in sectors is a data ID, which is a data sector address, and data ID error correction data and main data for error correction of the data ID. It consists of (Main Data). The data ID is a series of information indicative of the position of each sector on the disc, and the main data is composed of data to be reproduced and parity for error correction. The sector unit data is 2366 [Bytes], and the main data includes parity data necessary for error correction in 10 [Bytes] in the horizontal direction and 16 [Bytes] in the vertical direction.

The demodulated data from the 16-8 demodulator 106 is input to the data ID detection and data ID error correction unit 110. The data ID detection and data ID error correction unit 110 detects the data ID from the demodulated data and performs error correction on the data ID as error correction bits for error correction on the data ID. The detected data ID is provided to the memory controller 114 so that the memory controller 114 can store the demodulated data in the memory 300 in sector order. Here, the demodulated data is stored in the memory 300 under the control of the memory controller 114. The deinterleaver 108 adjusts the address of the memory 300 to deinterleave the data to deinterleave the memory. To be stored at 300.

When 16 sectors of data are stored in the memory 300, the memory controller 114 provides the data to the data error correction unit 112. The data error correction unit 112 corrects the data of the 16 sectors in the horizontal and vertical directions, and the data of which the error correction is completed is stored in the memory 300 by the memory controller 114 again. Here, only the main data remains when the error correction is completed, so the data stored in the memory 300 is the main data.

In this state, if there is a data request by the ATP 400 which manages the smooth data transfer between the DVD-ROM drive and the host, the microcomputer 200 transmits the error-corrected main data through the interface 120. Control the memory controller 114 to Accordingly, the memory controller 212 reads the descrambled data and descrambles it through the descrambler 116, and then provides the descrambled data to the atapi 400 through the interface 120. Here, the error detector 216 detects whether there is an error in the data output to the atapi 400 and provides the result to a host connected to the atapi 400.

While the data processor 400 processes and outputs data, the data occupies a memory area for three processes. That is, data occupies a memory area during data demodulation, error correction, and output. Accordingly, in order for the data to be continuously output to the outside, the memory 300 should have three areas capable of storing data of at least 16 sectors. Referring to FIG. 2, which shows a memory map of the memory 300, the memory 300 includes first to third data storage areas, and the data storage area should be capable of storing at least 16 sectors of data.

A process of processing and outputting the reproduction data EFM input to the data processor 100 will be described with reference to FIG. 3 illustrating the memory usage flow. First, in step 1, the memory controller 114 sequentially stores first demodulated data including 16 sectors of data in a first data storage area of the memory 300. When the storage of the first demodulated data is completed, the memory controller 114 proceeds to step 2.

In the process 2, the memory controller 114 reads the first demodulated data of the 16 sectors into the memory 300 and provides the data error correction unit 112. The data error correcting unit 112 corrects the first demodulated data, and the memory control unit 114 returns the error corrected data (hereinafter, referred to as first error corrected data) to the first data of the memory 300. Save to storage area. At the same time, the memory controller 114 stores the second demodulated data of 16 sectors in the second data storage area of the memory 300. When the storage of the first error corrected data and the storage of the second demodulated data of 16 sectors are finished, the memory controller 114 proceeds to step 3.

In the process 3, the memory controller 114 outputs the first error-corrected data stored in the first data storage area through the descrambler 116 and the interface 120 according to a data transfer command provided by the microcomputer 200. To blood 400. At the same time, the memory control unit 114 reads the second demodulated data stored in the second data storage area and provides the data to the data error correction unit 112. The data error correction unit 112 receives the second demodulated data and corrects the error, and the memory controller 114 stores the error corrected data (hereinafter referred to as second error corrected data) again. Save to the area. At the same time, the memory controller 114 stores the third demodulated data of 16 sectors in the third data storage area of the memory 300 before proceeding to step 4.

In step 4, the memory controller 114 stores the fourth demodulated data of 16 sectors in the first data storage area in the first data storage area. At the same time, the memory controller 114 transmits the second error-corrected data stored in the second data storage area according to the data transfer command of the microcomputer 200 through the descrambler 116 and the interface 120. To provide. At the same time, the memory controller 114 reads out the third demodulated data stored in the third data storage area and provides the same to the data error correction unit 112. The data error correcting unit 112 corrects the third demodulated data, and the memory controller 114 stores the error corrected data (hereinafter referred to as third error corrected data) in the third memory of the memory 300. Save it back to the data storage area.

As described above, the memory controller 114 may perform steps 1, 2, 3,... According to a time-lapse of one region of the memory 300. Perform The branch point of the process may be a synchronization detection point.

As described above, the atapi 400 should make a request for data transmission to the microcomputer 200 in a predetermined time range. However, the atapi 400 may not request data transmission in a timely manner. Even in this case, the memory controller 114 overwrites new data in an area where data to be transmitted is stored according to a memory usage flow.

The reason why the atta 400 does not properly request data is when there is no need for the transmission of the data to be transmitted first, and secondly, as the atta 400 performs other tasks. It is the case that the data transfer request did not occur in time.

If the atapi 400 does not make a data request for the first reason, the data to be transmitted becomes unnecessary, and thus may be deleted as new data is overwritten in the area where the data is stored. However, when the atta 400 does not make a data request for the second reason, the corresponding data to be transmitted is required data, and thus, the atapi 400 requests a transmission for the data when a job that is being performed is finished. Will do. Nevertheless, the data was deleted as new data was overwritten in the area where the data was stored.

As described above, in the prior art, if the atapi did not make a data transfer request in a timely manner, the data to be transmitted at that time was deleted. As a result, the process of reading and transmitting the data to be transmitted from the disk again has to be repeated.

Therefore, an object of the present invention is to prevent the data from being deleted as ATP does not request data transfer in a timely manner so that the data of the digital video disc drive is not required to be read and processed again from the disc. To provide a treatment method.

1 is a block diagram of a conventional data processing apparatus;

2 illustrates a memory map of the memory of FIG. 1;

3 is a diagram illustrating a memory usage flow of the memory controller of FIG. 1;

4 is a block diagram of a data processing apparatus according to a preferred embodiment of the present invention;

5 is a flow chart of the processing of the microcomputer of FIG. 4;

6 is a flowchart illustrating a process of the memory controller of FIG. 4;

FIG. 7 is a diagram illustrating a memory usage flow of the memory controller of FIG. 4. FIG.

In order to achieve the above object, the present invention provides a step of generating a data transfer command if there is a data transfer request within a predetermined time period from the atta, otherwise generating a standby command, and performing data read from the digital video disc. Demodulating, deinterleaving the demodulated data and storing the demodulated data in a memory if there is no waiting command, reading and demodulating the demodulated data stored in the memory; And storing the corrected data in the memory again, reading and descrambling the data stored in the memory when the data transfer command is generated and outputting it as an atapi.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

Referring to FIG. 4, which shows a data processor 500 of a digital video disk drive according to a preferred embodiment of the present invention, the playback data EFM and system clock PLCK are input to a 32-bit shift register 502. As shown in FIG. The shift register 502 outputs the 32-bit parallel to the reproduction data EFM, and the parallel output is input to the synchronous detection unit 504. The synchronization detector 504 detects synchronization by searching whether the output of the shift register 502 matches a predetermined synchronization pattern, and outputs the synchronization detection signal according to the data error correction unit 512 and the memory controller 514. To provide. The output of the shift register 502 is input to the 16-8 demodulator 506 in units of 16 bits. The 16-8 demodulator 506 demodulates the 16-bit reproduction data EFM into 8-bit data and outputs the demodulated data. The demodulated data from the 16-8 demodulator 506 is input to the data ID detection and data ID error correction unit 510. The data ID detection and data ID error correction unit 210 detects a data ID from demodulated data and performs error correction on the data ID as error correction bits for error correction on the data ID. The detected data ID is provided to the memory controller 514 so that the memory controller 514 can store the demodulated data in the memory 700 in the sector order. Here, the demodulated data is stored in the memory 700 under the control of the memory controller 514. The deinterleaver 508 adjusts the address of the memory 700 to deinterleave the interleaved data so that the memory is deinterleaved. To be stored at 700.

When 16 sectors of data are stored in the memory 700, the memory controller 514 provides the data to the data error correction unit 512. The data error correction unit 512 corrects the data of the 16 sectors in the horizontal and vertical directions, and the data of which the error correction is completed is stored in the memory 700 by the memory controller 514 again. Here, only the main data remains when the error correction is completed, so the data stored in the memory 700 is the main data.

In this state, the microcomputer 600 searches for the data transfer request or the data transfer rejection of the atapi 800, whether the data transfer is completed, and provides various control signals to the memory controller 514. Referring to FIG. 5, which illustrates a flow chart of the microcomputer 600, in operation 900, the microcomputer 600 searches for a data transmission request from the atapi 800. At this time, if there is a data transmission request from the atapi 800, the process proceeds to step 902, and the process proceeds to step 900 again after applying the request for transmission request, otherwise proceeds to step 904. In step 904, the microcomputer 600 searches whether a predetermined time has elapsed. In this case, the predetermined time is a time at which a process in the memory usage flow is performed. The microcomputer 600 proceeds to step 906 after a predetermined time has elapsed. In operation 906, the microcomputer 600 searches for an address of data output from the memory 700 to determine whether transmission of error-corrected data is completed. At this time, if the data transfer is completed, the microcomputer 600 proceeds to step 914 and applies a subsequent data processing command to the memory controller 514 and then proceeds to step 900 again.

If the data transmission is not completed even after the predetermined time has elapsed, the microcomputer 600 searches whether the data transmission rejection command provided by the atapi 800 is applied. At this time, if the microcomputer 600 applies the data transfer rejection command, the microcomputer 600 proceeds to step 914, and applies the subsequent data processing command to the memory controller 514, and then proceeds to step 900 again.

If the atapi 800 does not grant the data transfer rejection command, the microcomputer 600 searches whether the pickup has jumped. Here, since the previous data becomes unnecessary at the time of the pickup jump, the data recorded in the memory 800 can be deleted. If the pickup jumps, the microcomputer 600 proceeds to step 914 and applies a subsequent data processing command to the memory controller 514 and then proceeds to step 900 again.

If the transmission is not completed after the predetermined time has elapsed, the ATP 800 does not provide a data transmission refusal command, and the pickup does not jump, the microcomputer 600 sends a message to the memory controller 514. The wait command is provided, and the process proceeds to step 506 again.

Referring to FIG. 6, which illustrates a flow chart of the memory controller 514 for a memory area according to the instructions provided by the microcomputer 600, the memory controller 514 may store the memory 800 in step 916. The demodulation data is stored in one area of). After the storage, the memory controller 514 proceeds to step 918 to read demodulated data stored in the area and apply the data to the data error correction unit 512. The data error correction unit 512 performs error correction on the demodulated data. The memory controller 514 stores the error corrected data in the memory 700 in operation 920. After the storage, the memory controller 514 proceeds to step 922 to determine whether the microcomputer 600 provides a data transfer command. In this case, if the microcomputer 600 provides a data transmission command, the microcomputer 600 proceeds to step 924 and provides the error corrected data to the atapi 800 through the descrambler 516 and the interface 520.

Then, the microcomputer 600 does not provide a data transfer command, or during the data transfer, the memory controller 514 proceeds to step 926 to search whether the microcomputer 600 provides the standby command. In this case, when the microcomputer 600 provides the standby command, the memory controller 514 proceeds to step 922 and waits until there is a data transmission request. If the microcomputer 600 does not provide a standby command, the memory controller 514 proceeds to step 928 to search whether the microcomputer 600 provides a subsequent data processing command. At this time, if the microcomputer 600 provides a subsequent data processing command, the process proceeds to step 916 and stores new demodulation data in the area. If the microcomputer 600 does not provide a subsequent data processing command, the microcomputer 600 proceeds to step 922 and waits for a data transmission request.

The memory usage flow chart shown in FIG. 6 is for a region of memory 700. The memory 700 is composed of three areas, and the above-described memory usage flowchart is applied to all three areas.

A process of processing and outputting the reproduced data EFM input to the data processor 500 will be described with reference to FIG. 7 illustrating a usage flow for the three regions of the memory. First, in step 1, the memory controller 514 sequentially stores the first demodulated data in the first data storage area of the memory 700. When the storage of the first demodulated data is completed, the memory controller 514 proceeds to step 2.

In step 2, the memory controller 514 reads the first demodulated data into the memory 700 and provides the data error correction unit 512. The data error correction unit 512 performs error correction on the first demodulated data, and the memory controller 514 stores the first error corrected data in the first data storage area of the memory 700. At the same time, the memory controller 514 stores the second demodulated data in the second data storage area of the memory 700. When the storing of the first error corrected data and the storing of the second demodulated data are completed, the memory controller 514 proceeds to step 3.

In the process 3, the memory controller 514 outputs the first error-corrected data stored in the first data storage area through the descrambler 516 and the interface 520 according to a data transfer command provided by the microcomputer 600. To blood 800. At the same time, the memory controller 514 reads the second demodulated data stored in the second data storage area and provides the data to the data error correction unit 512. The data error correction unit 512 receives the second demodulated data and corrects the error, and the memory controller 514 stores the second error corrected data in the second data storage area. At the same time, the memory controller 114 stores the third demodulated data of 16 sectors in the third data storage area of the memory 300 before proceeding to step 4.

In step 4, the memory controller 114 stores the fourth demodulated data of 16 sectors in the first data storage area in the first data storage area. At the same time, the memory controller 114 transmits the second error-corrected data stored in the second data storage area according to the data transfer command of the microcomputer 200 through the descrambler 116 and the interface 120. To provide. At the same time, the memory controller 114 reads out the third demodulated data stored in the third data storage area and provides the same to the data error correction unit 112. The data error correction unit 112 corrects the third demodulated data, and the memory controller 114 stores the third error corrected data in the third data storage area of the memory 300 again.

In the process 5, the microcomputer 600 normally commands the transmission of the third error-corrected data. However, the microcomputer 600 causes the memory controller 514 as the atapi 800 does not request data transmission. No data transfer command will be issued. In this case, the microcomputer 600 provides a standby command to the memory controller 514, and the memory controller 514 waits without performing any operation on the memory 700 according to the standby command. In the case where the microcomputer 600 provides the subsequent data processing command again during the waiting, the memory controller 514 proceeds to step 6.

In step 6, the memory controller 514 reads the fourth demodulated data stored in the first data storage area and provides it to the data error correction unit 512. The data error correction unit 512 error corrects the fourth demodulated data, and the memory controller 514 stores the fourth error corrected data in the first data storage area of the memory 700. At the same time, the memory controller 514 stores the fifth demodulated data in the second data storage area of the memory 700. The third error corrected data stored in the third data storage area is transmitted according to the data transmission command of the microcomputer 600.

As described above, when the atapi 400 does not request the data transfer to the microcomputer 200 or the data transfer is not completed, the microcomputer 200 issues a standby command to the memory controller 514. to provide. Accordingly, data can be simply stored in the memory according to the memory usage flow, and the read data can be prevented from being deleted.

As described above, the present invention has an advantage of preventing the data from being deleted as ATP does not request data transfer in a timely manner, so that the process of reading the data from the disk again and processing does not have to be repeated.

Claims (2)

In the data processing method of a digital video disk drive, Generating a data transfer command if there is a data transfer request within a certain period of time from the atta; otherwise, generating a standby command; 16-8 demodulating the data read from the digital video disc, Deinterleaving the demodulated data in a memory if there is no waiting command; If there is no waiting command, correcting error by reading demodulated data stored in a memory; Storing the error corrected data in a memory again if there is no waiting command; Reading and descrambling the data stored in the memory when the data transfer command is generated and outputting it as an atapi; And maintaining the memory state at that time until the data transfer command is generated each time the standby command is issued. The method of claim 1, wherein And generating a data transfer command even when the pickup jumps.