KR0183298B1 - Apparatus and method for controlling a memory - Google Patents

Abstract

1. Field of the Invention:

To an apparatus and a method for accessing a memory in a decoder of a DVD reproducing apparatus.

2. Technical Problems to be Solved by the Invention:

And at least one device for the decoder controls access to the shared memory.

3. The point of the inventive solution:

The control method of the memory control unit for accessing the memory shared by at least one of the devices having the address generating unit is set to the read / write mode by the read / write signal for access from the device, Outputting the first half of the address applied from the device to the RAS address and the second half of the address to the memory using the cache address; And outputting the data from the device to the memory specified by the lass address and the cache address when in the write mode.

4. Important Uses of the Invention:

The devices for decoding implement this to access the shared memory.

Description

And control method for accessing memory

FIG. 1 is a system block diagram of a conventional digital video disk player; FIG.

FIG. 2 shows a block diagram of a system decoder in FIG. 1; FIG.

FIG. 3 is a block diagram of a memory controller in FIG. 2 according to a preferred embodiment of the present invention; FIG.

FIG. 4 shows a control flow diagram of FIG. 3 according to a preferred embodiment of the present invention; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

200: system decoder 111: microcomputer interface controller

112: Micom register 114: Amplifier

115: EFM demodulation unit 116: error correction unit

117: descrambler 119: microcomputer memory access unit

120: A / V decoder interface and DVD-ROM interface

210: memory control unit 220: memory re-

230: Data bus 240: Priority control unit

280: memory 500: microcomputer

The present invention relates to a memory access, and more particularly to an apparatus and a method for enabling a system decoder of a digital video disc (hereinafter referred to as DVD) playback apparatus to read / write a memory for access will be.

2. Description of the Related Art [0002] Conventionally, DVD is one of digital moving picture disk media, and is a next-generation high-quality and high-quality multimedia storage medium for storing digital images of Moving Picture Experts Group (MPEG)

FIG. 1 is a diagram showing a schematic configuration of a typical DVD reproducing apparatus. Hereinafter, the present invention will be described in detail with reference to FIG.

When the disc 100 is reproduced, the disc motor 160 starts to rotate at a certain speed. In the optical pickup having the head 130, the disc 100 information is converted into an analog high frequency (RF) signal and output. This signal is shaped into a pulse waveform so that the data stream (ESM) is transferred to the following digital phase-locked loop (PLL) 300 and system decoder 200. The system decoder 200 receives the data stream ESM to perform demodulation, error correction, and descrambling. The memory 280 temporarily stores data generated in the process of the system decoder 200. At this time, the memory 280 is a dynamic RAM. The microcomputer 500 is a device control unit for collectively controlling the overall operation of the optical disc reproduction system. Upon receipt of a data transmission start signal from the audio / video decoder 600 or the room decoder 950 described later, a transmission control signal is generated. The digital phase-locked loop 300 includes a phase comparator circuit, a voltage-controlled oscillator, and a frequency divider, and generates a first clock synchronized with a signal reproduced from an optical disc. The disk drive control unit 400 controls the constant linear velocity of the disk rotation and other disk related operations in consideration of the frequency servo, the phase servo, etc. according to the frame synchronization signal Sf provided by the predetermined synchronization detection unit. The audio / video decoder 600 separates the data output from the system decoder 200 into audio data and video data, and reduces the original audio data and the video data. The audio and video data demodulated by the audio / video decoder 600 are transferred to an NTSC (or PAL) encoder 700 and a digital / analog converter 800, respectively, and output through a monitor 960 and a speaker 970, respectively. The room decoder 950 is mainly installed in a host (e.g., a personal computer), operates according to the instructions of the computer, and transfers the data output from the system decoder 200 to the host according to a predetermined interface scheme.

FIG. 2 is a block diagram of a system decoder in FIG. Hereinafter, the first embodiment will be described.

Memory 280 is dynamic RAM.

The microcomputer interface controller 111 performs interfacing between the microcomputer 500 and the system decoder 200. The microcomputer 500 is a device control unit for collectively controlling the overall operation of the digital video disk reproducing apparatus, and it also controls the overall operation of the system decoder 200 as a whole.

When the disc is reproduced, the disc motor starts rotating at a predetermined linear velocity. In the optical pickup having the head, the disc information is converted into an analog high frequency (RF) signal and output. This signal is shaped into a pulse waveform so that the ESM data of the data stream is amplified by the amplifier 114 and transmitted to the ESM demodulator 115.

The ESM demodulator 115 demodulates the ESM data on a symbol-by-symbol basis and outputs the ESM data. In other words, the ESM demodulator 115 receives the ESM data into a 32-bit shift register (not shown), selects the lower (or upper) 16 bits of the output 32 bits of the 32-bit shift register, (Not shown). The 16-8 demodulator converts the input 16-bit data into 8-bit symbols and outputs the 8-bit data. This is because Eight to Fourteen Modulation is used when writing data to disk.

The error correction unit 116 performs error correction in a horizontal direction and a vertical direction with respect to a predetermined block made up of data read from the disk.

At this time, the memory 280 collects ID data and main data output from the ESM demodulator 115 through the data bus 230 and the memory controller 210, and stores the ID data and the main data on a predetermined block basis. In other words, the memory controller 210 controlled by the microcomputer 500 allocates an appropriate address to the memory 280 and provides the corresponding demodulated data to form an error correction block. The error correction block is composed of data for 16 sectors. The memory 280 also buffers data between the error correction in the two directions and stores the corrected data.

The descrambler 117 receives only the portion corresponding to the main data among the corrected data stored in the memory 280, and compensates for the time delay due to the scrambling to recover the original data.

The microcomputer memory access unit 119 allows the microcomputer 500 to access the memory 280. [

A / V decoder interface and a DVD-ROM (Read Only Memory) interface 120 transmit the descrambled data to an A / V decoder (not shown) according to the type of the disc or a ROM decoder (Not shown).

The memory re-flash unit 220 is for preventing erasure of data in the memory 280.

The priority control unit 240 accesses the memory generated by the ESM demodulation unit 115, the error correction unit 116, the descrambler 117, the microcomputer memory access unit 119, the A / V decoder interface, the DVD-ROM interface 120, And outputs a permission signal to the devices in accordance with the priority. In addition, the priority control unit 240 outputs the permission signal and also outputs an access request signal ACCESS_REQuest (hereinafter referred to as ACC_REQ) to the memory control unit 210.

The memory controller 210 generates control signals for accessing the memory under the control of the microcomputer 500, and forms an access path to the devices and the data bus 230 requesting access.

That is, the data read from the disk is stored in the memory 280, and the data is read out in units of a predetermined block, and the read data is supplied to the error corrector 116. The data corrected by the error corrector 116 is stored again in the corresponding area of the memory 280, When scrambling and deinterleaving are performed, the restored data is stored again in the memory 280 or the already stored data is read out. Also, the memory controller 210 receiving the ACC_REQ reads the address of the corresponding memory 280 and accesses the read / write signal applied from the data bus 230.

The microcomputer 112 receives data from the microcomputer 500, stores signals for controlling the devices of the system decoder 200, and temporarily stores status information generated by the microcomputer 500 so that the microcomputer 500 can read the data.

The microcomputer interface 111 interfaces the microcomputer 500 to read and write the memory contents of the microcomputer 112 and the memory 280.

As described above, a plurality of devices share a memory 280 to perform a decoder. And allows the devices to which access is permitted by the priority control unit 240 to access the memory 280. [

At this time, the memory controller 210 needs to control access to the various devices and the memory 280.

It is therefore an object of the present invention to provide a memory control device for access to control access of a memory shared by at least one device for a decoder.

In order to achieve the objects of the present invention, there is provided a method of controlling a memory controller for accessing a memory shared by at least one apparatus having an address generator, the method comprising the steps of: Outputting the first half of the address applied from the device to the RAS address and the second half of the address to the memory in the read mode when the read / write mode is set; And outputting data from the memory specified by the CAS address to the devices from the memory; and, when in the write mode, transferring data from the device to the memory specified by the RAS address and the CAS address Output characteristic .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is to be noted that like elements in the drawings denote the same reference numerals whenever possible.

FIG. 3 is a block diagram of a memory controller in FIG. 2 according to a preferred embodiment of the present invention. Hereinafter, this will be described in detail with reference to FIG.

2, an ESM demodulator 115, an error corrector 116, a descrambler 117, a microcomputer memory access unit 119, an A / V decoder interface and a DVD-ROM interface 120, and a memory re-flash unit 220 are provided with an address generator . When requesting the access, a request signal is output to the priority control unit 240, and a bus passage with the data bus 230 is formed by a permission signal to be subsequently applied. Accordingly, the devices output a read / write signal and then output an address (ADdRess: hereinafter referred to as ADR) through the address generator.

The memory control signal generating unit 23 becomes a read mode and a write mode in accordance with a read / write (R / W) signal of the devices. Also, the memory control signal generator 23 outputs an ACCESS_ACTIVE (hereinafter referred to as ACC_ACT) signal to the priority controller 240 indicating that access is in progress when the ACC_REQ output from the priority controller 240 of FIG. 2 is inputted. And outputs a RAS (Row Address Strobe) signal and a CAS (Column Address Strobe) signal to the memory 280. The memory control signal generator 23 also outputs a memory read enable signal (MOE) or a memory write enable signal (MWE) according to the read mode and the write mode . The memory control signal generator 23 also outputs a ras operation signal RAS ENaBle (hereinafter referred to as RASENB) and a CAS operation signal CAS ENaBle (hereinafter referred to as CASENB).

The RAS address generator 21 is implemented as a unidirectional tri-state buffer and inputs the RASENB as a driving signal to output 17 bits from the lower bits of the ADR applied in the apparatus to the RAS address.

The CAS address generator 22 is also implemented as a unidirectional tri-state buffer, and inputs the CASENB as a driving signal to output 8 bits from the 0-bit, which is the upper bit of the ADR, to the CAS address. That is, the RAS address and the CAS address are output to the memory 280 as a memory address signal (MADR).

The data transfer unit 24 may be implemented as a bidirectional tri-state buffer. The DIRection (hereinafter referred to as DIR) for setting the direction of the data transfer unit 24 is the logic of the R / W signal by the S / N gate 25. Thus, the data transfer unit 24 sets the data output direction in the first direction and the second direction by the DIR signal. The data transfer unit 24 receives an operation signal ENaBle (hereinafter referred to as ENB) obtained by logarithmically multiplying the MOE signal and the NWE signal by an AND gate 26 as a drive signal and outputs data (hereinafter referred to as DATA ) To memory access data (hereinafter referred to as " MDATA "), or outputs the MDATA as DATA.

FIG. 4 is a view showing a control flowchart of FIG. 3 according to a preferred embodiment of the present invention. 4 will be described in detail with reference to FIG. 3.

A system clock (SCLK) is a main clock applied from the clock source of the system decoder 200. The memory control signal generator 23 is synchronized by the SCLK. Then, the memory control signal generator 23 enters the read mode in the period M1 in which the R / W signal is at the high level, and enters the write mode in the period M2 in which the R / W signal is in the low level. When the ACC_REQ is high level during the M1 period, the 18-bit ADR and the 16-bit DATA are input to the memory controller 210 from the device requesting access at the high level through the data bus 230, respectively.

The memory control signal generator 23 of the memory controller 210 outputs the high-level ACC_ACT activated based on the ACC_REQ to the priority controller 240. [ The memory control signal generator 23 also outputs the activated low level RAS to the memory 280 and then outputs the activated low level CAS. In addition, the activated RASENB together with the RAS signal is output, and the activated CASENB is output together with the CAS signal. The memory control signal generator 23 outputs the MOE of the activated low level.

The ras address generation unit 21 outputs the lower bits of ADR to the RAS address RADR as MADR based on the activated RASENB. The CAS address generating unit 22 outputs the CAS address (CADR) to the MADR according to the activated CASENB. At this time, since the activated RASENB is generated earlier than the CASENB, the RAS address generator 21 and the CAS address generator 22 can divide the applied ADR into lower bits and output them.

Since the DIR is a low-level bevel in the first direction, the data transfer unit 24 forms a bus path from the memory 280 to the devices. The ENB signal becomes a low level activated based on the MOE signal, and the read data rdat in the corresponding area of the memory 280 is output to the device that requested access by the data transfer unit 24 by the RAS address and the CAS address. This means that the data rdat is transmitted during the activated low level period dl of the MOE.

The data in the memory 280 is read by the memory controller 210 whose ACC_REQ is in the read mode in the high level period T1.

Meanwhile, the memory control signal generating unit 23 enters the write mode during the period M2 where the R / W signal is at the low level. When the ACC_REQ is at the high level, the 18-bit ADR and the 16-bit DATA, which are the addresses to be written through the data bus 230 from the device requesting access at the high level, are input to the memory controller 210. The memory control signal generator 23 of the memory controller 210 outputs the high-level ACC_ACT activated based on the ACC_REQ to the priority controller 240. [ The memory control signal generator 23 also outputs the activated low level RAS to the memory 280 and then outputs the activated low level CAS. In addition, the activated RASENB together with the RAS signal is output, and the activated CASENB is output together with the CAS signal. In the write mode, the memory control signal generator 23 outputs the activated low level MWE.

The ras address generating unit 21 outputs the lower bits of the ADR as the RAS address RADR to the MADR based on the activated RASENB. The CAS address generating unit 22 outputs the CAS address (CADR) to the MADR according to the activated CASENB.

Since DIR is a high level in the second direction, the data transfer unit 24 forms a bus path from the device to the memory 280. [ The ENB signal becomes a low level activated based on the MWE signal, and the data DATA applied from the device is output to the MDATA, so that the write data wdat is written to the corresponding area of the memory 280 by the RAS address and the CAS address. This means that the data wdat is transmitted during the active low level period d2 of the MWE.

The data from the device is written to the memory 280 by the memory control unit 210 whose ACC_REQ is set to the write mode in the high level period T2.

As described above, in the present invention, the system controller 200 of the DVD player implements the memory controller 210 to access the memory 280 shared by the devices for decoding. Thus, the memory control unit 210 has an advantage that various devices can access the memory by a signal requesting access.

Claims (6)

A control device for reading / writing data from / to a memory, comprising: an address generator; and at least one device for accessing a memory, the device comprising: A memory control signal generator for outputting a signal and a memory read / write operation signal, and a memory control signal generator for outputting the first half of the address in the first half of the address in the address generator based on the ras signal and the cask signal, A memory address generating unit for generating a read / write signal and outputting the memory read / write signal to the memory; Access data in a corresponding area of the memory according to an address in the first direction and the second direction La transmission memory controller for access, characterized in that the adapted parts of the data transfer. 2. The memory control device according to claim 1, wherein the first address and the second address are set to be opposite to the cache address and the lass address. 2. The method of claim 1, wherein the first direction is a direction from the memory to the device by the read signal and the second direction is a direction from the device to the memory by the write signal. Gt; At least one apparatus for a decoder for outputting a request signal in a system decoder of a reproducing apparatus using a digital video disc as a recording medium and outputting data and an address in response to a permission signal; A control device for accessing a memory shared by the devices in a priority control section for outputting a signal and an access request signal, the control device comprising: a memory for storing a Las signal and a Kas signal activated based on the access request signal, A memory control signal generator for outputting a las operation signal and a kas operation signal, and a control unit for outputting a first half of an address applied from the devices based on the las operation signal and the kas operation signal, To the memory using a cache address And a memory controller for transmitting data applied from the memory to a memory of the corresponding area in a read mode according to the ras and cas addresses on the basis of the memory read / write operation signal, And a data transfer unit for transferring data applied from the device to a memory of the memory controller. A method of controlling a memory control unit for accessing a memory shared by at least one device having an address generator, the method comprising: a read / write mode for accessing from the device; The method comprising the steps of: outputting a first half of an address applied from the device to a RAS address and a second half of the address to a CAS address when the RAS mode is selected; And outputting data from the device to the memory specified by the lass address and the cache address when the device is in the write mode, A memory control method for access. At least one apparatus for a decoder for outputting a request signal and outputting data and an address by a permission signal in a system decoder of a playback apparatus using a digital video disc as a recording medium; A control method of a memory control unit for accessing a memory shared by the devices in a priority control unit for outputting a permission signal and an access request signal, the control method comprising: a read / write mode for accessing from the device; A step of outputting, to the memory, a first half of an address applied from the device after the access request signal is input, and a second half of the address as a cache address in the read / write mode; The las address and the cache address specified by the cache address And outputting data from the device to the memory specified by the lass address and the cache address when the device is in the write mode. The memory control method comprising: