KR100194044B1 - Interface device and method for memory access - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

A device and method for accessing a memory by a microcomputer.

2. The technical problem to be solved by the invention

When the microcomputer accesses the memory, the memory address is automatically increased by the counter to access the data at the corresponding address, and the read / write data is temporarily stored in the data register so that the memory control unit and the microcomputer interface control unit control the data. An interface device and method for memory access to access registers are provided.

3. Summary of Solution to Invention

A register designation section having a register address counter, a memory address register storing a memory address to be addressed at a location specified by address counter values of the register designation section, and a value of the memory address register by a counter operation signal of a read / write signal; In the interface device having a memory address counter for automatically incrementing the memory address and outputting the memory address to the memory, the interface method for accessing the memory by the microcomputer outputs the write signal when the light mode is entered. Writes a register address to the register designation section, writes the memory address to a designated area of the memory address register, writes a second register address to the register designation section, and usually a second register Writing the write data to the data register designated by the dress to write the write data to the memory area designated by the memory address counter, and outputting the read signal when the read mode is entered. Write an address to the register designation unit, write the memory address to the designated area of the memory address register, write the second register address to the register designation unit, and write to the data register designated by the second register. A process of reading read data from the stored memory is performed.

4. Important uses of the invention

This is implemented for an apparatus and method for directly accessing a memory attached to a DVD decoder from a microcomputer.

Description

Interface device and method for memory access

1 is a block diagram showing a digital video disc reproducing apparatus for carrying out the present invention.

2 is a block diagram of a system decoder in FIG. 1;

3 is a block diagram of an interface device for accessing a memory by a microcomputer in FIG. 2 according to a preferred embodiment of the present invention.

4 is a flowchart illustrating a control flow of a microcomputer interface controller for writing a memory by a microcomputer according to an exemplary embodiment of the present invention.

5 shows a timing diagram of FIG.

6 is a diagram illustrating a control flow diagram of a microcomputer interface controller for the microcomputer to read a memory according to an exemplary embodiment of the present invention.

FIG. 7 shows a timing diagram of FIG. 6. FIG.

* Explanation of symbols for main parts of the drawings

200: system decoder 111: microcomputer interface control unit

112: microcomputer resistor 114: amplifier

115: EFM demodulator 116: error correction unit

117 descrambler 119 microcomputer memory address generator

120: A / V decoder interface and DVD-ROM interface

210: memory controller 220: memory refresh unit

230: data bus 240: priority control unit

280: Memory 500: Microcomputer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video disc (DV) playback device (hereinafter referred to as DVD), and more particularly, to an apparatus and method for directly accessing a memory of a system decoder in a DVD.

Digital video disc is one of the digital moving picture disc media, and is a next-generation high-definition and high-definition multimedia storage medium that stores digital video of MPEG (Moving Picture Experts Group) 2 for two hours or more.

A memory attached to an apparatus for decoding data from the disc is used to store signal processing data for performing the decoder. In addition, the microcomputer needs a storage area to record information necessary for overall control of the system decoder, and to read the information to control the system when necessary. Accordingly, in the present invention, the storage area of the microcomputer is provided in the memory so that the memory can be freely accessed.

Accordingly, an object of the present invention is to provide an interface device and method for automatically accessing corresponding address data of the memory when the memory address is automatically increased by the memory address counter when the microcomputer designates the memory address in accessing the memory.

Another object of the present invention is to provide an interface apparatus and method for memory access for temporarily storing read / write data in a data register when a microcomputer accesses a memory and allowing a memory controller and a microcomputer interface controller to access the data register. .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that like elements in the figures represent like reference numerals wherever possible.

1 is a diagram showing a schematic configuration of a DVD player for carrying out the present invention. Hereinafter will be described in detail with reference to FIG.

When the disc 100 is played back, the disc motor 160 starts to rotate at a certain speed. In the optical pickup provided with the head 130, the disc 100 information is converted into an analog RF signal and output. This signal is shaped into a pulse waveform and the data stream (ESM) is passed to a digital phase locked loop (PLL) 300 and a system decoder 200. The system decoder 200 inputs the data stream (ESM) to perform demodulation, error correction and descrambling. The memory 280 temporarily stores data generated in the process of the system decoder 200. In this case, the memory 280 is a dynamic RAM. The microcomputer 500 is a device controller which controls the overall operation of the present optical disc reproducing system. When the data transmission start signal is received from the audio / video decoder 600 or the ROM decoder 950 described later, a transmission control signal is generated. The digital phase locked loop 300 is a phase comparator, which is composed of a voltage controlled oscillator and a divider to generate a first clock synchronized with a signal reproduced from an arbitrary optical disc. The disk drive controller 400 controls the constant linear velocity of the disk rotation and other disk related operations in consideration of the frequency servo, the phase servo, etc. according to the frame synchronization signal Sf provided from the predetermined synchronization detector. The audio / video decoder 600 classifies the data output from the system decoder 200 into audio data and video data and reduces the original audio source data and the video source data. The audio and video data demodulated by the audio / video decoder 600 are transmitted to the NTSC (or PAL) encoder 700 and the digital / analog converter 800, respectively, and output through the monitor 960 and the speaker 970, respectively. The ROM decoder 950 is mainly embedded in a host (eg, a personal computer), operates according to a command of the computer, and transmits data output from the system decoder 200 to the host according to a predetermined interface method.

FIG. 2 is a block diagram of a decoder of the DVD player in FIG.

Memory 280 is dynamic.

The microcomputer interface controller 111 is responsible for interfacing the microcomputer 5000 and the system decoder 200. The microcomputer 500 is a device controller which controls the overall operation of the digital video disk player. The system decoder 200 also controls the overall operation.

When the disc is played back, the disc motor starts to rotate at a predetermined linear speed. In the optical pickup provided with the head, the disc information is converted into an analog high frequency (RF) signal and output. The ESM data of the data stream shaped into a pulse waveform is amplified by the amplifier 114 and passed to the ESM demodulator 115.

The ESM demodulator 115 demodulates and outputs the ESM data in symbol units consisting of predetermined bits. In other words, the ESM demodulator 115 inputs the ESM data into a 32-bit shift register (not shown), and selects the lower (or higher) 16 bits among the 32 bits of the 32-bit shift register to output 16-8 decodes. Deliver to grandfather (not shown). The 16-8 demodulator converts the input 16-bit data into 8 bits constituting one symbol and outputs the converted 8-bit data. This is due to the 8-14 modulation (Eight to Fourteen Modulation) when data was written to disk.

The error correction unit 116 corrects errors in a horizontal direction and a vertical direction with respect to a predetermined block made up of data read from the disk.

In this case, the memory 280 collects ID data and main data output from the ESM demodulator 115 through the data bus 230 and the memory controller 210 and stores them in predetermined block units. In other words, the memory controller 210 under the control of the microcomputer 500 allocates an appropriate address to the memory 280 and provides the corresponding demodulated data to form an error correction block. The error correction block consists of data for 16 sectors. The memory 280 also buffers data between the two directions of error correction and stores corrected data.

The descrambler 117 receives only the portion of the corrected data stored in the memory 280 corresponding to the main data and restores the original data by compensating for the time delay caused by scrambling.

The microcomputer memory address generator 119 allows the microcomputer 500 to access the memory 280.

The A / V (Audio / Video) Decoder Interface and the DVD-ROM (Digital Video (or Verstile) Disc-Read Only Memory) Interface 120 allow the A / V decoder (not shown) to read descrambled data according to the type of the disc. Interface to transmit to or to a ROM decoder (not shown).

The memory refresh unit 220 is for preventing data erasing of the memory 280.

The priority control unit 240 responds to request signals applied from the ESM demodulator 115, the error correcting unit 116, the descrambler 117, the microcomputer memory address generator 119, the A / V decoder interface and the DVD-ROM interface unit 120, and the memory refresh 220. The priority is set accordingly to provide an order in which the memory 280 can be accessed.

The memory controller 210 operates under the control of the microcomputer 500 and operates such as generation of a low address signal, a column address signal, other addresses, and prevention of overflow and underflow. In other words, the data read from the disk is demodulated and stored in the memory 280, read in a predetermined block unit, and provided to the error correction unit 116, and the data corrected by the error correction unit 116 is stored in the corresponding region of the memory 280 When descrambling and deinterleaving, the restored data is stored in the memory 280 again or the data already stored is read.

The microcomputer register 112 receives data from the microcomputer 500 and stores signals for controlling the devices of the system decoder 200, and temporarily stores the state information generated from the devices so that the microcomputer 500 can read the microcomputer 500.

The microcomputer interface 111 performs an interface for the microcomputer 500 to read and write the memory contents of the microcomputer register 112 and the memory 280.

Accordingly, the present invention relates to the interface device 300 for performing a read / write of the memory 280 attached to the system decoder 200 in the DVD playback apparatus. The interface device 300 includes a microcomputer interface controller 111, a microcomputer register 112, a microcomputer memory address generator 119, and a memory controller 210.

Hereinafter, a detailed block diagram of the interface device 300 is shown in FIG. 3. 3 is a block diagram illustrating an interface device for accessing a memory by a microcomputer in FIG. 2 according to a preferred embodiment of the present invention. A description with reference to FIG. 3 is as follows. In the present invention, a case where the microcomputer 500 accesses the memory 280 when the address of the memory 280 is 3 bytes will be described as an example.

The microcomputer interface control unit 111 is connected to the microcomputer 500 via a microcomputer data bus (hereinafter referred to as MDATA BUS), the microcomputer read signal (hereinafter referred to as MOE (Micom Output Enable)) for the microcomputer 500 to read the register, and the microcomputer 500 to register the register. Microcomputer write signal (hereinafter referred to as MWE (Micom Write Enable)) for writing, whether the microcomputer 500 will connect the data bus to the register designation section 20 below, or the memory address register (hereinafter referred to as MA (Memory Address) register) 25 and data register (Hereinafter referred to as D (Data) register) A microcomputer register access signal (hereinafter referred to as MRZA (Micom Resister Zero Access)), a signal for selecting whether to connect to 26, a selection signal for the microcomputer 500 to access a register or a memory 280 ( ZCS (Zero Chip Select) is input from the microcomputer 500. The microcomputer interface controller 111 inputs a standby signal (hereinafter referred to as WAIT) from the memory controller 210 to prevent access when the memory is accessed, and outputs it to the microcomputer 500. Here a zero signal indicates that the low level is active. The microcomputer interface controller 111 inputs the MOE to output a signal (hereinafter referred to as OE (Output Enable)) to the memory controller 210 and the microcomputer memory address generator 119 indicating the read mode. The microcomputer interface controller 111 may input the MWE to output a signal (hereinafter, referred to as WE (write enable)) to the memory controller 210, the register designator 20, and the microcomputer memory address generator 119 to indicate that the write mode is in the write mode.

The register designation unit 20 inputs and accesses a register address operation signal (hereinafter referred to as RA enb (Resister Address Enable)) according to a register write operation signal (hereinafter referred to as RWE (Resistor Write Enable)) from the microcomputer interface control unit 111. Register address for storing temporary registers of the first and second registers of the register (hereinafter referred to as RA (Rasister Address)) register 23, and the contents of the RA register 23 as an initial value. Decode the register address counter 21, the output value of the register address counter 21 to the MA register 25 operation signals (hereinafter referred to as MA_enb (Memory Address_enable)) and the operation signal of the D register 26 (hereinafter referred to as D_enb (Data_enable)) The decoder 22 outputs. At this time, the register address counter 21 counts WE and OE starting from the value of the RA register 23 to generate respective register operation signals so that the microcomputer 500 can access the register.

The MA register 25 is divided into three regions, and stores the memory address applied from the data bus 24 connected to the microcomputer interface controller 111 in the first region MA0 due to the MA_enb0, and the data in the second region MA1 due to the MA_enb1. The memory address applied on the bus 24 is stored, and the memory address applied on the data bus 24 is stored in the third region MA2 due to the MA_enb2.

The D register 26 is a register designated by D_enb from the register designation unit 20, and temporarily stores write data applied on the data bus 24 and read data applied on the data bus 30.

The register designation unit 20, MA register 25, and D register 26 are the microcomputer register 112.

The access controller 28 and the memory address counter 27 are the microcomputer memory address generator 119. The access controller 28 inputs OE and WE to output an access request signal to the priority controller 240 when the read mode or the write mode is entered. Thus, when the access permission signal from the priority control unit 240 is input, the access control unit 28 outputs a passage formation signal (hereinafter referred to as enb (enable)).

The memory address counter 27 reads the memory address written in the MA register 25 by inputting the OE and WE, performs a counter based on the OE and WE using the memory address as a start address, and based on the enb. A passage with the address bus 29 is formed and outputs addresses to be accessed to the address bus 29.

The memory controller 210 connected to the memory 280 inputs an address of an area in which read data is stored by the address bus 29 when a read mode is entered by the OE. The address output from the memory address counter 27 is output to the memory 280 through OE, RAS, CAS, and address bus 32 to access read data and input read data through the data bus 33. The memory controller 210 outputs the data to the D register 26 through the data bus 30. In addition, when the memory controller 210 enters the write mode by the WE, the memory controller 210 inputs an address of an area to store write data from the address bus 29 and outputs the address to the address bus 32. The memory controller 210 generates WE, RAS, and CAS to access a memory area to be written, and inputs write data of the D register 26 through the data bus 30 and stores the data in the memory 280. The memory controller 210 outputs read data to the D register 26 or outputs WAIT to the microcomputer interface controller 111 when memory data is received from the D register 26. Thus, the microcomputer interface controller 111 outputs the WAIT to the microcomputer 500. Accordingly, the WAIT prevents the microcomputer 500 from accessing the D register 26.

In other words, when the MA0 register address is 70, MA1 is 71, and MA2 is 72, the MA register address, which is the first register of 70, is given to the RA register 23. 21 outputs 70, 71, and 72 to decoder 22 by counting REW starting with address 70. Decoder 22 then decodes the 70 and outputs MA_enb0. The first memory address applied from the microcomputer interface controller 111 is stored in an area of MA0. In addition, a second memory address applied from the microcomputer interface controller 111 is stored in an area MA1 corresponding to MA_enb1 of 71. A third memory address applied from the microcomputer interface controller 111 is stored in the region MA2 corresponding to the MA_enb2 of 72. The first, second, and third memory addresses stored in the MA register 25 are then output to the memory address counter 27. Thus, the memory address becomes the actual address of the memory 280. In this case, the combined first, second and third memory addresses are the starting point of the memory address counter 27, and the memory addresses that are counted and countered by the WE and OE are output to the memory controller 210.

If D register 26 with the second register address 80 is set, decoder 80 decodes 80 and outputs D_enb when 80 is applied to RA register 23. However, when the address address of the D register 26 is set to 73, the fourth counter value of the first register, MA0 register address 70, is 73, and therefore, the microcomputer interface controller 111 outputs D_enb, which is the value obtained by decoding 73, It is not necessary to output 2 register addresses. That is, an address address of the MA register 25 and an address address of the D register may be simultaneously designated by designating the first register address.

Accordingly, the D register 26 temporarily stores read data from the memory controller 210 through the data bus 30 and temporarily stores write data from the microcomputer interface controller 111 through the data bus 24. That is, the read / write data of the memory 280 is accessed through the D register 26.

FIG. 4 is a diagram illustrating a control flowchart of a microcomputer interface controller for writing a memory by a microcomputer according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating the timing diagram of FIG. 4 and 5 will be described in detail with reference to the configuration of FIG. 3.

When the ZCS applied from the microcomputer 500 becomes 0 in step 422, the microcomputer interface controller 111 confirms that MRZA becomes 0 in step 424. In FIG. 5, when the ZCS and the MRZA are 0, the microcomputer interface controller 111 generates RA enb, so that the M register from the microcomputer 500 is the first register in the RA register 23 in step 526 in the low level period. Light it. That is, 70 denotes data applied by the microcomputer 500 as wadr of FIG. 4 (hereinafter referred to as MDAT (Micom Data)). When the MRZA becomes a high level in step 428, the microcomputer interface controller 111 writes the memory address madr in the MA register 25 in step 430. In FIG. 5, when the MWE is applied with the low level while the MRZA is in the high level period, the microcomputer interface controller 111 stores the first, second, and third memory addresses madr0, madr1, and madr2 of the MDAT at addresses 70 and 71 of the MA register 25. Light at 72.

In step 432, when the MRZA becomes 0, the microcomputer interface controller 111 writes the second register address 80 to the RA register 23 in step 434. In FIG. 5, the second wadr of 80 from the microcomputer 500 is written to the RA register 23 in the low level period of MRZA. In this case, steps 432 and 334 may be deleted when the address of the D register is set to 73. This is because it can be set by counting at the register address counter 21.

When it is confirmed in step 436 that the MRZA becomes 1, the microcomputer interface controller 111 writes the write data wdat0 applied from the microcomputer 500 of FIG. 5 to the D register 26 at the rising edge of MWE. At this time, the microcomputer interface controller 111 outputs the WE to the memory controller 210, the microcomputer memory address generator 119, and the register designator 20. Thus, the memory controller 210 writes the write data wdat0 temporarily stored in the D register 26 to the memory 280 of the address applied from the memory address counter 27. In this case, the memory controller 210 outputs a low level WAIT while data is written to the memory 280. Accordingly, when WAIT is 0 in step 440, the microcomputer interface controller 111 does not write. When the write operation of the memory controller 210 ends, the microcomputer interface controller 111 writes the write data wdat1 to the D register 26 by the high level WAIT. That is, in steps 438, 440, and 442, the microcomputer interface controller 111 writes the write data to the D register 26 at the rising edge of the MWE, and immediately after the data is written to the D register 26, a REQ is generated to write the data of the D register 26. The operation to write to the memory 280 is started. At this time, the WAIT becomes low level and informs the microcomputer 500 that data is being written to the memory 280. When the data write operation of the D register 26 is completed in the memory 280, the WAIT becomes high level. Note that the next data is written to D register 26 based on the high level WAIT.

Thus, in step 442, the microcomputer interface controller 111 recognizes that the write operation is completed when the MWE from the microcomputer 500 reaches the high level where the MWE is not activated. In step 444, the write operation is terminated when the ZCS becomes 1.

FIG. 6 is a flowchart illustrating a control flow of a microcomputer interface controller for reading a memory by a microcomputer according to an exemplary embodiment of the present invention. 7 is a diagram showing the timing diagram of FIG. Hereinafter, FIGS. 6 and 7 will be described with reference to the configuration of FIG. 3.

When the ZCS applied from the microcomputer 500 in step 622 becomes 0, the microcomputer interface controller 111 confirms that the MRZA becomes 0 in step 624. In FIG. 7, when the ZCS and MRZA are 0, the microcomputer interface controller 111 writes the address, for example, 70, of the MA register, which is the first register, to the RA register 23 in step 626 when the MWE is a rising edge from the microcomputer 500. That is, 70 is radr of FIG. 6 and is MDAT in the microcomputer 500. When the MRZA becomes the high level in step 628, the microcomputer interface controller 111 writes the memory address madr in the MA register 25 at the rising edge of the MWE in step 630. That is, the memory address madr0 is written to address 70, the memory address madr1 is written to address 71, and the memory address madr2 is written to address 72 at each rising edge of the MWE.

In step 632, when the MRZA becomes 0, the microcomputer interface controller 111 writes the address, for example, 80, of the second register, D register 26, to the RA register 23 in step 634. In FIG. 7, the second radr of 80, from which the MRZA is applied from the microcomputer 500 in the low level period, is written to the RA register 23. In FIG. In this case, in steps 632 and 634, when the address of the D register is set to 73, the address of the D register 26 may not be set again. This is because it can be set by counting at the register address counter 21.

The memory controller 210 reads data from the memory 280 and writes the data from the memory 280 to the D register 26 through the data bus 30 by using the address generated by the memory address counter 27 by the memory address. In this case, the memory controller 210 reads data from the memory 280 and generates WAIT while writing the read data to the D register 26 so that the microcomputer 500 does not access the D register 26 at this time.

When it is confirmed in step 636 that MRZA is 1, the microcomputer interface controller 111 outputs the applied WAIT to the microcomputer 500. Thus, in FIG. 7, the microcomputer 500 generates a low level MOE when the WAIT is withdrawn. When the WACOM becomes 1 in step 638 and the MOE becomes 0, the microcomputer interface controller 111 reads the read data radt of the D register 26 and outputs the read data radt to the microcomputer 500 in step 640.

When the MOE becomes 1 again, the memory address counter 27 outputs the value countered by the OE, and the memory controller 210 writes the read data accordingly to the D register 26. That is, when the MOE of FIG. 7 rises, the memory address counter 27 counters one by one and outputs the incremented address to the memory controller 210, and the memory controller 210 reads the data rdat0 of the memory 280 corresponding to the address applied to each occurrence of the OE. Write, 1, 2, 3 to D register 26. The microcomputer interface control unit 111 reads the read data rdat0, 1, 2, and 3 to the microcomputer 500 whenever the MOE becomes low by the steps 638, 640, and 642.

As described above, the microcomputer 500 does not need to reset the address of the microcomputer register 112 in order to access the read / write data to the memory 280. In the present invention, the microcomputer 500 counters the register designator 20 to automatically designate the next register. The memory address counter 27 automatically increments the addresses one by one by the OE, so the microcomputer 500 can continuously access read or write data by the MOE or MRE. The D register 26 allows the microcomputer 500 to directly access the read / write data of the memory 280.

Claims (7)

A memory controller for generating control signals necessary for access of a memory and accessing the memory according to a read / write signal, the interface device for reading / writing the memory, comprising: a first and a second register address and a memory address; A microcomputer interface controller which outputs write data and the read / write signal, inputs read data, and decodes the address counter values by predetermined counters of the first register address, and decodes the second register address to decode the data register. A register designation unit for outputting to an address, a memory address register for writing the memory address at an address specified by the address counter values, and a read / write signal as a counter operation signal for inputting the memory address register; A memory address counter for outputting the memory address predetermined by the counter operation signal to the memory controller, starting from a value, and designated by the data register address, and temporarily storing the read data from the memory controller; And a data register configured to output to an interface controller and temporarily store the write data from the microcomputer interface controller and output the write data to the memory controller. The register designator of claim 1, wherein the register designation unit comprises: an area for storing the first and second register addresses, a register address counter for predetermined counters starting from the first register address, an output of the register address counter, and the first register address; And a decoding unit for decoding the register address and outputting the register address to the memory address register or the data register. The interface device according to claim 1 or 2, wherein the data register is designated as an address of a next address of the memory address register and is automatically designated by the address counter values. A decoder device of a playback apparatus using a digital video disk as a recording medium, comprising: a memory for storing data generated during decoder execution, a microcomputer for controlling the decoder device as a whole, and reading / writing information necessary for the memory; Predetermined register address data by the microcomputer interface control unit for generating a control signal for accessing the memory under the control of the microcomputer, the memory control unit for generating the control signals for accessing the memory to access the memory, and the microcomputer interface control unit. A register designation unit for counting and outputting address counter values by decoding; and a memory address register for recording an address of the memory to be accessed from the microcomputer interface control unit at an address designated by the address counter values. And a priority control unit for outputting a permission signal for allowing memory access in accordance with a predetermined priority with respect to the access request signal of the memory, and the access request signal based on the read / write signal of the microcomputer interface controller. An access control unit for outputting a path forming signal by inputting the access permission signal applied to the priority control unit, and outputting a path forming signal, and inputting the read / write signal as a counter operation signal to obtain a value of the memory address register; And a memory address counter for outputting the memory address predetermined by the counter operation signal to the memory control section, wherein an address bus passage with the memory control section is formed by the passage formation signal, and by the register designation section. Designated memo And a data register for inputting read data from a memory device and outputting the read data to the microcomputer interface controller, and temporarily storing the write data of the microcomputer interface controller and outputting the write data to the memory controller. A decoder device of a playback apparatus using a digital video disk as a recording medium, comprising: a memory for storing data generated during decoder execution, a microcomputer for controlling the decoder device as a whole, and reading / writing information necessary for the memory; A disk rotation controller for rotating the digital disk under the control of the micom, a demodulator connected to a data / address bus, and a demodulation device for demodulating data input from the digital disk under the control of the microcomputer, the data / address bus; An error correction unit connected to and correcting an error of demodulated data of the demodulator under control of the micom, and a descrambler connected to the data / address bus and descrambled the error corrected data under control of the micom; And is connected to the data / address bus, An interface unit performing an interface function to transmit the descrambled data to an audio / video decoder unit and a host based on a disc control signal according to the type of the digital disc output from the micom under the control of a microcomputer; A memory refresh to prevent memory data from being erased; a microcomputer interface controller configured to generate a control signal for accessing the memory under the control of the microcomputer; and between the memory and the data / address bus, the data / address A memory controller for controlling data transfer between the memory and the apparatus through a bus and generating control signals for accessing the memory to access the memory, and registers register address data from the microcomputer interface controller. A register designation unit for decoding and outputting address counter values, a memory address register for recording an address of the memory to be accessed from the microcomputer interface control unit at an address designated by the address counter values, the demodulation device and the error correction unit; A priority control unit for outputting a permission signal for allowing memory access according to a predetermined priority with respect to an access request signal for the memory from the government, the descrambler, the interface, and the memory refresh, and the microcomputer interface control unit; An access control unit for outputting the access request signal to the priority control unit based on a read / write signal of the input unit, and inputting the access permission signal applied to the priority control unit to output a path formation signal; Inputs the signal as a counter operation signal and outputs the memory address predetermined by the counter operation signal to the memory controller, starting with the value of the memory address register, and an address with the memory controller by the passage forming signal. A memory address counter in which a bus passage is formed and read data from the memory, input by the register designation unit, and outputted to the microcomputer interface controller, and temporarily storing write data of the microcomputer interface controller; Interface device for memory access, characterized in that consisting of a data register for outputting. A register designation section having a register address counter, a memory address register storing a memory address to be addressed at a location specified by address counter values of the register designation section, and a value of the memory address register by a counter operation signal of a read / write signal; In the interface device having a memory address counter for automatically incrementing the memory address and outputs the memory address to the memory, the interface signal for accessing the memory by the microcomputer outputs the write signal when the write mode is entered. Write a first register address to the register designation section, write the memory address to a designated area of the memory address register, write a second register address to the register designation section, and write the second register address to the register designation section. Writing the write data to the data register designated by the jitter address to write the write data to the memory area designated by the memory address counter, and outputting the read signal when the read mode is entered. Write a register address to the register designation section, write the memory address to a designated area of the memory address register, write the second register address to the register designation section, and write the data register designated by the second register. And reading the read data from the memory stored in the memory. The memory device of claim 6, wherein the memory stores the read data in the data register, or generates a weight signal when the write data stored in the data register is written to the memory to access the data register. Interface method for accessing memory, characterized in that the further step of making it impossible.