JP3555664B2 - Data reproducing method and data reproducing apparatus - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a data reproducing method and a data reproducing apparatus suitable for use in an optical disk device or a magneto-optical disk device for reproducing image data or audio data recorded on a disk such as an optical disk or a magneto-optical disk.
[0002]
[Prior art]
For example, as an optical disk device for reproducing moving image data or audio data recorded on a recording medium such as an optical disk by an image compression method conforming to a predetermined standard such as MPEG, for example, Japanese Patent Application No. There is one disclosed in the specification and drawings of 4-92223.
[0003]
That is, as shown in FIG. 19, in this optical disk device, the pickup 2 irradiates the optical disk 1 with laser light, and reproduces, for example, image data recorded on the optical disk 1 from the reflected light. Data output from the pickup 2 is input to a demodulation circuit 3 where it is demodulated. The output of the pickup 2 is also input to a phase locked loop (PLL) circuit 9 to extract a clock. This clock is sent to the demodulation circuit 3 and the sector detection circuit 4. The data demodulated by the demodulation circuit 3 is input to the ECC circuit 6 via the sector detection circuit 4, where error detection and correction are performed.
[0004]
The sector detection circuit 4 detects a sector number (address assigned to a sector of the optical disc 1) from the data demodulated by the demodulation circuit 3 and outputs the same to the control circuit 31. Further, the sector detection circuit 4 outputs, for example, a sector number abnormality signal to the track jump determination circuit 7 if the sector number cannot be detected or if the sector number can be detected, for example, if the sector numbers are not continuous. .
[0005]
The ECC circuit 6 detects a data error from the data supplied from the demodulation circuit 3 via the sector detection circuit 4, and performs error correction using a parity bit (parity data) added to the data. Further, when the ECC circuit 6 cannot correct the data error, it outputs an error occurrence signal to the track jump determination circuit 7. The error-corrected data is supplied from the ECC circuit 6 to the track jump ring buffer memory 5 and stored therein under the control of the control circuit 31.
[0006]
The control circuit 31 reads an address of each sector of the optical disc 1 from the output of the sector detection circuit 4, and stores data from the ECC circuit 6 in the ring buffer memory 5 corresponding to the address (ring buffer memory). 5) The write address (write point (WP)) is specified. Further, the control circuit 31 specifies a read address (reproduction point (RP)) of the data written in the ring buffer memory 5 based on the code request signal from the video code buffer memory 10 of the decoding unit 20 at the subsequent stage. Then, data is read from the reproduction point (RP), supplied to the video code buffer memory 10, and stored.
[0007]
The data stored in the video code buffer memory 10 is transferred to the inverse VLC circuit 11 based on a code request signal from the subsequent inverse VLC circuit 11. The inverse VLC circuit 11 performs an inverse VLC process on the input data. When the inverse VLC process on the input data is completed, the inverse VLC circuit 11 outputs the data to the inverse quantization circuit 12 and sends a code request signal to the video code buffer 10. Output and request input of new data. Further, the inverse VLC circuit 11 outputs the quantization step size or the motion vector to the inverse quantization circuit 12 or the motion compensation circuit 15, respectively.
[0008]
The inverse quantization circuit 12 inversely quantizes the input data according to the quantization step size supplied from the inverse VLC circuit 11 and outputs the data to the inverse DCT circuit 13. The inverse DCT circuit 13 performs an inverse DCT process on the input data, and supplies the data to the addition circuit 14.
[0009]
When the data supplied from the inverse DCT circuit 13 to the addition circuit 14 is I-picture data, the data is output to the frame memory 16 via the addition circuit 14 and stored as it is.
[0010]
If the data is data of a P picture having an I picture as a prediction image, data of the already decoded I picture is read from the frame memory 16 and supplied to the motion compensation circuit 15. The motion compensation circuit 15 performs motion compensation corresponding to the motion vector supplied from the inverse VLC circuit 11 on the data supplied from the frame memory 16 to obtain a predicted image, and supplies the predicted image to the addition circuit 14. The addition circuit 14 adds the data output from the inverse DCT circuit 13 and the data output from the motion compensation circuit 15 to generate P picture data. This data is also stored in the frame memory 16.
[0011]
If the data output from the inverse DCT circuit 13 is B-picture data, the already decoded I-picture or P-picture data is read from the frame memory 16 and supplied to the motion compensation circuit 15. The data supplied to the motion compensation circuit 15 is subjected to motion compensation there, and is supplied to the addition circuit 14. The addition circuit 14 adds the data output from the inverse DCT circuit 13 and the data output from the motion compensation circuit 15, so that decoded B picture data is obtained. This data is also stored in the frame memory 16.
[0012]
The image data decoded as described above and stored in the frame memory 16 is subjected to D / A conversion by the D / A converter 17, and then supplied to the display 18 for display.
[0013]
As described above, the control circuit 31 supplies the data stored in the ring buffer memory 5 to the video code buffer memory 10 in response to the code request signal from the video code buffer memory 10; When the data processing for the image continues and the data transfer amount from the video code buffer memory 10 to the inverse VLC circuit 11 decreases, the data transfer amount from the ring buffer memory 5 to the video code buffer memory 10 also decreases. Then, the amount of data stored in the ring buffer memory 5 increases, and there is a possibility of overflow.
[0014]
Therefore, the track jump determination circuit 7 calculates (detects) the amount of data currently stored in the ring buffer memory 5 from the write point (WP) and the reproduction point (RP) controlled by the control circuit 31, and When the data amount exceeds a predetermined reference value set in advance, it is determined that there is a possibility that the ring buffer memory 5 overflows, and a track jump command is output to the tracking servo circuit 8.
[0015]
When the track jump determination circuit 7 detects a sector number abnormal signal from the sector detection circuit 4 or an error occurrence signal from the ECC circuit 6, the write point (WP) and the reproduction point (RP) controlled by the control circuit 31 are controlled. ), The amount of data remaining in the ring buffer memory 5 is determined. Also, while the optical disk 1 makes one rotation from the current track position (while waiting for one rotation of the optical disk 1), reading from the ring buffer memory 5 to the video code buffer memory 10 is guaranteed (the ring buffer memory). 5 to obtain the necessary data amount (to prevent underflow from occurring).
[0016]
If the amount of remaining data in the ring buffer memory 5 is sufficiently large, even if data is read from the ring buffer memory 5 to the video code buffer memory 10 at the highest transfer rate, no underflow occurs in the ring buffer memory 5. The track jump determination circuit 7 determines that the error recovery is possible by reproducing the error occurrence position by the pickup 2 again, and outputs a track jump command to the tracking servo circuit 8.
[0017]
When the track jump command is output from the track jump determination circuit 7, the tracking servo circuit 8 causes the track reproduced by the pickup 2 to jump. That is, for example, when data is recorded from the inner circumference to the outer circumference of the optical disc 1, the tracking servo circuit 8 causes the pickup 2 to jump from the current position to an adjacent track on the inner circumference side. Then, a new reproduction position by the pickup 2 is maintained until the optical disk 1 makes one rotation again to reach the original position, that is, until the sector number obtained from the sector detection circuit 4 becomes the sector number at the time of the track jump. Writing of data to the ring buffer memory 5 is prohibited, and data already stored in the ring buffer memory 5 is transferred to the video code buffer memory 10 as necessary.
[0018]
Also, after the track jump, even if the sector number obtained from the sector detection circuit 4 matches the sector number at the time of the track jump, if the data amount stored in the ring buffer memory 5 exceeds a predetermined reference value, When there is a possibility that the ring buffer memory 5 overflows, data writing to the ring buffer memory 5 is not restarted, and the track jump is performed again.
[0019]
Here, the ring buffer memory 5 has a capacity capable of storing data of at least one track (one rotation) of the optical disc 1.
[0020]
Therefore, when the optical disk 1 is, for example, a constant linear velocity (CLV) disk, the rotation cycle is maximum at the outermost circumference, and thus the storage capacity of one track (one rotation) at the outermost circumference, that is, (rotation of the outermost circumference) It has at least a storage capacity of (cycle) × (data transfer rate from the ECC circuit 6 to the ring buffer memory 5).
[0021]
The maximum transfer rate of data from the ring buffer memory 5 to the video code buffer memory 10 is set to a value equal to or smaller than the data transfer rate from the ECC circuit 6 to the ring buffer memory 5. By doing so, a code request for data transfer from the video code buffer memory 10 to the ring buffer memory 5 can be freely transmitted regardless of the track jump timing.
[0022]
As described above, according to this optical disk device, the pickup 2 is caused to make a track jump according to the storage capacity of the ring buffer memory 5, so that regardless of the complexity or flatness of the reproduced image from the optical disk 1, Overflow or underflow of the video code buffer memory 10 is prevented, and an image of uniform quality can be reproduced for a long time.
[0023]
Further, according to this optical disk device, when an error occurs in the data read from the optical disk 1, the pickup 2 is caused to perform a track jump and the data is read from the optical disk 1 again. Degradation can be prevented.
[0024]
Incidentally, the ECC circuit 6 in the optical disk device of FIG. 19 is configured as shown in FIG. 20, for example. Data output from the demodulation circuit 3 (FIG. 19) is input to the ECC circuit 6 via the sector detection circuit 4, and is temporarily stored in the buffer memory 41 (FIG. 20) at the input stage. The data stored in the buffer memory 41 is sequentially transferred to the memory 42 and stored according to the address generated by the address generator 43. The data stored in the memory 42 is read therefrom and transferred to the error correction circuit 44. The error correction circuit 44 performs error correction on the data transferred from the memory 42, and stores the error-corrected data in the memory 42 again.
[0025]
Here, writing and reading of data to and from the memory 42 will be described with reference to a memory map of FIG. The circles in the figure indicate one symbol unit of error correction, usually one byte. Writing or reading of data to / from the memory 42 is performed in units of one data length in one horizontal row of the memory map shown in FIG. At the end, a parity bit (a shaded portion in the figure) is added, and the parity bit is added in a diagonal direction of the memory map (hereinafter referred to as an interleave direction) (a direction indicated by a dotted arrow in the figure). The parity bit as the last part of the data arrangement is a parity bit for correcting errors in the data arranged in the interleave direction.
[0026]
That is, for example, in order to isolate a burst error, data and parity bits for correcting an error of the data are arranged in the interleave direction.
[0027]
Therefore, in the memory 42, first, the data from the buffer memory 41 is written in the address direction according to the address indicated by the write pointer wp1.
[0028]
The address direction means a direction from left to right and from top to bottom in the memory map of FIG.
[0029]
Then, according to the address indicated by the read pointer rp1 delayed by at least the storage capacity (address) required to read data in the interleave direction (hereinafter referred to as the interleave length), the data already written in the memory 42 is The data is read out in the interleave direction and supplied to the error correction circuit 44. The error correction circuit 44 performs an error correction process on the data arrangement in the interleave direction as described above, and the error-corrected data is transferred to the memory 42.
[0030]
The data error-corrected by the error correction circuit 44 is written again at the first written position (address) according to the address indicated by the write pointer wp2, and according to the read pointer rp2 moving in the address direction, the buffer memory 45 (FIG. 20). ).
[0031]
By repeating the above operation as one cycle, the error-corrected data is sequentially output from the buffer memory 45 to the ring buffer memory 5 (FIG. 19).
[0032]
Therefore, the error-corrected data is once stored in the memory 42 (FIG. 20) and then stored in the ring buffer memory 5 again.
[0033]
As described above, in the conventional optical disk device, a redundant operation of sequentially putting data in and out of two different memories (the memory 42 and the ring buffer memory 5) is performed, and the size of the device only increases. However, there is a problem that the data processing speed is reduced.
[0034]
Therefore, the present applicant has previously proposed, as Japanese Patent Application No. 4-285475, to correct an error in data stored in the ring buffer memory 5.
[0035]
[Problems to be solved by the invention]
However, the above proposal has a problem that a correct sector address cannot be read and the optical disk 1 cannot be accessed accurately and quickly.
[0036]
Furthermore, when there is a large error in the data read from the optical disc 1 and the data cannot be corrected, there is a problem that the data cannot be corrected again.
[0037]
Further, there is a problem that it takes time to deinterleave, and it is difficult to perform a high-speed reproduction operation during special reproduction such as fast-forward or rewind.
[0038]
The present invention has been made in view of such a situation, and has an object to enable quick access to a disk and high-speed reproduction of the disk.
[0039]
Further, the present invention improves the error correction capability.
[0040]
[Means for Solving the Problems]
The data reproducing method of the present invention is a data reproducing method for reproducing recorded data recorded on a disc, Calculated including the sector header From the disk on which the recording data including the error correction code of the two systems is recorded, the recording data is read via the pickup, the read data is demodulated, the demodulated data is stored in the memory, and the demodulated data is demodulated. The data is subjected to error correction by one of two error correction codes, and if the error of the demodulated data is correctable, the corrected value is supplied to the memory. Overwrites the value stored in memory and decrypts the data read from memory And detects a sector address from a sector header of the error-corrected data. It is characterized by the following.
[0041]
The two systems of error correction codes are a first error correction code added to data interleaved with data recorded on the disk, and a second error correction code added to data not interleaved. Consists of correction code The error correction for the demodulated data is performed by the second error correction code. be able to.
[0042]
If the error with respect to the demodulated data cannot be corrected, the data stored in the memory is read out, corrected again by the first error correction code, and the corrected value is supplied to the memory. Overwrites the value read from the memory and decrypts the data read from the memory can do.
[0047]
A valid period and an invalid period are set based on the continuity of valid sector addresses among the detected sector addresses, and when a valid sector address is not detected during the valid period, the sector addresses are interpolated. it can.
[0049]
A data reproducing apparatus of the present invention is a data reproducing apparatus for reproducing recorded data recorded on a disc, Calculated including the sector header A reading means (for example, a pickup 2 in FIG. 1) for reading recording data from a disc (for example, the optical disc 1 in FIG. 1) on which recording data including two systems of error correction codes are recorded, and a data read by the reading means. Means for demodulating the data, a memory for storing data demodulated by the demodulation means (for example, the ring buffer memory 5 in FIG. 1), and one of two error correction codes for the demodulated data. Error correction means (for example, the error correction circuit 71 in FIG. 1) for performing error correction, and when an error in the demodulated data can be corrected, the corrected value is supplied to the memory and stored in the memory. The control means (for example, the control circuit 74 in FIG. 1) for controlling to overwrite the value, and the decoding means (for example, FIG. Decoding unit of 20) and A sector address detecting means for detecting a sector address from a sector header of error-corrected data; It is characterized by having.
[0050]
The two systems of error correction codes are a first error correction code added to data interleaved with data recorded on the disk, and a second error correction code added to data not interleaved. Correction code The error correction for the demodulated data performed by the error correction means is performed by the second error correction code. be able to.
[0051]
control Means are For demodulated data error But Uncorrectable Met If stored in memory Is Data Is read by the error correction means using the first error correction code. Correct again Is performed, the corrected value is supplied to the memory, the value stored in the memory is overwritten, and the data read from the memory is controlled to be decoded. can do.
[0056]
A valid period and an invalid period are set based on the continuity of the valid sector addresses among the detected sector addresses, and means for interpolating the sector addresses when no valid sector address is detected during the valid period is provided. Features.
[0058]
[Action]
In the data reproducing method and the data reproducing apparatus having the above-described configuration, data such as image data recorded on a disk is read out and demodulated by a pickup as a reproducing point, and temporarily stored in a memory such as a ring buffer memory. Is done. Then, the error of the data stored in this memory is, for example, Calculated including the sector header The error is corrected by one of the two error correction codes. If the error in the demodulated data is correctable, the corrected value overwrites the value stored in the memory, and the data is read from the memory and decoded. , Sector address is detected from sector header of error-corrected data . Therefore, not only errors can be reduced, but also quick access to the disk and high-speed reproduction can be achieved.
[0059]
【Example】
FIG. 1 is a block diagram showing the configuration of an embodiment of an optical disk device to which the data reproducing method of the present invention is applied. In the figure, parts corresponding to those in FIG. 19 are denoted by the same reference numerals.
[0060]
Next, before describing the optical disk device, a data format on the optical disk 1 reproduced by the optical disk device will be described with reference to FIG.
[0061]
In FIG. 2, circles indicate data of one symbol (one byte). In the data, for example, one code (one line) is in units of 128 bytes, and includes a sector header for every 16 codes.
[0062]
As shown in FIG. 3, the sector header includes a sector mark indicating the sector header, a sector address which increases by one for each sector, and a cyclic code (CRC) for detecting an error in the sector header.
[0063]
As shown in FIG. 2, in the data in which one row is arranged every 128 bytes, an error correction code of 16 bytes is added as inner parity to data read in a diagonal direction (direction of arrow A). In the figure, a circle with a vertical line added therein indicates an inner parity. For the inner parity, so-called convolution is performed, and the parity is calculated without interruption from the beginning to the end of the data in the oblique direction. The code of 144 (= 128 + 16) bytes in the oblique direction is called an inner code.
[0064]
Next, data is read in the horizontal direction (in the direction of arrow B) from the row for which the inner parity has been calculated. It is added as parity. In FIG. 2, a circle with a horizontal line indicates an outer parity. The code of 160 (= 128 + 16 + 16) bytes in the horizontal direction is called an outer code.
[0065]
These two types of parity (inner parity and outer parity) are calculated including the sector header, and an error occurring in the sector header can be corrected by outer code correction or inner code correction.
[0066]
As shown in FIG. 2, a sync signal is added to the head of 160 bytes (128 bytes of data, 32 bytes of inner and outer parities) of each row.
[0067]
The pickup 2 shown in FIG. 1 irradiates a laser beam onto the optical disc 1 on which image data is recorded in the format described above, and reproduces, for example, image data recorded on the optical disc 1 from the reflected light. Data output from the pickup 2 is input to the demodulation circuit 3 and demodulated. The output of the pickup 2 is also input to the PLL circuit 9 to extract a clock. This clock is sent to the demodulation circuit 3 and the buffer memory 61. The data demodulated by the demodulation circuit 3 is input to the buffer memory 61. The data output from the buffer memory 61 is written into the ring buffer memory 5 under the control of the control circuit 74.
[0068]
The demodulation circuit 3 has a sync protection function. That is, in the normal reproduction state of the disc, syncs are obtained at equal intervals at the beginning of each code from the reproduction data, but when no sync is obtained, the interpolation of the sync is performed as shown in FIG. That is, since the sync occurs at a fixed cycle, if no sync is detected at this cycle, the sync is generated and output in a pseudo manner. Since the circuits subsequent to the demodulation circuit 3 use the sync as one operation unit, stable operation can be performed by such sync interpolation.
[0069]
The demodulation circuit 3 has a built-in conversion table and performs demodulation by comparing input data with a conversion table for each modulation unit. If a combination is found, an error flag is set for each symbol (the flag is set to 1). Further, the locked state of the PLL is known from the clock supplied from the PLL circuit 9, and an error flag is set while the lock is released.
[0070]
Further, when the sync is interpolated and when the number of error flags in one code is larger than a predetermined number, an error flag is set for all symbols having one code length. This error flag is sent to the buffer memory 61 together with the data.
[0071]
Next, writing and reading of data to and from the ring buffer memory 5 and the flag register 73 will be described.
[0072]
As the ring buffer memory 5, a static random access memory (SRAM) or a dynamic random access memory (DRAM) can be used. An SRAM is different from a DRAM in that data can be continuously written or read at a high speed without limitation, but is expensive.
[0073]
On the other hand, although DRAMs are inexpensive, it is necessary to use a so-called high-speed page mode to write or read data at high speed. The page unit in the high-speed page mode is limited to, for example, 256 bytes, and when reading or writing data beyond this, it is necessary to switch pages. The shorter the number of page switching, the shorter the processing time. Therefore, the present apparatus reads and writes data in different directions depending on whether the outer code is corrected (correction in the direction of arrow B in FIG. 2) or the inner code is corrected (correction in the direction of arrow A in FIG. 2). In this case, in any case, a method of storing data in the ring buffer memory 5 is devised so that page switching is performed at equal intervals as much as possible and the number of times of switching is reduced. .
[0074]
Hereinafter, a method of storing data in the ring buffer memory 5 will be described. That is, the data in the format shown in FIG. 2 is represented by a matrix D (i, j), where i is the code number (row in FIG. 2), j is the number of the symbol in the code from the top of the sync, and . In this case, the i-th (i-th row) code is composed of 160 symbols from D (i, 0) to D (i, 159). The data sequence in the inner code direction (the direction of arrow A in FIG. 2) is represented as follows.
D (i, 0), D (i + 1,1), D (i + 2,2),
...., D (i + 143, 143)
[0075]
On the other hand, the address of the ring buffer memory 5 is represented as R (m, n), where m is the row address and n is the column address. n is a value of 0 or more and 159 or less. The row address and the column address are each 16 pages. Here, the data D (i, j) in the format of FIG. 2 is written into the ring buffer memory 5 at an address R (m, n) indicated by m and n obtained by the following equation. That is,
k = (15− (i mod 16)) + j
And then
m = i
n = k when k <160
When k ≧ 160, n = k−160
It is said. However, the operator mod represents a remainder.
[0076]
FIG. 5 shows a state where the data D (i, j) is stored at the address R (m, n) of the ring buffer memory 5. In this case, the data order of the outer code and the inner code starting from D (1, 0) is as shown in FIG. As is clear from FIG. 6, since the outer code is arranged in the horizontal direction and the inner code is arranged in the vertical direction, in each case, except for the first few symbols, every 16 symbols, at equal intervals, Page switching occurs. Therefore, by storing the data in the ring buffer memory 5 in this manner, both the outer code and the inner code can realize high-speed reading and writing in the high-speed page mode.
[0077]
Writing to and reading from the ring buffer memory 5 is performed at a rate several times the data rate input from the demodulation circuit 3 to the buffer memory 61, for example, five times. FIG. 7 shows the timing. The one sync time in FIG. 7 is the same time (sync cycle) as the interval between the syncs shown in FIG. 4, and is the time when 160 bytes of one code data is input from the demodulation circuit 3 to the buffer memory 61. Corresponding to
[0078]
Xw in FIG. 7 indicates a timing (period) at which data for one sync temporarily stored in the buffer memory 61 is written to the ring buffer memory 5. Xc indicates the timing (period) of rewriting the error symbol and the outer code flag. Yr indicates the timing (period) of reading the inner code data on the ring buffer memory 5. Yc indicates the timing (period) of rewriting the error symbol and the inner code flag. Zr indicates the timing (period) of reading data from the ring buffer memory 5 to the video code buffer memory 10.
[0079]
FIG. 8 schematically shows the memory space of the ring buffer memory 5 with one code length as one horizontal row (actually, as shown in FIG. 5 and FIG. Is stored). The write pointer of Xw is indicated by PXw. It is assumed that each pointer moves upward in the figure.
[0080]
The ring buffer memory 5 is provided with an area for storing a correction result flag of the outer code correction and the inner code correction, one bit for each code, and is shown at the right end of FIG. is there.
[0081]
9 and 10 show configuration examples of the flag register 73. In the case of this embodiment, data input through the switch 81 is output through 144 switches and further through the switch 82. The output data is returned to 144 consecutive registers again via one register and the switch 81.
[0082]
Now, the error correction is in progress, and the inner code correction in the direction of arrow A in FIG. 8 including the symbol one below the outer code correction PYr for the PYr row shown in FIG. 8 has been completed. And At this time, the past outer code flags fi + 143, fi + 142,... Fi are stored in the 144 registers of the flag registers 73, as shown in FIG. The progress from the empty state of the flag register 73 (that is, the state where error correction is started for the first time) to such a state will be described later. The operation from error correction until data is sent to the video code buffer will be described below with reference to the timing chart of FIG.
[0083]
When writing one row of data indicated by the pointer PXw of FIG. 8 stored in the buffer memory 61 to the ring buffer memory 5 during the period Xw of FIG. 7, the control circuit 74 causes the switching contact piece 63, 64 are all connected to the contact a side. The data output from the buffer memory 61 is written into the ring buffer memory 5 and, at the same time, along with the error flag output from the buffer memory 61, via the switching contact 63 or 64 of the switch 62. The signal is input to the correction circuit 71 (corresponding to the error correction circuit 44 in FIG. 20). The error correction circuit 71 performs erasure correction on the input data of the row indicated by the pointer PXw in FIG. 8 using the external parity and the error flag in the period Xw. As a result of the correction, an error symbol and its correction value are obtained.
[0084]
Next, in a period Xc of FIG. 7, the error correction circuit 71 supplies the corrected value to the ring buffer memory 5 and the flag register 73, and the ring buffer memory 5 corrects the corrected value for the corresponding error symbol. Is overwritten. In addition, since the correction has been performed, the outer code flag in FIG. 8 (in this case, the outer code flag fi + 144) is set to zero. If the error cannot be corrected due to a large number of errors, the data in the ring buffer memory 5 is not rewritten, and the data cannot be corrected. Therefore, 1 is written to the outer code flag fi + 144.
[0085]
Next, in a period Yr in FIG. 7, the switching pieces 63 and 64 of the switch 62 are switched to the contact b, and the inner buffer is corrected from the position indicated by the pointer PYr to the interleave direction (arrow in FIG. Data is read in the direction A (vertical direction in FIG. 6) and input to the error correction circuit 71. On the other hand, the outer code flags fi + 143, fi + 142,... Fi are sequentially read from the flag register 73 and used for correcting the inner code. The error correction circuit 71 performs error correction (erasure correction) of input data (inner code) using the input outer code flag and inner parity.
[0086]
At this time, the flag register 73 operates as follows. As shown in FIG. 10B, the outer code flag fi + 144 output from the error correction circuit 71 is stored in the leftmost register of the flag register 73 via the contact b of the switch 81. At the same time, the outer code flag fi + 143 stored in the rightmost register of the flag register 73 is output via the switch 82.
[0087]
Next, as shown in FIG. 10C, the switch 81 is switched to the contact a side, and the outer code flag fi + 144 is transferred to the right end of the 144 shift registers. At the same time, the outer code flags fi + 142,... Fi stored in the respective registers are output via the switch 82. Thus, the flag register 73 can output the outer code flags fi + 143, fi + 142,... Fi for one inner code length. The fifty-four registers of the flag register 73 store outer code flags fi + 144, fi + 143, fi + 142,... Fi + 1. In this way, the flag register 73 always stores the latest outer code flag for one inner code length (144).
[0088]
The outer code flag is stored in the flag register 73 and supplied to the error correction circuit 71 despite the fact that the outer code flag is written in the empty area of the ring buffer memory 5. This is because the outer code flag cannot be read simultaneously for each symbol.
[0089]
Next, in the period Yc in FIG. 7, the corrected value is sent to the ring buffer memory 5 and overwritten for the error symbol in the ring buffer memory 5 in the same manner as the correction of the outer code. If the error cannot be corrected due to many errors, the data is not rewritten.
[0090]
In addition, in all of the inner code flags gi to gi + 143, zero if an error has been corrected, and 1 if the error cannot be corrected, is written in the free area of the ring buffer memory 5, respectively. However, among the inner code flags gi to gi + 143, nothing is written to the one in which 1 has already been written in the past inner code correction.
[0091]
This operation will be described with reference to FIG. In FIG. 11, if only the three inner codes indicated by the pointers PYr1, PYr2, and PYr3 cannot be corrected, the inner code flag is written as shown in FIG. That is, the inner code flag indicates how far the uncorrectable inner code extends from the outer code direction.
[0092]
Thus, the data in the ring buffer memory 5 after the error correction is finally read out to the video code buffer memory 10 of the decoding unit 20 in the period Zr in FIG. PZr in FIG. 8 is a read pointer in this case. Although the data is read in the forward direction (horizontal direction), the inner parity and the outer parity are unnecessary (because the correction has already been completed), so the data is skipped and read (not read). As shown in FIG. 8, the logical product of the outer code flag fj and the inner code flag gj via an AND gate (not shown) is output from the video code buffer memory to the PZr as an uncorrectable flag of the code in the j-th row. Sent to 10.
[0093]
A series of operations as described above is repeated according to the timing chart of FIG. 7, and data that has been subjected to outer code correction and inner code correction by the error correction circuit 71 is transferred to the video code buffer 10 via the ring buffer memory 5. Supplied.
[0094]
Here, the reason for taking the logical product of fj and gj is that, for example, when an inner symbol becomes uncorrectable, as shown in FIG. 11, the inner code extends over the length of the inner code length in an oblique direction (interleave direction). This is because a flag is set and an uncorrectable portion cannot be specified. By taking the logical product of the outer code flag fj and the inner code flag gj, if the outer code flag can be corrected even if the inner code flag is set, it can be determined that there is no error in the row j. An uncorrectable flag can be set more accurately for an uncorrectable error part.
[0095]
As shown in FIG. 8, the difference between the pointers PYe and PZr is the remaining data amount in the ring buffer memory 5. Here, PYe represents a pointer to the latest data for which the inner code correction has been completed.
[0096]
The data sent from the ring buffer memory 5 to the video code buffer memory 10 is decoded by the decoding unit 20 in the same manner as in FIG. 19 if the uncorrectable flag is zero (correction is performed correctly). Decrypted). If the uncorrectable flag is 1, the code contains an error. Therefore, the subsequent video decoding circuit (the inverse VLC circuit 11 to the motion compensation circuit 15) stops decoding until the flag becomes zero, and the display 18 Is to repeatedly transmit the image data already decoded and stored in the frame memory 16 (therefore, it becomes a still image), thereby preventing the image from being disturbed.
[0097]
Here, the operation of the flag register 73 from the empty state to the state of FIG. 10A will be described.
[0098]
Now, it is assumed that the pointer PXw is at the position of the outer code flag fi (the position of PYe) in FIG. 8 and error correction starts from this position. When the outer code correction of the row of PYe is completed, as shown in FIG. 9A, the switch 81 is switched to the contact b side, and the outer code flag fi output from the error correction circuit 71 becomes 144 bits. Are input to the leftmost register of consecutive shift registers. The outer code flag fi of the left end shift register is sequentially shifted rightward in the 144 shift registers and transferred to the right end register.
[0099]
Next, the pointer PXw is moved up by one line in FIG. 8 (that is, a position one line above PYe). Then, outer code correction of the code of the row is performed, and as shown in FIG. 9B, the outer code flag fi + 1 is input to the leftmost register of the 144 consecutive shift registers. At this time, the outer code flag fi of the rightmost register of the 144 consecutive shift registers is transferred to one register.
[0100]
Further, as shown in FIG. 9C, the switch 81 is switched to the contact a side, and the outer code flag fi + 1 is sequentially shifted rightward in the 144 shift registers and transferred to the rightmost register. At this time, since the switch 81 has been switched to the contact a side, the outer code flag fi is input to the left end of the 144 shift registers, sequentially shifted rightward, and transferred from the right end to the immediately preceding register. Is done.
[0101]
Next, the pointer PXw is further moved up by one line (that is, a position two lines above PYe). Then, the outer code of the code in that row is corrected, and as shown in FIG. 9D, the switch 81 is switched to the contact b side, and the outer code flag fi + 2 is set to the leftmost register of 144 consecutive shift registers. Is input to At this time, the outer code flag fi + 1 of the rightmost register of the 144 consecutive shift registers is transferred to one register. The outer code flag fi is transferred to the rightmost register of the shift register.
[0102]
Further, as shown in FIG. 9E, the switch 81 is switched to the contact a side, and the outer code flag fi + 2 is sequentially shifted rightward in the 144 shift registers and transferred to the rightmost register. At this time, since the switch 81 has been switched to the contact a side, the outer code flags fi + 1 and fi are sequentially input to the left ends of the 144 shift registers, and further sequentially shifted to the right, two positions before the right end. Is transferred to the three registers before.
[0103]
Next, as shown in FIG. 9F, the switch 81 is switched to the contact b side, and the same processing is repeated thereafter. Therefore, the outer code flag is input to the flag register 73 at a rate of one per one sync. 9A to 9F and FIG. 10, the switch 82 is open and the outer code flag is not output.
[0104]
As described above, when the pointer PXw reaches the position shown in FIG. 8, as shown in FIG. 10A, 144 registers of the flag register 73 have the outer code flags fi + 143, fi + 142,. fi is stored.
[0105]
By the way, assuming that the memory space of the ring buffer memory 5 is represented by a circle as shown in FIG. 12, the pointers PXw, PYr, and PZr rotate in the direction shown by the arrows (counterclockwise) without overtaking each other. become. The distance between the pointers PXw and PYr is constant and does not separate. The ring buffer memory 5 reads data in response to a request from the video code buffer memory 10 and supplies the data to the video code buffer memory 10, and the data remaining amount shown in the figure changes accordingly.
[0106]
The reading and writing of data to and from the ring buffer memory 5 is controlled by the control circuit 74, and the pointers PXw, PYr, and PZr are managed by the control circuit 74. The control circuit 74 also controls writing and reading to and from the flag register 73.
[0107]
Next, the extraction of the sector address will be described. As described above, the data output from the buffer memory 61 is supplied to the error correction circuit 71 via the switch 62, where the data is corrected. The outer code corrected data is sent to the sector detection circuit 72 together with the outer code flag. Sent. The sector detection circuit 72 searches the input data for a sector mark and detects a sector header. Then, error detection by CRC is performed. Further, the sector address is read from the sector header and stored (FIG. 3).
[0108]
The sector address is sent to the control circuit 74 when no error is detected by CRC error detection or when the outer code flag is zero even if an error is detected by CRC error detection.
[0109]
The extraction of the sector address is performed after the outer code is corrected. However, since the outer code is arranged in the same direction as the arrangement of the data on the optical disc 1, it is weak against a burst error, and the sector address cannot be obtained because it cannot be corrected. There is. In addition, an erroneous correction may occur in the outer code correction. Therefore, a correct sector address is not always obtained for each sector. Therefore, the correctness of the sector address is monitored by a flywheel operation in the control circuit 74 described below.
[0110]
Next, the flywheel operation of the sector address will be described. The control circuit 74 monitors the sector address input from the sector detection circuit 72, and if the sector address can be detected at 16 code intervals (FIG. 2) and the value of the sector address increases by one, Validate the address. If the valid sector address continues for a preset number of sectors, for example, three or more sectors, the flywheel (flag) is turned on.
[0111]
When the flywheel is on and the state where the sector address is not valid continues for a preset number of sectors, for example, 5 sectors or more, the flywheel is turned off. Such a state can occur, for example, when the pickup 2 flies to another truck due to an impact or the like. In this case, an abnormality processing operation is performed. This will be described later.
[0112]
FIG. 13 shows the state of the flywheel. A indicates a valid sector address, and X indicates an invalid sector address. The subscript of A indicates an address value. It is assumed that sector addresses are obtained from left to right. Starting from A22, the effective sector address is obtained continuously for three sectors A23, A24, and A25, and the flywheel is turned on. After A32, the flywheel is turned off because an effective sector address cannot be obtained for five consecutive sectors.
[0113]
When the flywheel is on, the last valid sector address obtained is stored while being constantly updated as the latest valid sector address. In FIG. 13, A32 is the latest valid sector address.
[0114]
By turning the flywheel on and off in this way, it is monitored whether or not the sector address is obtained correctly. If there is an error in the data and the sector address cannot be obtained temporarily, the sector address is immediately updated. By interpolating as continuous from the value, stable writing of data to the ring buffer memory 5 becomes possible.
[0115]
When the reproduction of the optical disk 1 is started, the data output from the buffer memory 61 is not immediately written to the ring buffer memory 5. Only when the sector address is continuously detected in the control circuit 74 and the flywheel is turned on, the pointers PXw and PYr are sent to the ring buffer memory 5, and the writing and reading of the ring buffer memory 5 and the error correction circuit 71 are performed. , The error correction of the inner code is started (the correction of the outer code is always performed). The same applies to the case where writing is interrupted and then resumed. Writing to the ring buffer memory 5 is always performed with the flywheel turned on.
[0116]
Next, a track jump of the pickup 2 will be described. When the remaining amount of data in the ring buffer memory 5 exceeds the set value and there is a possibility of overflow, that is, in the case where the pointer PXw may catch up with PZr in FIG. Command is output. At this time, the writing and reading of the ring buffer memory 5 and the error correction operation of the inner code of the error correction circuit 71 are interrupted. Then, the flywheel is turned off, and the latest valid sector address, for example, A32 in FIG. 13 is stored.
[0117]
FIG. 14 shows recording tracks on the optical disc 1. In this figure, the latest effective sector address A32 is located just before the point P where the jump starts. When a jump is commanded, the pickup 2 (reproduction point) jumps from point P to point Q, starts reading the inner track, and the flywheel turns on again, as shown in the figure. When the optical disk 1 makes one round and the pickup 2 arrives at the latest effective sector address A32 stored therein, writing and reading of the ring buffer memory 5 and error correction of the inner code of the error correction circuit 71 are restarted from there.
[0118]
FIG. 15A shows a state in which the sector address is detected when the pickup 2 comes to the point P again. Writing of data to the ring buffer memory 5 from the sector A32 is restarted.
[0119]
Here, A32 may be an invalid sector. FIG. 15B shows an example of such a case. In this case, since the flywheel is on, even if A32 is not detected, interpolation is performed from a past address. Then, the writing operation is restarted from the data 16 codes after A31.
[0120]
By performing the above operation, continuous data can be continuously written in the ring buffer memory 5 even though the writing is interrupted by the track jump.
[0121]
While the pointers PXw and PYr (PYe) are stopped by the track jump, data is read out in response to a request from the video code buffer memory 10 during that time. Therefore, the pointer PZr advances counterclockwise in FIG. The amount is reduced and overflow can be prevented.
[0122]
Next, the abnormality processing operation will be described. For example, it is assumed that the pickup 2 causes an unintended track jump due to mechanical vibration (disturbance) or the like. At this time, since a continuous sector address cannot be obtained, the flywheel is turned off, and the writing and reading of the ring buffer memory 5 and the error correction operation of the inner code of the error correction circuit 71 are interrupted. At this time, the control circuit 74 refers to the latest effective sector address and moves the pickup 2 so as to read out, for example, 20 sectors before. By doing so, the flywheel is turned on again before the latest valid sector address, and writing can be resumed from the latest valid sector in the same manner.
[0123]
At this time, if there is sufficient data remaining, the data remaining in the ring buffer memory 5 may not become zero before the pickup 2 returns to the position where an unintended track jump has occurred and resumes data reading. Absent. Therefore, reading from the ring buffer memory 5 to the video code buffer memory 10 is not interrupted, and recovery can be performed without affecting image decoding / reproduction at all.
[0124]
Next, processing when error correction becomes impossible will be described. FIG. 16 shows each pointer on the ring buffer memory 5, as in FIG. Here, it is assumed that the portion represented by the point X after the point R cannot be corrected by the outer code correction and the inner code correction. The control circuit 74 stores the address of the head sector of the uncorrectable portion. When the control circuit 74 determines that the error can be corrected, the correction is advanced to a point S which is a fixed distance from the end of the uncorrectable portion, for example, 5 sectors after.
[0125]
Further, the control circuit 74 calculates a time obtained by adding a time required for performing error correction from the point R to the point S to a time required for one round of the disk. Then, this time is multiplied by the maximum speed of data transfer from the ring buffer memory 5 to the video code buffer memory 10, and the maximum amount of data that can be lost by the ring buffer memory 5 is obtained within the time obtained by the multiplication. . Further, this data amount is compared with the remaining data amount on the ring buffer memory 5. If the remaining data amount is larger, the pointer PZr cannot catch up with PYr, so that it is determined that the data can be repeatedly corrected.
[0126]
Here, the time for one round of the disc is obtained to some extent accurately from the position information of the pickup 2 in the radial direction of the disc. Possibilities can be increased. That is, when the pickup 2 is located near the outermost circumference of the disk 1, the rotation period of the disk is long, and the above-mentioned re-correction cannot be performed unless a corresponding remaining amount of data remains in the ring buffer memory 5. When it is on the inner circumference, the rotation cycle is short and the remaining data amount is at least re-correctable.
[0127]
If it is determined that the correction can be repeated, a track jump is first performed to stop reading from the optical disc 1, and the switching contacts 63 and 64 of the switch 62 are switched to the contact b. The pointers PXw and PYr are returned to the point R as shown in FIG. 17, from which the outer code correction and the inner code correction are started again. When the correction is completed up to the point S, the pointer is stopped there, the contact pieces 63 and 64 of the switch 62 are switched to the contact point a, and the writing is restarted after the data after the point S is read from the optical disc 1. The writing at this point S is restarted from the latest valid sector address as in the case of the track jump described above.
[0128]
Note that the error flag from the demodulation circuit 3 has already been lost. Therefore, when performing iterative correction, since there is no error flag to be referred to at the time of the second outer code correction, normal correction (correction using only outer parity instead of erasure correction) is performed. However, the outer code flag obtained by the second outer code correction is used for the erasure correction of the second inner code correction.
[0129]
By performing such control, the uncorrectable portion can be corrected again without interrupting reading from the ring buffer memory 5 to the video code buffer memory 10 (without affecting image decoding / reproduction at all). It becomes possible. Further, as long as the data remaining amount has a margin, the uncorrectable portion can be repeatedly corrected any number of times, and the error correction capability can be improved.
[0130]
Next, the operation at the time of special reproduction will be described. In special playback such as fast forward and fast rewind (rewind), for example, only I picture data on the optical disc 1 is sequentially read and played. At this time, since the inner code is interleaved, it is necessary to start reading from the desired sector by an interleave length before. Also, at the end of reading, it is necessary to read extra by the interleave length from the required last data. The time required for the deinterleaving is not a problem because the data is continuously processed during the normal reproduction. However, in the special reproduction in which the operation of reading out the desired data (I picture data) at a high speed is repeated, the high speed reproduction becomes difficult. It becomes a factor. That is, this is a factor of delaying the reproduction time.
[0131]
Therefore, at the time of special reproduction, the control circuit 74 controls the ring buffer memory 5, the error correction circuit 71, and the like so that only error correction using the outer code is performed and error correction using the inner code is not performed. During the special reproduction, the switching pieces 63 and 64 of the switch 62 are always switched to the contact a side. As described above, the data output from the buffer memory 61 is sent to the ring buffer memory 5 and the error correction circuit 71, where the data is corrected by an outer code.
[0132]
In normal reproduction, data is read from the ring buffer memory 5 again, sent to the error correction circuit 71, and error correction is performed by the inner code. However, this is not performed in special reproduction. Data is sent to the video code buffer memory 10 in the same manner as during normal reproduction. At this time, the read pointer PZr does not need to be after the pointer PYr as shown in FIG. 8, and the read can be started immediately after the pointer PXw.
[0133]
As described above, since deinterleaving is not performed, data can be quickly transmitted from the ring buffer memory 5 to the video code buffer memory 10, and a high-speed reproduction operation can be performed. Since the inner code correction is not performed, there is a slight disadvantage in terms of error correction capability. However, during special playback, even if the screen freezes temporarily due to error correction failure (even if a still image is reproduced), It is not very noticeable and hardly hinders in practical use.
[0134]
Note that the error correction code may be a complete product code instead of a convolutional code (inner code and outer code). FIG. 18 shows an example of a format when a product code is used. In this embodiment, C1 parity is added to the horizontal data and C2 parity is added to the vertical data. The present invention can be applied to data in such a format by changing the write and read addresses for the ring buffer memory 5.
[0135]
The case where the data reproducing method of the present invention is applied to the optical disk device has been described above, but the present invention can be applied to not only the optical disk device but also, for example, a magneto-optical disk device.
[0136]
Further, the present invention can be applied not only to the case of reproducing moving image data, but also to the case of reproducing audio data or data in which moving image data and audio data are multiplexed.
[0137]
【The invention's effect】
As described above, according to the data reproducing method and the data reproducing apparatus of the present invention, Calculated including the sector header Since the error of the data is corrected by any one of the two error correction codes, more reliable correction can be performed.
[0138]
Also, in the case of special reproduction or searching for a sector address, for example, error correction can be performed using only one system of error correction codes, and higher-speed reproduction and quick access become possible.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the configuration of an embodiment of an optical disk device to which a data reproducing device of the present invention is applied.
FIG. 2 is a diagram showing a data format of the data reproducing apparatus of the present invention.
FIG. 3 is a diagram showing a configuration of a sector header of the data format of FIG. 2;
FIG. 4 is a diagram showing a state where a sync is interpolated by a demodulation circuit 3 of FIG. 1;
FIG. 5 is a diagram showing a state where data is stored in a ring buffer memory 5 of FIG. 1;
FIG. 6 is a diagram showing an order of writing or reading data in the ring buffer memory 5 of FIG. 1;
FIG. 7 is a diagram showing timings for writing and reading data in the ring buffer memory 5 of FIG. 1;
8 is a diagram schematically showing a memory space of a ring buffer memory 5 in FIG.
FIG. 9 is a diagram illustrating the operation of the flag register 73 of FIG.
FIG. 10 is a diagram illustrating the operation of a flag register 73 of FIG. 1;
FIG. 11 is a diagram illustrating an inner code flag written to a ring buffer memory 5;
FIG. 12 is a view for explaining write and read pointers on the ring buffer memory 5 of FIG. 1;
FIG. 13 is a diagram illustrating an input sector address and on / off of a flywheel.
FIG. 14 is a view showing a locus of a track jump of the pickup 2 on the optical disc 1;
FIG. 15 is a diagram illustrating sector addresses when writing to the ring buffer memory 5 is resumed.
FIG. 16 is a diagram illustrating write and read pointers on the ring buffer memory 5 of FIG. 1;
FIG. 17 is a view for explaining write and read pointers on the ring buffer memory 5 of FIG. 1;
FIG. 18 is a diagram showing a modification of the data format of the data reproducing apparatus of the present invention.
FIG. 19 is a block diagram illustrating a configuration of an example of a conventional optical disc device.
20 is a block diagram showing a more detailed configuration of an ECC circuit 6 of the optical disc device of FIG.
21 is a memory map showing a memory space of a memory 42 of the ECC circuit 6 in FIG.
[Explanation of symbols]
1 optical disk
2 Pickup
3 Demodulation circuit
4 Sector detection circuit
5 Ring buffer memory
6 ECC circuit
7 Track jump judgment circuit
8 Tracking servo circuit
9 PLL circuit
10 Video code buffer memory
11 Reverse VLC circuit
12 Inverse quantization circuit
13 Inverse DCT circuit
14 Addition circuit
15 Motion compensation circuit
16 frame memory
17 D / A conversion circuit
18 Display
20 Decoding section
31 Control circuit
41 buffer memory
42 memory
43 Address Generator
44 Error Correction Circuit
45 buffer memory
61 buffer memory
62 switch
63, 64 switching section
71 Error Correction Circuit
72 sector detection circuit
73 Flag Register
74 control circuit

Claims (8)

In a data reproducing method for reproducing recorded data recorded on a disc,
Reading out the recording data from a disc on which recording data including two systems of error correction codes calculated including the sector header is recorded via a pickup,
Demodulating the read data,
Storing the demodulated data in a memory, and performing error correction on the demodulated data using one of the two error correction codes;
If the error of the demodulated data was correctable, supply the corrected value to the memory, and overwrite the value stored in the memory,
Decoding the data read from the memory ,
A data reproducing method comprising: detecting a sector address from a sector header of the error-corrected data. The two systems of error correction codes are a first error correction code added to data obtained by interleaving data recorded on the disk, and a second error correction code added to data not interleaved. Error correction code,
2. The data reproducing method according to claim 1, wherein the error correction for the demodulated data is performed by the second error correction code. If the error with respect to the demodulated data is uncorrectable, read the data stored in the memory, perform the correction again by the first error correction code, supply the corrected value to the memory, 3. The data reproducing method according to claim 2, wherein a value stored in the memory is overwritten, and data read from the memory is decoded. Setting a valid period and an invalid period based on the continuity of the valid sector addresses among the detected sector addresses;
In the expiration time, if the valid sector address is not detected, the data reproducing method according to claim 1, characterized in that interpolating the sector address. In a data reproducing apparatus for reproducing recorded data recorded on a disc,
Reading means for reading the recording data from a disk on which recording data including two systems of error correction codes calculated including a sector header is recorded;
Demodulating means for demodulating the data read by the reading means,
A memory for storing data demodulated by the demodulation means,
Error correction means for performing error correction on the demodulated data by any one of the two error correction codes;
If the error of the demodulated data was correctable, supply the corrected value to the memory, control means for controlling to overwrite the value stored in the memory,
Decoding means for decoding data read from the memory ;
A data reproducing apparatus, comprising: sector address detection means for detecting a sector address from a sector header of the error-corrected data. The two systems of error correction codes are a first error correction code added to data obtained by interleaving data recorded on the disk, and a second error correction code added to data not interleaved. Error correction code,
6. The data reproducing apparatus according to claim 5 , wherein the error correction for the demodulated data performed by the error correction unit is performed by the second error correction code. When the error in the demodulated data is uncorrectable, the control means reads the data stored in the memory, and the error correction means corrects the error again using the first error correction code, 7. The method according to claim 6 , further comprising: supplying the corrected value to the memory, performing overwriting of the value stored in the memory, and decoding data read from the memory. Data playback device. Means for setting a valid period and an invalid period based on the continuity of valid sector addresses among the detected sector addresses, and interpolating the sector address when the valid sector address is not detected during the valid period. The data reproducing apparatus according to claim 5 , comprising:

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