JP4061550B2 - Data reproduction method and data reproduction apparatus - Google Patents

Description

  The present invention relates to a data reproduction method and a data reproduction apparatus suitable for use in, for example, an optical disk apparatus or a magneto-optical disk apparatus that reproduces image data or audio data recorded on a disk such as an optical disk or a magneto-optical disk.

  For example, as an optical disc apparatus that reproduces moving image data or audio data recorded on a recording medium such as an optical disc by an image compression method that complies with a predetermined standard such as MPEG, for example, Japanese Patent Application No. No. 4-92223 is disclosed in the specification and drawings.

  That is, as shown in FIG. 19, in this optical disc apparatus, the pickup 2 irradiates the optical disc 1 with laser light, and reproduces, for example, image data recorded on the optical disc 1 from the reflected light. Data output from the pickup 2 is input to the demodulation circuit 3 where it is demodulated. The output of the pickup 2 is also input to a phase locked loop (PLL) circuit 9, and a clock is extracted. This clock is sent to the demodulation circuit 3 and the sector detection circuit 4. The data demodulated by the demodulating circuit 3 is input to the ECC circuit 6 via the sector detecting circuit 4, and error detection and correction are performed.

  The sector detection circuit 4 detects the sector number (address assigned to the sector of the optical disc 1) from the data demodulated by the demodulation circuit 3, and outputs it to the control circuit 31. The sector detection circuit 4 outputs a sector number abnormality signal to the track jump determination circuit 7 when the sector number cannot be detected or detected, for example, but is not continuous. .

  The ECC circuit 6 detects a data error from the data supplied from the demodulation circuit 3 via the sector detection circuit 4, and performs error correction using a parity bit (parity data) added to the data. Further, the ECC circuit 6 outputs an error occurrence signal to the track jump determination circuit 7 when the data error cannot be corrected. The data on which the error correction has been performed is supplied from the ECC circuit 6 to the ring buffer memory 5 for track jump and is stored therein under the control of the control circuit 31.

  The control circuit 31 reads the address of each sector of the optical disc 1 from the output of the sector detection circuit 4 and stores the data from the ECC circuit 6 in the ring buffer memory 5 corresponding to the address (ring buffer memory). 5), a write address (write point (WP)) is designated. Further, the control circuit 31 designates the read address (reproduction point (RP)) of the data written in the ring buffer memory 5 based on the code request signal from the video code buffer memory 10 of the subsequent decoding unit 20. Then, data is read from the playback point (RP), supplied to the video code buffer memory 10 and stored.

  The data stored in the video code buffer memory 10 is transferred to the inverse VLC circuit 11 based on the code request signal from the inverse VLC circuit 11 at the subsequent stage. The inverse VLC circuit 11 performs inverse VLC processing on the input data. When the inverse VLC processing of the input data is completed, the inverse VLC circuit 11 outputs the data to the inverse quantization circuit 12 and sends a code request signal to the video code buffer 10. Output and request input of new data. Further, the inverse VLC circuit 11 outputs the quantization step size or the motion vector to the inverse quantization circuit 12 or the motion compensation circuit 15, respectively.

  The inverse quantization circuit 12 inversely quantizes the input data in accordance with the quantization step size supplied from the inverse VLC circuit 11 and outputs it to the inverse DCT circuit 13. The inverse DCT circuit 13 performs inverse DCT processing on the input data and supplies it to the adder circuit 14.

  When the data supplied from the inverse DCT circuit 13 to the adder circuit 14 is I picture data, the data is directly output to the frame memory 16 via the adder circuit 14 and stored.

  If the data is P picture data having an I picture as a predicted image, the already decoded I picture data is read from the frame memory 16 and supplied to the motion compensation circuit 15. The motion compensation circuit 15 performs motion compensation corresponding to the motion vector supplied from the inverse VLC circuit 11 on the data supplied from the frame memory 16 to obtain a predicted image, and supplies the prediction image to the adder circuit 14. The adder circuit 14 adds the data output from the inverse DCT circuit 13 and the data output from the motion compensation circuit 15 to generate P picture data. This data is also stored in the frame memory 16.

  When the data output from the inverse DCT circuit 13 is B picture data, the already decoded I picture or P picture data is read from the frame memory 16 and supplied to the motion compensation circuit 15. The data supplied to the motion compensation circuit 15 is subjected to motion compensation and supplied to the adder circuit 14. The adder circuit 14 adds the data output from the inverse DCT circuit 13 and the data output from the motion compensation circuit 15, so that decoded B picture data is obtained. This data is also stored in the frame memory 16.

  The image data decoded as described above and stored in the frame memory 16 is D / A converted by the D / A converter 17 and then supplied to the display 18 for display.

  Incidentally, as described above, the control circuit 31 supplies the data stored in the ring buffer memory 5 to the video code buffer memory 10 in response to the code request signal from the video code buffer memory 10. If data processing relating to an image continues and the data transfer amount from the video code buffer memory 10 to the inverse VLC circuit 11 decreases, the data transfer amount from the ring buffer memory 5 to the video code buffer memory 10 also decreases. Then, the amount of data stored in the ring buffer memory 5 increases and there is a risk of overflow.

  For this reason, the track jump determination circuit 7 calculates (detects) the data amount currently stored in the ring buffer memory 5 from the write point (WP) and playback point (RP) controlled by the control circuit 31, and When the data amount exceeds a predetermined reference value set in advance, it is determined that the ring buffer memory 5 may overflow, and a track jump command is output to the tracking servo circuit 8.

  When the track jump determination circuit 7 detects a sector number abnormality signal from the sector detection circuit 4 or an error occurrence signal from the ECC circuit 6, the write point (WP) and reproduction point (RP) controlled by the control circuit 31 are detected. ), The amount of data remaining in the ring buffer memory 5 is obtained. Also, reading from the ring buffer memory 5 to the video code buffer memory 10 is guaranteed (ring buffer memory) while the optical disk 1 makes one rotation from the current track position (while waiting for one rotation of the optical disk 1). (In order not to cause underflow in 5), the required data amount is obtained.

  When the remaining data amount of the ring buffer memory 5 is sufficiently large, even if data is read from the ring buffer memory 5 to the video code buffer memory 10 at the highest transfer rate, no underflow occurs in the ring buffer memory 5. The track jump determination circuit 7 determines that error recovery is possible by reproducing the error occurrence position again with the pickup 2 and outputs a track jump command to the tracking servo circuit 8.

  When the track jump determination circuit 7 outputs a track jump command, the tracking servo circuit 8 causes the playback position of the pickup 2 to jump. That is, for example, when data is recorded from the inner periphery to the outer periphery of the optical disc 1, the tracking servo circuit 8 jumps the pickup 2 from the current position to the adjacent track on the inner periphery side. Then, the playback position by the pickup 2 is new until the optical disk 1 rotates once again and reaches the original position, that is, until the sector number obtained from the sector detection circuit 4 becomes the sector number at the time of track jump. Writing of data to the ring buffer memory 5 is prohibited, and data already stored in the ring buffer memory 5 is transferred to the video code buffer memory 10 as necessary.

  In addition, even if the sector number obtained from the sector detection circuit 4 after the track jump matches the sector number at the time of the track jump, the amount of data stored in the ring buffer memory 5 exceeds a predetermined reference value. When there is a possibility that the ring buffer memory 5 overflows, writing of data to the ring buffer memory 5 is not resumed, and a track jump is performed again.

  Here, the ring buffer memory 5 has a capacity capable of storing data for at least one track (one rotation) of the optical disc 1.

  Therefore, when the optical disk 1 is, for example, a constant linear velocity (CLV) disk, the rotation period is maximum at the outermost periphery, so the storage capacity for one track (one rotation) at the outermost periphery, that is, (the outermost rotation) (Cycle) × (data transfer rate from the ECC circuit 6 to the ring buffer memory 5).

  The maximum data transfer rate from the ring buffer memory 5 to the video code buffer memory 10 is set to be equal to or smaller than the data transfer rate from the ECC circuit 6 to the ring buffer memory 5. In this way, a code request for data transfer from the video code buffer memory 10 to the ring buffer memory 5 can be freely sent regardless of the track jump timing.

  As described above, according to this optical disk apparatus, since the pickup 2 is caused to track jump in accordance with the storage capacity of the ring buffer memory 5, regardless of the complexity or flatness of the reproduced image from the optical disk 1, An overflow or underflow of the video code buffer memory 10 is prevented, and an image with uniform image quality can be reproduced over a long period of time.

  Further, according to this optical disc apparatus, when an error occurs in the data read from the optical disc 1, the pickup 2 is caused to track jump and read the data from the optical disc 1 again. Can be prevented.

  By the way, the ECC circuit 6 in the optical disc apparatus of FIG. 19 is configured as shown in FIG. 20, for example. The data output from the demodulation circuit 3 (FIG. 19) is input to the ECC circuit 6 via the sector detection circuit 4, and temporarily stored in the buffer memory 41 (FIG. 20) in the input stage. The data stored in the buffer memory 41 is sequentially transferred to the memory 42 and stored according to the address generated by the address generator 43. The data stored in the memory 42 is read from there and transferred to the error correction circuit 44. The error correction circuit 44 performs error correction on the data transferred from the memory 42 and stores the error-corrected data in the memory 42 again.

  Here, writing and reading of data with respect to the memory 42 will be described with reference to the memory map of FIG. Circles in the figure indicate one symbol unit for error correction, usually one byte. Data is written to or read from the memory 42 in units of one data length in one horizontal row of the memory map shown in FIG. In addition, a parity bit (a hatched portion in the figure) is added at the end, and an oblique direction of the memory map (hereinafter referred to as an interleaving direction) (a direction indicated by a dotted arrow in the figure) The parity bit as the last part of the data sequence is a parity bit for correcting an error in the data arranged in the interleaving direction.

  That is, for example, in order to isolate a burst error, data and a parity bit for correcting the error of the data are arranged in the interleaving direction.

  Therefore, in the memory 42, first, the data from the buffer memory 41 is written in the address direction according to the address indicated by the write pointer wp1.

  Note that the address direction means a direction from left to right and from top to bottom in the memory map of FIG.

  The data already written in the memory 42 in accordance with the address indicated by the read pointer rp1 delayed by at least the storage capacity (address) necessary for reading the data in the interleave direction (hereinafter referred to as the interleave length) is The data is read in the interleave direction and supplied to the error correction circuit 44. In the error correction circuit 44, error correction processing is performed on the arrangement of data in the interleave direction as described above, and the error-corrected data is transferred to the memory 42.

  Data that has been error-corrected by the error correction circuit 44 is written again at the position (address) where it was first written according to the address indicated by the write pointer wp2, and according to the read pointer rp2 moving in the address direction, the buffer memory 45 (FIG. 20). ).

  By repeating this operation as one cycle, the error-corrected data is sequentially output from the buffer memory 45 to the ring buffer memory 5 (FIG. 19).

  Accordingly, the error-corrected data is once stored in the memory 42 (FIG. 20) and then stored in the ring buffer memory 5 again.

  As described above, in the conventional optical disk apparatus, a redundant operation of sequentially putting data in and out of two different memories (the memory 42 and the ring buffer memory 5) is performed, which only increases the scale of the apparatus. However, there is a problem that the data processing speed becomes slow.

Therefore, the present applicant has previously proposed correcting an error in data stored in the ring buffer memory 5 as Japanese Patent Application No. 4-285475.
Japanese Patent Laid-Open No. 5-161115 JP-A-6-111495

  However, the previous proposal has a problem that the correct sector address cannot be read and the optical disc 1 cannot be accessed accurately and quickly.

  Furthermore, there is a problem that when data read from the optical disc 1 has a large error and cannot be corrected, it cannot be corrected again.

  In addition, it takes time for deinterleaving, and there is a problem that high-speed playback operation during special playback such as fast forward and rewind is difficult.

  The present invention has been made in view of such circumstances, and is intended to enable quick access to a disk and to reproduce the disk at high speed.

  The present invention also improves error correction capability.

The data reproduction method of the present invention is a data reproduction method for reproducing recorded data recorded on a disk, and reads the recorded data from a disk on which recorded data including two systems of error correction codes is recorded. The read data is demodulated, the demodulated data is input to the memory and the error correction circuit, the data input to the memory is stored, and the data input to the error correction circuit is Error correction using two error correction codes, and error correction using one of the two error correction codes during special playback can correct errors in data input to the error correction circuit. If there is, supply the corrected value to the memory, overwrite the value stored in the memory, and decode the data read from the memory. Features.

The two error correction codes are a first error correction code added to data obtained by interleaving data recorded on the disk and a second error added to data not interleaved. by the correction code can be so constituted.

Error correction codes of two systems is calculated contains a sector header may be adapted to detect a sector address from the sector header of the data error correction.

  A valid period and an invalid period are set based on the continuity of valid sector addresses among the detected sector addresses, and when a valid sector address is not detected in the valid period, the sector address is interpolated. it can.

A data reproducing apparatus according to the present invention is a data reproducing apparatus for reproducing recorded data recorded on a disk, and reads out the recorded data from a disk on which recorded data including two systems of error correction codes is recorded. And a demodulating means for demodulating the data read by the reading means, an input means for inputting the data demodulated by the demodulating means to the memory and the error correction circuit, and data input to the memory by the input means are stored. The data input to the error correction circuit by the storage means and the input means is controlled so that error correction is performed using two error correction codes during normal reproduction, and two error correction codes are used during special reproduction. Error correction control means for controlling error correction by one of the systems, and data read from the memory The error correction control means supplies the corrected value to the memory and overwrites the value stored in the memory when the error of the input data can be corrected. It is characterized by controlling as follows.

The two error correction codes are a first error correction code added to data obtained by interleaving data recorded on the disk and a second error added to data not interleaved. by the correction code can be so constituted.

The two error correction codes are calculated including the sector header, and a sector address detecting means for detecting a sector address from the sector header of the error-corrected data can be further provided .

  A valid period and an invalid period are set based on the continuity of valid sector addresses among the detected sector addresses, and when a valid sector address is not detected in the valid period, means for interpolating the sector address is provided. can do.

In the data reproduction method and apparatus of the present invention, the recorded data is read from the disk on which the recorded data including the two systems of error correction codes is recorded, the read data is demodulated, and the demodulated data is The data input to the memory and the error correction circuit is stored, and the data input to the memory is stored, and the data input to the error correction circuit is subjected to error correction by two error correction codes during normal reproduction. During special reproduction, error correction is performed by one of the two error correction codes, and if the error of the data input to the error correction circuit can be corrected, the corrected value is stored in the memory. The value supplied and stored in the memory is overwritten, and the data read from the memory is decoded.

  According to the present invention, more reliable correction can be performed.

  In addition, according to the present invention, when special reproduction or sector address retrieval is performed, error correction can be performed using only one of the error correction codes, and faster reproduction and quick access can be achieved. Is possible.

  FIG. 1 is a block diagram showing the configuration of an embodiment of an optical disc apparatus to which the data reproducing method of the present invention is applied. In the figure, portions corresponding to those in FIG. 19 are denoted by the same reference numerals.

  Next, the optical disk apparatus will be described. Before that, the data format in the optical disk 1 reproduced by the optical disk apparatus will be described with reference to FIG.

  In FIG. 2, a circle indicates data of one symbol (1 byte). In the data, for example, one code (one row) is in units of 128 bytes, and a sector header is included for every 16 codes.

  As shown in FIG. 3, the sector header includes a sector mark indicating a sector header, a sector address incremented by 1 for each sector, and a cyclic code (CRC) for detecting an error in the sector header.

  As shown in FIG. 2, in the data in which one row is arranged every 128 bytes, a 16-byte error correction code is added as inner parity to the data read in an oblique direction (arrow A direction). In the figure, a circle indicated by adding a vertical line inside represents the inner parity. The inner parity is so-called convolution, and the parity is calculated without interruption from the beginning to the end of the data in the diagonal direction. The code of 144 (= 128 + 16) bytes in the oblique direction is referred to as an inner code.

  Next, the data is read in the horizontal direction (arrow B direction) for the line for which the calculation of the inner parity has been completed. Added as parity. In FIG. 2, a circle with a horizontal line represents an outer parity. The code of 160 (= 128 + 16 + 16) bytes in the horizontal direction is referred to as an outer code.

  These two types of parity (inner parity and outer parity) are calculated including the sector header, and errors generated in the sector header portion can be corrected by outer code correction or inner code correction.

  As shown in FIG. 2, a sync signal is added to the head of data of 160 bytes (data is 128 bytes, inner parity and outer parity is 32 bytes) in each row.

  The pickup 2 in FIG. 1 irradiates a laser beam onto the optical disc 1 on which image data is recorded in the above format, and reproduces, for example, image data recorded on the optical disc 1 from the reflected light. Data output from the pickup 2 is input to the demodulation circuit 3 and demodulated. The output of the pickup 2 is also input to the PLL circuit 9, and a clock is extracted. This clock is sent to the demodulation circuit 3 and the buffer memory 61. Data demodulated by the demodulation circuit 3 is input to the buffer memory 61. Data output from the buffer memory 61 is written into the ring buffer memory 5 under the control of the control circuit 74.

  The demodulation circuit 3 has a sync protection function. That is, in the normal reproduction state of the disc, syncs are obtained at equal intervals from the beginning of each code from the reproduction data, but when no syncs are obtained, sync interpolation is performed as shown in FIG. That is, since a sync is generated at a constant cycle, if no sync is detected at this cycle, a sync is generated and output in a pseudo manner. Since the circuits after the demodulating circuit 3 use a sync as one unit of operation, stable operation is possible by such sync interpolation.

  Further, the demodulation circuit 3 has a built-in conversion table (table), and performs demodulation by comparing the input data with the conversion table for each modulation unit. When a combination is found, an error flag is set for each symbol (flag is set to 1). Further, the lock state of the PLL is known from the clock supplied from the PLL circuit 9, and an error flag is set while the lock is released.

  Further, when the sync is interpolated and when the number of error flags in one code is larger than a predetermined number, error flags are set for all symbols of one code length. This error flag is sent to the buffer memory 61 together with the data.

  Next, data writing and reading with respect to the ring buffer memory 5 and the flag register 73 will be described.

  As the ring buffer memory 5, a static random access memory (SRAM) or a dynamic random access memory (DRAM) can be used. Unlike DRAM, SRAM can write or read data continuously at high speed without limitation, but is expensive.

  In contrast, DRAM is inexpensive, but so-called high-speed page mode must be used to write or read data at high speed. The page unit in the high-speed page mode is limited to, for example, 256 bytes, and when data is read or written beyond this, it is necessary to perform page switching. The shorter the number of page switching times, the faster the processing time. Therefore, in this apparatus, data is read and written in different directions depending on whether outer code correction (correction in the direction of arrow B in FIG. 2) or inner code correction (correction in the direction of arrow A in FIG. 2) is performed. Although it is necessary, in any case, the method of storing data in the ring buffer memory 5 is devised so that page switching is performed at equal intervals as much as possible and the number of times is reduced. .

The method for storing data in the ring buffer memory 5 will be described below. That is, the data on the format shown in FIG. 2 is represented by a matrix D (i, j) where the code number (row in FIG. 2) is i, the symbol number in the code is j from the head of the sync. . In this way, the i-th (i-th row) code is composed of 160 symbols from D (i, 0) to D (i, 159). The data string in the inner code direction (the direction of arrow A in FIG. 2) is expressed as follows.
D (i, 0), D (i + 1,1), D (i + 2,2),
..., D (i + 143, 143)

On the other hand, the address of the ring buffer memory 5 is represented as R (m, n) where m is the row address and n is the column address. n is a value of 0 or more and 159 or less. The row address and the column address each have 16 pages. Here, the data D (i, j) on the format of FIG. 2 is written to the ring buffer memory 5 at an address R (m, n) indicated by m and n obtained by the following equation. That is,
k = (15− (i mod 16)) + j
Anyway,
m = i
n = k when k <160
When k ≧ 160, n = k−160
It is said. However, the operator mod represents a remainder.

  FIG. 5 shows a state where the data D (i, j) is stored at the address R (m, n) of the ring buffer memory 5. In this case, the data order of the outer code and inner code starting from D (1, 0) is as shown in FIG. As is clear from FIG. 6, since the outer code is arranged in the horizontal direction and the inner code is arranged in the vertical direction, in each case, except for the first few symbols, every 16 symbols at equal intervals, A page change occurs. Therefore, by storing data in the ring buffer memory 5 in this manner, both the outer code and the inner code can be read and written at high speed by the high-speed page mode.

  Writing to and reading from the ring buffer memory 5 are performed at a rate several times the data rate input from the demodulation circuit 3 to the buffer memory 61, for example, 5 times. FIG. 7 shows the timing. One sync time in FIG. 7 is the same time (synchronization cycle) as the interval between syncs shown in FIG. 4, and the time for which 160-byte data for one code is input from the demodulation circuit 3 to the buffer memory 61. Corresponding to

  Xw in FIG. 7 indicates the timing (period) for writing the data for one sync temporarily stored in the buffer memory 61 into the ring buffer memory 5. Xc indicates the timing (period) for rewriting the error symbol and the outer code flag. Yr indicates the read timing (period) of the inner code data on the ring buffer memory 5. Yc indicates the timing (period) for rewriting the error symbol and the inner code flag. Zr indicates the timing (period) for reading the data on the ring buffer memory 5 to the video code buffer memory 10.

  FIG. 8 schematically shows the memory space of the ring buffer memory 5 with one code length as one horizontal row (in practice, data is shown on the DRAM as shown in FIGS. 5 and 6). Is stored). The write pointer of Xw is indicated by PXw. Each pointer moves in the upward direction in the figure.

  The ring buffer memory 5 is provided with one bit for each code for storing an outer code correction and a correction result flag for the inner code correction. The right end of FIG. 8 shows a correspondence with the data area. is there.

  9 and 10 show a configuration example of the flag register 73. FIG. In this embodiment, data input via the switch 81 is output from 144 consecutive registers via the switch 82. The output data is returned to 144 consecutive registers again via one register and the switch 81.

  Now, error correction is in progress, and the inner code correction in the direction of the arrow A in FIG. 8 including the symbol one lower than the outer code correction PYr for the PYr row shown in FIG. 8 has been completed. And At this time, the 144 registers of the flag register 73 are in a state in which the past outer code flags fi + 143, fi + 142,... Fi are stored as shown in FIG. . A process from when the flag register 73 is empty (that is, a state where error correction is started for the first time) to such a state will be described later. The operation from error correction until data is sent to the video code buffer will be described with reference to the timing chart of FIG.

  In the period Xw of FIG. 7, when one row of data indicated by the pointer PXw of FIG. 8 stored in the buffer memory 61 is written to the ring buffer memory 5, the control circuit 74 causes the switching contact piece 63, 64 is connected to the contact a side. The data output from the buffer memory 61 is written to the ring buffer memory 5, and at the same time, the error flag output from the buffer memory 61 is also transmitted through the switching contact 63 or 64 of the switch 62 at the same timing. Input to the correction circuit 71 (corresponding to the error correction circuit 44 in FIG. 20). In the period Xw, the error correction circuit 71 performs erasure correction on the data in the row indicated by the pointer PXw in FIG. 8 using the outer parity and the error flag. As a result of correction, an error symbol and its correction value are obtained.

  Next, in the period Xc of FIG. 7, the error correction circuit 71 supplies the corrected value to the ring buffer memory 5 and the flag register 73, and the ring buffer memory 5 corrects the corresponding error symbol. Is overwritten. Since the correction is performed, the outer code flag in FIG. 8 (in this case, the outer code flag fi + 144) is set to zero. If the number of errors is large and cannot be corrected, the data on the ring buffer memory 5 is not rewritten, and correction is impossible, so 1 is written in the outer code flag fi + 144.

  Next, in the period Yr in FIG. 7, the switching contacts 63 and 64 of the switch 62 are switched to the contact b, and the inner code correction is performed from the position indicated by the pointer PYr from the ring buffer memory 5 in the interleave direction (arrow in FIG. Data is read in the A direction (vertical direction in FIG. 6) and input to the error correction circuit 71. On the other hand, the outer sign flags fi + 143, fi + 142,..., Fi are sequentially read from the flag register 73 and used for correcting the inner code. The error correction circuit 71 performs error correction (erasure correction) of input data (inner code) using the input outer code flag and inner parity.

  At this time, the flag register 73 operates as follows. As shown in FIG. 10B, the outer code flag fi + 144 output from the error correction circuit 71 is stored in the leftmost register of the flag register 73 via the contact b of the switch 81. At the same time, the outer code flag fi + 143 stored in the rightmost register of the flag register 73 is output via the switch 82.

  Next, as shown in FIG. 10C, the switch 81 is switched to the contact a side, and the outer code flag fi + 144 is transferred to the right end of the 144 shift registers. At the same time, the outer code flags fi + 142,... Fi stored in each register are output via the switch 82. Thus, the flag register 73 can output the outer code flags fi + 143, fi + 142,... Fi for one inner code length. Out of the sign registers fi + 144, fi + 143, fi + 142,..., Fi + 1 are stored in 144 registers of the flag register 73. Thus, the flag register 73 always stores the latest outer code flag for one inner code length (144).

  The outer code flag is stored in the flag register 73 and supplied to the error correction circuit 71 in spite of being written in the empty area of the ring buffer memory 5 from different areas in the ring buffer memory 5. This is because the outer code flag cannot be read simultaneously for each symbol.

  Next, in the period Yc of FIG. 7, the corrected value is sent to the ring buffer memory 5 and overwritten with respect to the error symbol on the ring buffer memory 5 in the same manner as the correction of the outer code. If there are many errors that cannot be corrected, the data is not rewritten.

  Further, all of the inner code flags gi to gi + 143 are written in an empty area of the ring buffer memory 5 when the error is corrected, and when the error is impossible, 1 is written. However, nothing is written in the inner code flags gi to gi + 143 for those in which 1 has already been written in the past inner code correction.

  This operation will be described with reference to FIG. If only three inner codes indicated by the pointers PYr1, PYr2, and PYr3 are uncorrectable in FIG. 11, an inner code flag is written as shown in FIG. That is, the inner code flag indicates how far the uncorrectable inner code extends when viewed from the outer code direction.

  In this way, the data on the ring buffer memory 5 that has been subjected to error correction is finally read out to the video code buffer memory 10 of the decoding unit 20 in the period Zr of FIG. PZr in FIG. 8 is a read pointer in this case. Data is read in the forward direction (horizontal direction), but inner parity and outer parity are not necessary (since correction has already been completed), so they are skipped (not read). Further, as shown in FIG. 8, the logical product of an outer code flag fj and an inner code flag gj through an AND gate (not shown) with respect to PZr is a video code buffer memory as a code uncorrectable flag in the jth row. 10 is sent.

  A series of operations as described above are repeated according to the timing chart of FIG. 7, and data that has undergone outer code correction and inner code correction by the error correction circuit 71 is transferred to the video code buffer 10 via the ring buffer memory 5. Supplied.

  Here, the reason why the logical product of fj and gj is taken is that, for example, when a certain inner symbol becomes uncorrectable, as shown in FIG. 11, the inner code over the length of the inner code length in the diagonal direction (interleave direction). This is because a flag is set and an uncorrectable portion cannot be specified. By calculating the logical product of the outer code flag fj and the inner code flag gj, even if the inner code flag is set, if the outer code flag can be corrected, it can be determined that there is no error in the row j, and the correction is made. It becomes possible to set an uncorrectable flag more accurately for an impossible error part.

  As shown in FIG. 8, the difference between the pointers PYe and PZr is the remaining data amount in the ring buffer memory 5. Here, PYe represents the pointer of the latest data for which the inner code correction has been completed.

  If the uncorrectable flag is zero (if correction is performed correctly), the data sent from the ring buffer memory 5 to the video code buffer memory 10 is decoded by the decoding unit 20 in the same manner as in FIG. Decrypted). If the uncorrectable flag is 1, the code includes an error, so the subsequent video decoding circuit (inverse VLC circuit 11 to motion compensation circuit 15) stops decoding until this flag becomes zero, and the display 18 Repeatedly transmits image data that has already been decoded and stored in the frame memory 16 (thus becoming a still image), thereby preventing image distortion.

  Here, the operation until the flag register 73 changes from the empty state to the state shown in FIG. 10A will be described.

  It is assumed that the pointer PXw is at the position of the outer code flag fi (position of PYe) in FIG. When the outer code correction of this PYe row is completed, as shown in FIG. 9A, the switch 81 is switched to the contact b side, and 144 outer code flags fi are output from the error correction circuit 71. Are input to the leftmost register of the consecutive shift registers. The outer code flag fi of the leftmost shift register is sequentially shifted rightward from the 144 shift registers and transferred to the rightmost register.

  Next, the pointer PXw is moved up by one line in FIG. 8 (that is, the position one line above PYe). Then, the outer code correction of the code of the row is performed, and as shown in FIG. 9B, the outer code flag fi + 1 is inputted to the leftmost register of 144 consecutive shift registers. At this time, the outer code flag fi of the rightmost register of 144 consecutive shift registers is transferred to one register.

  Further, as shown in FIG. 9C, the switch 81 is switched to the contact a side, and the outer code flag fi + 1 is sequentially shifted rightward through the 144 shift registers and transferred to the rightmost register. At this time, since the switch 81 is switched to the contact a side, the outer code flag fi is input to the left end of 144 shift registers, sequentially shifted rightward, and transferred to the register immediately before the right end. Is done.

  Next, the pointer PXw is moved up by one line (that is, the position two lines above PYe). Then, the outer code correction of the code of the row is performed, and as shown in FIG. 9D, the switch 81 is switched to the contact b side, and the outer code flag fi + 2 is the left end of 144 consecutive shift registers. Is input to the register. At this time, the outer code flag fi + 1 of the rightmost register of 144 consecutive shift registers is transferred to one register. The outer code flag fi is transferred to the rightmost register of the shift register.

  Further, as shown in FIG. 9E, the switch 81 is switched to the contact a side, and the outer code flag fi + 2 is sequentially shifted rightward from the 144 shift registers and transferred to the rightmost register. . At this time, since the switch 81 is switched to the contact a side, the outer code flags fi + 1 and fi are sequentially input to the left end of the 144 shift registers, and further shifted to the right, and 2 from the right end. The data is transferred up to the previous and third registers.

  Next, as shown in FIG. 9F, the switch 81 is switched to the contact b side, and the same processing is repeated thereafter. Accordingly, the outer code flag is input to the flag register 73 at a rate of one for one sync. Note that, during the period from FIG. 9A to FIG. 9F and FIG. 10, the switch 82 is open, and the outer code flag is not output.

  As described above, when the pointer PXw reaches the position shown in FIG. 8, as shown in FIG. 10A, the 144 registers of the flag register 73 are stored in the outer code flags fi + 143, fi + 142. ,..., Fi is stored.

  By the way, if the memory space of the ring buffer memory 5 is represented by a circle as shown in FIG. 12, the pointers PXw, PYr, PZr rotate in the direction indicated by the arrows (counterclockwise) without overtaking each other. become. The distance between the pointers PXw and PYr is constant and never leaves. The ring buffer memory 5 reads out data in response to a request from the video code buffer memory 10 and supplies the data to the video code buffer memory 10. The data remaining amount shown in FIG.

  The control circuit 74 controls reading and writing of data with respect to the ring buffer memory 5, and the pointers PXw, PYr, and PZr are managed by the control circuit 74. The control circuit 74 also controls writing to and reading from the flag register 73.

  Next, sector address extraction will be described. As described above, the data output from the buffer memory 61 is supplied to the error correction circuit 71 via the switch 62 and is corrected there. The outer code corrected data is supplied to the sector detection circuit 72 together with the outer code flag. Sent. The sector detection circuit 72 searches a sector mark from the input data and detects a sector header. Then, error detection by CRC is performed. Further, the sector address is read from the sector header and stored (FIG. 3).

  The sector address is sent to the control circuit 74 when no error is detected by CRC error detection or when the outer code flag is zero even if an error is detected by CRC error detection.

  The sector address is extracted after the outer code correction, but the outer code is arranged in the same direction as the data arrangement on the optical disc 1, so that it is vulnerable to burst errors and cannot be corrected and cannot be obtained. There is. In addition, there is a possibility that erroneous correction occurs due to outer code correction. Therefore, a correct sector address is not always obtained for each sector. Therefore, the correctness of the sector address is monitored by a flywheel operation in the control circuit 74 described below.

  Next, the sector address flywheel operation will be described. The control circuit 74 monitors the sector address input from the sector detection circuit 72, and if the sector address can be detected at 16 code intervals (FIG. 2) and the value of the sector address is increased by 1, the sector address The address is valid. If the effective sector address continues for a preset number of sectors, for example, 3 sectors or more, the flywheel (flag) is turned on.

  When the flywheel is on, if the state where the sector address is not valid continues for a preset number of sectors, for example, 5 sectors or more, the flywheel is turned off. Such a state can occur, for example, when the pickup 2 flies to another track due to an impact or the like. In this case, an abnormality processing operation is performed. This will be described later.

  FIG. 13 shows the state of the flywheel. A indicates a valid sector address, and X indicates an invalid sector address. The subscript “A” indicates an address value. It is assumed that sector addresses are obtained from left to right. Since A23, A24, and A25 and the effective sector addresses are obtained continuously from A22, the flywheel is turned on. In addition, after A32, since the effective sector address was not obtained continuously for 5 sectors, the flywheel is turned off.

  When the flywheel is on, the last valid sector address is stored as the latest valid sector address while being constantly updated. In FIG. 13, A32 is the latest valid sector address.

  By turning the flywheel on and off in this way, it is monitored whether the sector address is obtained correctly. If there is an error in the data and the sector address cannot be obtained temporarily, the sector address is By interpolating as continuous from the value, stable data writing to the ring buffer memory 5 is possible.

  When reproduction of the optical disk 1 is started, the data output from the buffer memory 61 is not immediately written into the ring buffer memory 5. Only when the sector address is continuously detected in the control circuit 74 and the flywheel is turned on, the pointers PXw and PYr are sent to the ring buffer memory 5 to write and read the ring buffer memory 5, and the error correction circuit 71. The error correction of the inner code is started at (the correction of the outer code is always performed). This is the same when resuming writing after being interrupted, and writing to the ring buffer memory 5 is always performed with the flywheel on.

  Next, the track jump of the pickup 2 will be described. If the remaining amount of data in the ring buffer memory 5 exceeds the set value and there is a possibility of overflow, that is, if the pointer PXw may catch up with PZr in FIG. 12, the track jump from the control circuit 74 to the tracking servo circuit 8 A command is output. At this time, the writing and reading of the ring buffer memory 5 and the error correction operation of the inner code of the error correction circuit 71 are interrupted. Then, the flywheel is turned off, and the latest valid sector address, for example, A32 in FIG. 13 is stored.

  FIG. 14 shows a recording track of the optical disc 1. In this figure, the latest valid sector address A32 is positioned before the point P where the jump starts. When a jump is commanded, as shown in the figure, the pickup 2 (reproduction point) jumps from point P to point Q, starts reading the inner track, and the flywheel is turned on again. When the pickup 2 comes to the latest effective sector address A32 stored in the optical disk 1 once, the writing and reading of the ring buffer memory 5 and the error correction of the inner code of the error correction circuit 71 are resumed from there.

  FIG. 15A shows a state in which the sector address is detected when the pickup 2 comes to the point P again. Writing of data to the ring buffer memory 5 is resumed from the sector A32.

  Here, A32 may be an invalid sector. FIG. 15B shows an example of such a case. In this case, since the flywheel is on, interpolation is performed from the past address even if A32 is not detected. Then, the writing operation is resumed from the data after 16 codes of A31.

  By performing the above operation, continuous data can be continuously written in the ring buffer memory 5 even though the writing is interrupted by the track jump.

  The pointers PXw and PYr (PYe) are stopped by the track jump, but during that time, data is read in response to a request from the video code buffer memory 10, so that the pointer PZr advances counterclockwise in FIG. The amount is reduced and overflow can be prevented.

  Next, the abnormality processing operation will be described. For example, it is assumed that the pickup 2 causes an unintended track jump due to mechanical vibration (disturbance) or the like. At this time, since continuous sector addresses cannot be obtained, the flywheel is turned off, and the writing and reading of the ring buffer memory 5 and the error correction operation of the inner code of the error correction circuit 71 are interrupted. At this time, the control circuit 74 refers to the latest valid sector address, and moves the pickup 2 so as to read from, for example, 20 sectors before. By doing so, the flywheel is turned on again before the latest valid sector address, and writing can be resumed from the latest valid sector in the same manner.

  At this time, if there is a sufficient remaining amount of data, the remaining amount of data in the ring buffer memory 5 may become zero before the pickup 2 returns to the position where the unintended track jump occurred and resumes data reading. Absent. Accordingly, reading from the ring buffer memory 5 to the video code buffer memory 10 is not interrupted, and recovery can be performed without affecting the image decoding / playback.

  Next, processing when error correction is impossible occurs will be described. FIG. 16 shows each pointer on the ring buffer memory 5 as in FIG. Here, it is assumed that the portion represented by the point X after the point R cannot be corrected by the outer code correction and the inner code correction. The control circuit 74 stores the address of the head sector of the uncorrectable part. If the control circuit 74 determines that the error correction is possible, the correction proceeds to a point S after a certain distance, for example, 5 sectors, from the end of the uncorrectable portion.

  In addition, the control circuit 74 calculates a time obtained by adding the time required for one round of the disk to the time required to perform error correction from the point R to the point S. Then, this time is multiplied by the maximum data transfer rate from the ring buffer memory 5 to the video code buffer memory 10, and the maximum amount of data that can be lost by the ring buffer memory 5 is obtained within the time obtained by this multiplication. . Further, the data amount is compared with the remaining data amount on the ring buffer memory 5. If the remaining amount of data is larger, the pointer PZr cannot catch up with PYr, so it is determined that it can be corrected repeatedly.

  Here, the time for one round of the disk is obtained to a certain degree of accuracy from the position information of the pickup 2 in the radial direction of the disk. The possibility can be increased. That is, when the pickup 2 is near the outermost periphery of the disk 1, since one rotation cycle of the disk is long, the re-correction can not be performed unless a corresponding data remaining amount remains in the ring buffer memory 5. In the case of the inner circumference, the rotation period is short, and at least the remaining data amount can be corrected again.

  When it is determined that the correction can be repeated, the track jump is first performed to stop reading from the optical disc 1 and the switching contact pieces 63 and 64 of the switch 62 are switched to the contact b. As shown in FIG. 17, the pointers PXw and PYr are returned to point R, from which outer code correction and inner code correction are started again. When the correction is completed up to the point S, the pointer is stopped there, the contact pieces 63 and 64 of the switch 62 are switched to the contact a, and the writing after the point S is read from the optical disk 1 is resumed. The writing at this point S is resumed from the latest valid sector address as in the case of the track jump described above.

  Note that the error flag from the demodulation circuit 3 has already been lost. Therefore, when iterative correction is performed, there is no error flag to be referred to at the time of the second outer code correction, so normal correction (correction using only outer parity, not erasure correction) is performed. However, the outer code flag obtained by the second outer code correction is used for the erasure correction of the second inner code correction.

  By performing such control, the uncorrectable portion can be corrected again without interrupting reading from the ring buffer memory 5 to the video code buffer memory 10 (without affecting the image decoding / playback at all). It becomes possible. Further, as long as there is enough data remaining, the uncorrectable part can be repeatedly corrected any number of times, and the error correction capability can be improved.

  Next, the operation during special playback will be described. In special playback such as fast-forward and fast-rewind (rewind), for example, only I picture data on the optical disc 1 is sequentially read and played. At this time, since the inner code is interleaved, it is necessary to start reading from the front by the interleave length from the desired sector. Also, at the end of reading, it is necessary to read extra by the interleave length from the necessary last data. The time required for this deinterleaving is not a problem because data is continuously processed during normal reproduction, but high-speed reproduction is difficult in special reproduction that repeats the operation of reading desired data (I picture data) at high speed. It becomes a factor. That is, it becomes a factor of delaying the reproduction time.

  Therefore, at the time of special reproduction, the control circuit 74 controls the ring buffer memory 5, the error correction circuit 71, etc. so that only error correction by the outer code is performed and error correction by the inner code is not performed. During special reproduction, the switching pieces 63 and 64 of the switch 62 are always switched to the contact a side. As described above, the data output from the buffer memory 61 is sent to the ring buffer memory 5 and the error correction circuit 71 to be corrected by the outer code.

  During normal reproduction, data is read again from the ring buffer memory 5 and sent to the error correction circuit 71, where error correction is performed using an inner code. However, this is not performed during special reproduction. Data is sent to the video code buffer memory 10 as in normal playback. At this time, the read pointer PZr does not need to be after the pointer PYr, as shown in FIG. 8, and reading can be started immediately after the pointer PXw.

  As described above, since deinterleaving is not performed, data can be quickly sent from the ring buffer memory 5 to the video code buffer memory 10, and high-speed reproduction operation is possible. Since internal code correction is not performed, there is a slight disadvantage in terms of error correction capability. However, during special playback, even if the screen freezes temporarily (even if a still image is played back) due to the error correction being impossible, It doesn't stand out so much, and there is almost no practical use.

  The error correction code may be a complete product code instead of a convolutional code (inner code and outer code). FIG. 18 shows an example of a format when using a product code. In this embodiment, C1 parity is added to the horizontal data in the figure, and C2 parity is added to the vertical data. The present invention can also be applied to data in such a format by changing the write and read addresses for the ring buffer memory 5.

  The case where the data reproducing method of the present invention is applied to an optical disk apparatus has been described above. However, the present invention can be applied not only to an optical disk apparatus but also to, for example, a magneto-optical disk apparatus.

  Further, the present invention can be applied not only when reproducing moving image data but also when reproducing audio data or data obtained by multiplexing moving image data and audio data.

1 is a block diagram showing a configuration of an embodiment of an optical disc apparatus to which a data reproducing apparatus of the present invention is applied. It is a figure which shows the format of the data of the data reproduction apparatus of this invention. FIG. 3 is a diagram illustrating a configuration of a sector header of the data format of FIG. 2. It is the figure which showed a mode that a sync was interpolated by the demodulation circuit 3 of FIG. It is the figure which showed the state in which data are stored in the ring buffer memory 5 of FIG. It is a figure which shows the order which writes or reads data in the ring buffer memory 5 of FIG. It is a figure which shows the timing which writes and reads data in the ring buffer memory 5 of FIG. It is a figure which shows the outline of the memory space of the ring buffer memory 5 of FIG. It is a figure explaining operation | movement of the flag register 73 of FIG. It is a figure explaining operation | movement of the flag register 73 of FIG. It is a figure explaining the inner code flag written in the ring buffer memory. It is a figure explaining the pointer of writing and reading on the ring buffer memory 5 of FIG. It is a figure explaining the input sector address and ON / OFF of a flywheel. FIG. 6 is a diagram showing a locus on which the pickup 2 performs a track jump on the optical disc 1. It is a figure explaining the sector address when writing in the ring buffer memory 5 is resumed. It is a figure explaining the pointer of writing and reading on the ring buffer memory 5 of FIG. It is a figure explaining the pointer of writing and reading on the ring buffer memory 5 of FIG. It is a figure which shows the modification of the data format of the data reproduction apparatus of this invention. It is a block diagram which shows the structure of an example of the conventional optical disk apparatus. FIG. 20 is a block diagram showing a more detailed configuration of the ECC circuit 6 of the optical disc apparatus of FIG. 19. 21 is a memory map showing a memory space of the memory 42 of the ECC circuit 6 of FIG.

Explanation of symbols

  1 optical disk, 2 pickup, 3 demodulation circuit, 4 sector detection circuit, 5 ring buffer memory, 6 ECC circuit, 7 track jump determination circuit, 8 tracking servo circuit, 9 PLL circuit, 10 video code buffer memory, 11 reverse VLC circuit, 12 Inverse quantization circuit, 13 Inverse DCT circuit, 14 Addition circuit, 15 Motion compensation circuit, 16 Frame memory, 17 D / A conversion circuit, 18 Display, 20 Decoding unit, 31 Control circuit, 41 Buffer memory, 42 Memory, 43 Address generator, 44 error correction circuit, 45 buffer memory, 61 buffer memory, 62 switch, 63, 64 switching intercept, 71 error correction circuit, 72 sector detection circuit, 73 flag register, 74 control A road

Claims (8)

In a data reproduction method for reproducing recorded data recorded on a disc,
Reading the recording data from a disk on which recording data including two error correction codes is recorded,
Demodulate the read data,
The demodulated data is input to a memory and an error correction circuit,
The data input to the memory is stored, and the data input to the error correction circuit is subjected to error correction by the two error correction codes during normal reproduction, and during the special reproduction, the two systems. Perform error correction with one of the error correction codes,
If the error in the data input to the error correction circuit is correctable, supply the corrected value to the memory, overwriting the value stored in the memory,
A data reproduction method comprising: decoding data read from the memory. The two systems of error correction codes are a first error correction code added to data obtained by interleaving data recorded on the disc and a second error correction code added to data not interleaved. The data reproduction method according to claim 1, comprising: an error correction code of: The two error correction codes are calculated including a sector header,
2. The data reproduction method according to claim 1, wherein a sector address is detected from a sector header of the error-corrected data. Based on the continuity of valid sector addresses among the detected sector addresses, set valid period and invalid period,
The data reproducing method according to claim 3, wherein when the effective sector address is not detected in the effective period, the sector address is interpolated. In a data reproducing apparatus for reproducing recorded data recorded on a disc,
A reading means for reading the recording data from a disk on which recording data including two systems of error correction codes is recorded;
Demodulation means for demodulating data read by the reading means;
Input means for inputting data demodulated by the demodulation means to a memory and an error correction circuit;
Storage means for storing data input to the memory by the input means;
The data input to the error correction circuit by the input means is controlled to perform error correction using the two error correction codes during normal reproduction, and the two error correction codes are used during special reproduction. Error correction control means for controlling to perform error correction by any one of the systems;
Decoding means for decoding data read from the memory,
The error correction control means controls to supply the corrected value to the memory and overwrite the value stored in the memory when the error of the input data can be corrected. A featured data reproducing apparatus. The two systems of error correction codes are a first error correction code added to data obtained by interleaving data recorded on the disc and a second error correction code added to data not interleaved. The data reproducing apparatus according to claim 5, wherein the data reproducing apparatus comprises: The two error correction codes are calculated including a sector header,
The data reproducing apparatus according to claim 5, further comprising sector address detecting means for detecting a sector address from a sector header of the error-corrected data. Means for setting a valid period and an invalid period based on continuity of valid sector addresses among the detected sector addresses, and interpolating the sector address when the valid sector address is not detected in the valid period The data reproducing apparatus according to claim 7, wherein:

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