JP3301695B2 - Encoded signal decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a coded signal decoding device for decoding a coded signal of voice or image information.

[0002]

2. Description of the Related Art In recent years, transmission devices capable of more efficiently transmitting information by encoding information such as audio and images, and recording and reproducing devices capable of recording and reproducing the above information more efficiently have been developed. I have. For example, International Organization for Standardization (Internatio
For example, for a CD-ROM disc defined by the ISO 9660 standard by the International Standard Organization (hereinafter referred to as ISO), a video CD player uses the MPEG standard of ISO.
(MPEG, Moving Pictures Experts Group: Moving Picture Experts Group) Records and reproduces moving pictures and audio according to the encoding method specified by the standard ISO / IEC11172.

[0003] A moving picture or audio signal encoded according to the MPEG standard is formed by a frame-by-frame encoded signal comprising a synchronizing signal, encoded information and encoded data as shown in FIG. In FIG. 5, the synchronization signal is a bit string representing the head of a unit frame, and is used to extract the unit frame when decoding the encoded signal. Also, the encoded information is
It includes accompanying information relating to encoding processing necessary for decoding, such as the bit rate and sampling frequency of encoded data included in the frame.

In such a coded signal decoding apparatus, an input coded signal in frame units is subjected to error detection and correction processing, separation processing of video signals and audio signals, and the like. Data is not input to the processing unit at a constant rate, but is often input in bursts.
For this reason, a memory buffer is provided at the input stage of the decoding processing unit, and the input coded signal is temporarily stored in this memory buffer, and then input to the decoding processing unit at a predetermined transfer rate to obtain a desired audio signal And a video signal.

In order to realize such a function, a conventional coded signal decoding device has a configuration as shown in FIG. Here, the configuration and operation of the conventional encoded signal decoding device will be described more specifically with reference to FIGS.

In the conventional coded signal decoding device shown in FIG. 3, a memory 11 is a memory for storing an input coded signal of at least one frame. The first address generation unit 22 is a unit that generates a write address of the memory 11. The second address generation unit 23 is a unit that generates a read address of the memory 11.

[0007] The synchronization detecting means 20 is means for detecting a synchronization signal in the encoded signal read from the memory 11. The decoding means 24 is means for extracting encoded information and encoded data from the encoded signal in accordance with the output of the synchronization detecting means 20 and decoding the same.

FIG. 4 shows an address change (lines A and C) at the time of writing to the memory 11 and an address change (lines B and C) at the time of reading.
D). In FIG. 3, the encoded signal S
When the RD is input, the signal is stored in the memory 11. The storage address at that time is the first address generation means 2
2 generated. Wherein the first address generating means 22, as shown in the portion of the straight line A in FIG. 4, and stores the encoded signal in order from the head address A ₀ of the memory 11, stores up to the maximum capacity of the address A _n. Thereafter, as shown by the portion of the straight line C, the signal is stored again from the head address, and the write address is generated so that the memory 11 becomes a ring buffer.

The encoded signal SRD is input when the request signal RQD generated by the decoding means 24 is active (RQD = Hi), and when the memory 11 is full, the request signal RQ is
D becomes inactive (RQD = Lo).

The coded signals stored in the memory 11 as described above are sequentially read in accordance with the read address generated by the second address generating means 23. The synchronization signal in the read encoded signal is detected by the synchronization detection means 20.

The decoding means 24 extracts encoded information and encoded data from the encoded signal read out according to the synchronization signal of the synchronization detecting means 20, decodes the encoded data based on the encoded information, and outputs the decoded data. A signal DAD is generated. Decoding means 2
4 controls the second address generator so that the read address generated by the second address generator 23 is linked to the write address of the first address generator 22. Each time the decoding of the encoded signal is completed, the data of the predetermined frame stored in the memory 11 is transmitted to the request signal RQD.
Is output. Thus, it requests the memory 11 to replenish the encoded signal again. Since the amount of encoded data changes for each frame, the read processing time may be shortened as shown by a broken line D in FIG.

Here, the coded signal input to the coded signal decoding apparatus may be interrupted in the middle of a frame when the reproducing state of the reproducing apparatus is bad or when fast-forward reproduction is performed. Further, the interval between frames may be out of the predetermined range. In such a state, in the conventional coded signal decoding device, the synchronization detection means 20 manages the detection cycle of the synchronization signal in the coded signal read from the memory 11. If the synchronization state is abnormal, instead of reading out the encoded signal having the abnormal synchronization signal from the second address generation means 23, the second address generation means 23 reads the immediately preceding encoded signal having the effective synchronization signal. It was controlled to put it out.

As described above, the conventional coded signal decoding device sequentially stores the input coded signal in the ring buffer included in the memory 11, decodes the coded data while reading the coded signal, and controls the read address. Had gone.

[0014]

However, in the conventional configuration, the first address generating means 22 generates a cyclic address and the second address generating means 23 in order to form a ring buffer using the memory 11. Generates a read address linked to the cyclic address. In such a configuration, the input to the memory 11 is generally a burst input, whereas the output must be at a constant rate. For this reason, it has been difficult to determine the relationship between the input address and the output address at the system design stage, and there has been a problem that the generation control of the address becomes complicated.

When the reproducing state of the reproducing apparatus is abnormal, interpolation reproduction is performed by substituting the immediately preceding valid coded signal. For this reason, the memory 11 stores the valid coded signal and the latest coded signal. However, there is a problem that it is necessary to have a capacity capable of storing an encoded signal for at least two frames including the above.

An object of the present invention is to solve such a conventional problem, and a first object of the present invention is to provide a coded signal decoding device in which input / output address control of a memory constituting a ring buffer is simple. It is a second object of the present invention to provide an encoded signal decoding device capable of realizing interpolation processing at the time of abnormal reproduction with a smaller memory capacity and decoding a reproduced signal of high quality.

[0017]

According to a first aspect of the present invention, there is provided a synchronous signal for inputting an encoded signal to which a synchronous signal or encoded information is added in frame units, and detecting a synchronous signal in the encoded signal. Detecting means, a memory for storing the coded signal, first address generating means for updating a write address of the memory in accordance with an output of the synchronization detecting means, and a memory for storing the coded signal stored in the memory. A second address generating means for generating a read address, an encoded signal read by the second address generating means being inputted, the encoded signal being decoded to generate an output signal, and a code being transmitted to the memory. Generating a write request signal for storing the
Decoding means for controlling the generation of the write address in the first address generation means and the generation of the read address in the second address generation means in accordance with the output of the synchronization detection means ; Output of synchronization detection means
Identify the synchronization signal in the encoded signal by force
If the periodicity is abnormal, the coded signal is added to the memory.
The output of the request signal for charging is stopped, and the
The first address generation means and the second address generation means
Update of the generated address to be stored in the memory.
Characterized by decoding again valid past coded signals
It is assumed that.

The invention according to claim 2 of the present application provides a synchronizing signal or
Input coded signal with coded information added in frame units
And a synchronization detecting means for detecting a synchronization signal in the encoded signal.
Stage, a memory for storing the encoded signal, and the synchronization detection.
Update the write address of the memory according to the output of the output means
First address generation means for performing
Address for generating the read address of the encoded signal
Read by generating means and the second address generating means
The encoded signal is input, and the encoded signal is decoded and output.
Generate an input signal and store the encoded signal in the memory.
Generating a write request signal for storing the first address;
A write address and a second address in the dress generation means.
Detection of the generation of the read address by the
Decoding means for controlling according to the output of the means.
The recording / decoding means is provided in the encoded signal read from the memory.
Calculating the frame length of the encoded signal from the encoded information,
When the period of the synchronization signal is different from the calculated frame length
Is for detecting the synchronization with respect to the first address generating means.
Instruct the user to prohibit address updates in accordance with the output of the
It is characterized by showing.

The invention according to claim 3 of the present application provides a synchronizing signal and
Input coded signal with coded information added in frame units
And a synchronization detecting means for detecting a synchronization signal in the encoded signal.
Stage, a memory for storing the encoded signal, and the synchronization detection.
Update the write address of the memory according to the output of the output means
First address generation means for performing
Address for generating the read address of the encoded signal
Read by generating means and the second address generating means
The encoded signal is input, and the encoded signal is decoded and output.
Generate an input signal and store the encoded signal in the memory.
Generating a write request signal for storing the first address;
A write address and a second address in the dress generation means.
Detection of the generation of the read address by the
Decoding means for controlling according to the output of the means.
The recording / decoding means is provided in the encoded signal read from the memory.
Calculating the frame length of the encoded signal from the encoded information,
When the period of the synchronization signal is different from the calculated frame length
Is read from the memory by the second address generating means.
Attenuates the playback level of the coded signal and decodes it.
It is characterized by that.

[0020]

[0021]

[0022]

[0023]

According to the first aspect of the present invention, an output signal can be generated for an input having an abnormal synchronization state by using the coded signal stored in the memory until the synchronization is stabilized.

According to the second aspect of the present invention, the reliability of the synchronization detection can be confirmed by comparing the period of the detected synchronization signal with the frame length calculated from the coded information.

According to the third aspect of the present invention, when the synchronization state is abnormal, the signal level can be made less noticeable by attenuating the output level when the encoded signal is decoded.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An encoded signal decoding apparatus according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram illustrating a configuration of the encoded signal decoding device according to the present embodiment. FIG. 2 shows the data of the memory 11 as an address. Lines E, H, and I show the address change at the time of writing, and broken line G shows the address conversion at the time of reading. In FIG. 1, FIG. 3 shows that a memory 11, a first address generator 12 for generating a write address, a second address generator 13 for generating a read address, and a decoder 14 for an encoded signal are provided. Is the same as the conventional example. Unlike the conventional example, the capacity of the memory 11 is at least one frame, and the synchronization detecting means 10 is provided at the input of the encoded signal (SRD). The synchronization detecting means 10 is a means for detecting a synchronizing signal included in the encoded signal and providing the same to the first address generating means 12 and the decoding means 14. If it is difficult to determine the synchronization signal due to interruption of the input signal, only the determined signal is output.

The operation of the coded signal decoding apparatus according to the present embodiment configured as described above will be described. In FIG. 1, a coded signal input in a burst manner is temporarily stored in a memory 11. At this time, the synchronization detecting means 10 detects a synchronization signal in the encoded signal. The first address generation means 12 updates the write address according to the synchronization signal of the synchronization detection means 10. That is, when the input coded signal is in the asynchronous state, the write address is not updated. When a transition has been made from the asynchronous state to the synchronous state, the first address generation means 12 sequentially transmits the synchronization signal and the subsequent encoded information and encoded data from the head address E _{0 of the} memory as shown by a straight line E in FIG. Store.

While the synchronization state continues, FIG.
( ₁₎ until the memory 11 becomes full, that is, until the memory 11 becomes full. As shown by the broken line G in FIG. 2, the encoded signal stored in the memory 11 is read out at a constant bit rate based on the read address generated by the second address generating means 13, and is decoded by the decoding means 14. Is input to

The decryption means 14 is the second address generation means 1
After identifying whether the coded signal input based on the output of No. 3 is a synchronization signal, coded information, or coded data, decoding of the coded data is performed using them.

The decryption means 14 is the second address generation means 1
When it is identified that the encoded information for one frame stored in the memory 11 has been read out by the output of
outputs the request signal RQD from t ₂ requests input to supplement the coded signal to the memory 11.

[0032] If when the position of the synchronizing signal by the mismatch of the coded signal in the input is changed to the address E ₁ 2, may be shifted to data of the address E ₁ to E _n. That start address H ₀ of the first address generating unit 12 memory 11 as the output of the broken line F storage address E ₁ to E _n of the encoded signal is not read from the memory 11 in response to the decoding means 14 (= E ₀ ).

[0033] The next coding signal inputted according to the result of the request signal RQD is sequentially stored from time t ₃ to the address H ₁ and later. Request signal RQ output from decoding means 14
D stops writing when the write address by the first address generating unit 12 reaches the last address H _n of the memory indicated at time t _4.

As described above, when the encoded signal is stored in the memory 11 in the encoded signal decoding process of the present embodiment, the encoded signal is stored at the write address corresponding to the detection result of the synchronization signal.
The decoding means 14 can correctly identify whether the encoded signal read by the read address is a synchronization signal, encoded information, or encoded data.

Further, as an encoded signal decoding apparatus of the present invention ,
The second address generation means 13 has a function of storing the write address of the synchronization signal in the encoded signal. By shifting the coded signals stored in the memory 11 In this way, for example, to shift the synchronizing signal present in the address E ₁ to the address H ₀ (address E _0), the broken line a synchronizing signal detected by the address H ₂ I to address I ₀ . In this case, the synchronization signal is always stored in memory 1
1 is stored at the start address of the decryption unit 1
4 makes it easier to decode the encoded information and encoded data.

[0036]

As described above in detail, according to the present invention, when a coded signal input in a burst manner is stored in a memory, a write address is formed according to a synchronization signal in the coded signal. This can simplify generation and writing of a read address of an encoded signal necessary for decoding. Also, at the time of interpolation reproduction performed when the reproduction state is abnormal, since the encoded signal of the effective frame is stored from the head address of the memory, the read address can be easily updated. Therefore, the capacity of the memory for storing the encoded signal may be small, and an encoded signal decoding device with a small circuit scale can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an encoded signal decoding device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a change in a write address of a memory in the encoded signal decoding device of the present embodiment.

FIG. 3 is a block diagram illustrating a configuration of a conventional encoded signal decoding device.

FIG. 4 is an explanatory diagram showing a change in a write address of a memory in a conventional encoded signal decoding device.

FIG. 5 Frame-based signal arrangement used in MPEG
FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Synchronization detection means 11 Memory 12 Second address generation means 13 Second address generation means 14 Decoding means

Claims (3)

(57) [Claims] 1. A synchronization detection means for inputting an encoded signal to which a synchronization signal or encoded information is added in units of frames, detecting a synchronization signal in the encoded signal, and a memory for storing the encoded signal; A first address generation unit that updates a write address of the memory in accordance with an output of the synchronization detection unit; a second address generation unit that generates a read address of an encoded signal stored in the memory; The coded signal read by the second address generation means is input, and the coded signal is decoded to generate an output signal, and a write request signal for storing the coded signal in the memory is generated. Decoding means for controlling the generation of the write address in the first address generation means and the generation of the read address in the second address generation means in accordance with the output of the synchronization detection means. And Bei, said decoding means, synchronization signal in the coded signal by the output of said synchronization detecting means
Signal and encode it if the synchronization signal has abnormal periodicity
The output of a request signal for replenishing a signal to the memory is stopped.
And the first address generation means and the second
Controls the update of the generated address in the address generation means.
The previous valid coded signal stored in the memory
A coded signal decoding device characterized in that the coded signal is decoded. 2. Synchronization signals and coded information are frame by frame.
The added coded signal is input, and synchronization in the coded signal is performed.
Synchronization detection means for detecting a signal, a memory for storing the encoded signal, and a write address of the memory in response to an output of the synchronization detection means.
Address generating means for updating the address, and generating a read address of the encoded signal stored in the memory.
A second address generating means for forming the encoding read out by said second address generating means
Input a signal and decode the coded signal to generate an output signal
And storing the encoded signal in the memory.
Generating a write request signal;
Write address in the stage and the second address generating means
Generation of the read address in the output of the synchronization detecting means.
Anda decoding means for controlling in response, the decoding means, from the coded information in the coded signal read from the memory
Calculate the frame length of the encoded signal, and calculate the period of the synchronization signal.
And the calculated frame length is different, the first
The address generation means responds to the output of the synchronization detection means.
To prohibit the update of the address
A coded signal decoding device. 3. A synchronizing signal and encoded information are transmitted in units of frames.
The added coded signal is input, and synchronization in the coded signal is performed.
Synchronization detection means for detecting a signal, a memory for storing the encoded signal, and a write address of the memory in response to an output of the synchronization detection means.
Address generating means for updating the address, and generating a read address of the encoded signal stored in the memory.
A second address generating means for forming the encoding read out by said second address generating means
Input a signal and decode the coded signal to generate an output signal
And storing the encoded signal in the memory.
Generating a write request signal;
Write address in the stage and the second address generating means
Generation of the read address in the output of the synchronization detecting means.
Anda decoding means for controlling in response, the decoding means, from the coded information in the coded signal read from the memory
Calculate the frame length of the encoded signal, and calculate the period of the synchronization signal.
And the calculated frame length is different, the second
The encoded signal read from the memory by the address generation means
The feature is that the playback level is attenuated and decoded for the signal.
Encoded signal decoding device.