KR19990047650A - Liquid crystal display device having two or more shorting bars and manufacturing method thereof - Google Patents

Abstract

A vertical gate shorting bar for connecting a plurality of gate lines and a plurality of gate lines in a horizontal direction is formed on a transparent insulating substrate and a gate insulating film is formed over the gate lines and gate shorting bars on the whole. A plurality of data lines are formed in the vertical direction on the gate insulating film so as to intersect the gate lines, and a portion where the gate lines and the data lines cross each other is a pixel region. A first data shorting bar is formed on the gate insulating film to connect the data lines to each other outside the pixel region and the first auxiliary shorting bar is formed inside the gate shorting bar and is electrically connected to the odd gate lines, And a second auxiliary shorting bar electrically connected to the gate line is formed in parallel with the first auxiliary shorting bar.

Description

Liquid crystal display device having two or more shorting bars and manufacturing method thereof

The present invention relates to a liquid crystal display device having two or more shorting bars and a method of manufacturing the same. More particularly, the present invention relates to a liquid crystal display device having a shorting bar structure that is easy to detect for pixel defects and short defects, And a manufacturing method thereof.

Generally, the shorting bar discharges the static electricity generated during the process of the liquid crystal display device and is used for the inspection of the thin film transistor array after the process is completed.

Hereinafter, a liquid crystal display according to a related art will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic view showing a thin film transistor substrate for a liquid crystal display having a shorting bar according to a conventional technique, FIG. 2 is an enlarged view of part A of FIG. 1, and FIG. 3 is a cross- to be.

Gate lines G1, G2, G3, .... are formed on the substrate 1 in the lateral direction and gate pads 10 are formed at the ends of the gate lines G1, G2, G3, And the gate shorting bar 20 connects the gate lines G1, G2, G3, .... to the outside of the gate pad 10. [ Over the gate lines G1, G2, G3, ...., a gate insulating film 15 is covered. Data lines D1, D2, D3, D4, .... are formed in the vertical direction on the data lines D1, D2, D3, D4, And a data shorting bar 40 connects the data lines D1, D2, D3, D4, .... to the outside of the pad 30. [ At this time, the gate shorting bar 40 and the data shorting bar 20 are connected to each other by a resistor R.

In the screen display region of the liquid crystal display device, a portion where the data lines D1, D2, D3, D4, .... intersect with the gate lines G1, G2, G3, TFTs are formed in each of the pixel regions PX to receive scanning signals from the gate lines G1, G2, G3, D3, D4, ....) of the image signal.

The gate lines G1, G2 and G3 and the gate wiring 5 including the gate pad 10 and the gate shorting bar 20 are formed on the same surface on the substrate 1 as shown in Figs. 2 and 3, And is covered with a gate insulating film 15 and a protective film 25 thereon. The static electricity generated in the substrate during the manufacturing process of the liquid crystal display device is discharged through the gate shorting bar 20 and the gate shorting bar 20 is cut after the whole process with reference to the cutting line L. [

When a voltage Va for inspection of the array is applied to both ends of the shorting bars 20 and 40, the gate lines G1, G2, G3, .... and the data lines D1, D2, D3, D4,. ... are simultaneously applied with the same voltage Va, the thin film transistors TFT in the pixel region PX are simultaneously turned on. Accordingly, in the normally white mode, which is mainly used at present, the pixel region PX appears dark due to the voltage applied to the data lines D1, D2, D3, D4, .... However, in the pixel region PX (PX) in which there is a disconnection defect in the gate lines G1, G2, G3, or the data lines D1, D2, D3, D4, Is brightly displayed, it is possible to detect the failure of the pixel region PX.

However, when a short failure S1 in which two or more gate lines or two or more data lines D2 and D3 are connected to each other occurs, since the same voltage of Va is applied to the two data lines D2 and D3, No change due to defective S1 is detected. That is, the short defect S1 can not be detected using the structure formed by one gate shorting bar 20 and one data shorting bar 40. [

To compensate for this disadvantage, dividing the shot bar 40 into two or more pieces increases the detection force, but may lead to damage of the substrate due to static electricity during the process.

An object of the present invention is to realize a thin film transistor substrate having a shorting bar which is easy to detect a shorting defect and is not susceptible to static electricity.

FIG. 1 is a view showing a thin film transistor substrate for a liquid crystal display having a shorting bar structure according to a conventional technique,

2 is an enlarged plan view of portion A of Fig. 1,

3 is a sectional view taken along line III-III 'of FIG. 2,

4 is a view illustrating a thin film transistor substrate for a liquid crystal display having a shorting bar according to the present invention,

5A is a graph showing a voltage application state for an array inspection of the liquid crystal display device of FIG. 4,

5B is a graph showing a voltage fluctuation state when a short defect exists in the liquid crystal display device,

6 is an enlarged plan view of the portion B in Fig. 4,

Fig. 7 is another plan view showing an enlarged view of a portion B in Fig. 4,

8 is a sectional view taken along the line VIII-VIII 'in Fig. 7,

Fig. 9 is a plan view showing an enlarged view of a portion C in Fig. 4,

10 is a sectional view taken along the line X-X 'in Fig. 9,

11A to 11F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention, with the gate shorting bar as a center,

12A to 12F are cross-sectional views illustrating a manufacturing method of a liquid crystal display device according to the present invention, with reference to a data shorting bar in the order of the process.

In order to solve such a problem, a liquid crystal display substrate according to the present invention has a plurality of gate lines formed in parallel to each other, and a shorting bar for two testers alternately connecting gate lines is formed. In addition, a main shorting bar connecting all the gate lines is formed outside the shorting bar.

At this time, the gate line and the shorting bar for the tester may be connected by a conductive connection pattern, respectively.

A plurality of data lines are formed perpendicularly to the gate lines and three shorting bars for the tester may be alternately connected to three consecutive data lines which may be connected by a conductive connection pattern .

In addition, it is preferable that the outline of the shorting bar is connected to the main shorting bar and connected to the gate line.

In this method of manufacturing a liquid crystal display device, the conductive connection pattern is formed in the step of forming the transparent pixel electrode.

A part of the gate line and the data line inside the main shorting bar can be removed after the transparent conductive connection pattern is formed.

In the liquid crystal display substrate and the manufacturing method thereof, the gate assisted shorting bars or the data assisted shorting bars are formed in two or more, respectively, and separated from the gate shorting bar and data shorting bar after the completion of the process, Defect detection is also easy.

Hereinafter, a liquid crystal display substrate and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can readily carry out the present invention.

First, a liquid crystal display substrate and a manufacturing method thereof will be outlined with reference to FIG.

FIG. 4 is a schematic view showing wirings in a thin film transistor substrate for a liquid crystal display having a shorting bar according to an embodiment of the present invention. The wirings of the liquid crystal display device in a state in which the anti- .

Gate electrodes G1, G2, G3, G4, ... are formed in the lateral direction and gate pads 110, 120, 130, ... are formed at the ends of the gate lines G1, G2, G3, G4, 140, ... are formed. The data lines D1, D2, D3, D4, .... are formed in the vertical direction with the gate lines G1, G2, G3, G4, .... and the insulating film And data pads 510, 520, 530, 540, ... are formed at one ends of the data lines D1, D2, D3, D4,.

The data lines D1, D2, D3, and D4 are disposed in the screen display region A inside the gate pads 110, 120, 130, 140, ... and the data pads 510, 520, 530, 540, The pixel region PX is formed by the portion where the gate lines G1, G2, G3, G4, .... cross each other, (TFTs) are formed one by one to receive image signals from the data lines D1, D2, D3, D4, .... by receiving scan signals from the gate lines G1, G2, G3, G4, And it plays a role of switching.

The static electricity generated in the wiring formation process causes defects in the thin film transistor TFT or the wirings G1, G2, ..., D1, D2, ... in the pixel region PX, And data shot bars 200 and 400 are formed as follows.

A longitudinal gate shorting bar 200 formed of metal for gate wiring outside the gate pads 110, 120, 130, 140, 102, 103, 104, ... extending from the gate extension portions 101, 102, 103, 104,. Outside the data pads 510, 520, 530, 540, ..., a data shorting bar 400 is formed in the lateral direction as a metal for the data interconnections. The data pads 510, 520, 530, 540, 502, 503, 504, ... extending from the data extension units 501, 502, 503, .... The gate shorting bar 200 and the data shorting bar 400 are connected to each other. Static electricity generated in the substrate is discharged by the shorting bars 200 and 400 having such a structure.

These gate and data shorting bars 200, 400 are cut along the cutting line L1 after all wiring processes of the substrate have been completed, thereby removing the antistatic pattern.

Thereafter, an array inspection is performed in the image display area of the substrate.

420, 210, 220, and 230 formed inside the gate and data shorting bars 200 and 400. The auxiliary lines 410 and 420, 230) is as follows.

Two auxiliary lines 410 and 420 are formed between the gate shorting bar 200 and the gate pads 110, 120, 130, 140, ... as a metal for data wiring such as Cr and molybdenum And three auxiliary lines 210, 220 and 230 are formed between the data shorting bar 400 and the data pads 510, 520, 530, 540, (Al), and is formed in parallel with the data shorting bar 400. At this time, the gate lines G1, G2, G3, G4, ... are alternately connected to the two auxiliary lines 410, 420, that is, the first and second auxiliary lines, which are formed in parallel with the gate shorting bar 200 The data lines D1, D2, D3 and D4 are connected to the three auxiliary lines 210, 220 and 230, that is, the third, fourth and fifth auxiliary lines, which are connected in parallel to the data shorting bar 400, , ...) are alternately connected.

Therefore, different signals are applied to the even-numbered gate lines G2, G4, ... and the odd-numbered gate lines G1, G3, ... using the first and second auxiliary lines 410, And the data lines D1, D2, D3, D4, .... are divided and applied to the R, G, and B signals by using the third, fourth, and fifth auxiliary lines 210, 220, and 230 , The defects in the substrate can be more accurately inspected.

The principle of inspecting defects in the substrate will be described with reference to FIGS. 5A and 5B. FIG.

FIG. 5A is a graph showing a gate voltage application state for an array inspection of a liquid crystal display device, and FIG. 5B is a graph showing a variation in a gate voltage when a short defect exists between gate lines in the liquid crystal display device.

Figure 5a, as shown, the odd-numbered gate lines (G1, G3, ...) and even-numbered gate lines (G2, G4, ...), each common voltage V such that the variation around the V _com to _{odd, Apply} a voltage of V _even .

5B, when a short circuit S2 is present between the two gate lines G2 and G3, the voltage V _even applied to the second gate line G2 transitions in an increasing direction, and the third voltage V is applied to the _odd gate lines (G3) is transferred to the reduction direction that converges to the V _com.

Therefore, the potential difference is detected as 0 between the two gate lines G2 and G3 where the short circuit S2 is generated.

The same also applies to the case of the data line. Third, fourth and fifth auxiliary lines to the data lines alternately connected to each other. When there is a short circuit S3 between the data lines D2, D3 and D4, the potential difference is not detected between the data lines D2, D3 and D4 where the applied voltage converges to a certain value and the short circuit S3 occurs .

After the array inspection of the substrate is completed, the substrate defect inspection pattern is removed by cutting the substrate along the cutting line L2 inside the auxiliary lines 410, 420 (210, 220, 230).

Thus, the driving substrate for a liquid crystal display device is completed.

6 to 10, the gate shorting bar 200, the first and second auxiliary lines 410 and 420, the data shorting bar 400 and the third, fourth and fifth auxiliary lines 210 , 220 and 230 will be described in more detail.

6 and 7 are enlarged views of the portion B of FIG. 4, that is, the gate shorting bar portion according to the first and second embodiments, FIG. 8 is a cross-sectional view taken along line VIII-VIII ' And a connection line between the bar and the auxiliary line.

Gate pads 110, 120, 130, ... are formed on a substrate 1 and gate extension parts 101, 102, 103, 200). A gate insulating film 150 is formed on the gate insulating film 150. The first and second auxiliary lines 410 and 420 are formed on the gate insulating film 150 in parallel with the gate shorting bar 200 to form gate pads 100, 110, 120,. .., and a gate shorting bar 200, and a protective film 250 is formed thereon.

A connection pattern (not shown) formed of a material such as a transparent pixel electrode (not shown) is formed on an upper portion of the portion where the gate extension portions 101, 103, ... overlap the first auxiliary line 210 or the second auxiliary line 220. [ (310, 320) are formed. The connection patterns 310 and 320 are formed in the opening part a in the protective film 250 above the first auxiliary line 210, the gate insulating film 150 in the upper part of the gate extension part 101, c and the gate extension part 102 which are in contact with the first extension line 210 and the gate extension part 101 through the first extension line b and through the protection layer 250 above the second extension line 220, The second auxiliary line 220 and the gate extension portion 102 are in contact with each other through the opening d opened in the gate insulating film 150 and the protective film 250 on the upper side. That is, the respective gate extension portions 101 and 102 are electrically connected to the first and second auxiliary lines 210 and 220, respectively.

As described above, the gate shorting bar 200 is removed from inside the gate shorting bar 200 along the cutting line L1 before the array inspection is performed, and after the inspection, the gate pads 110, 120, The cutting line L2 located on the outer side of the substrate is cut off, thereby completing the manufacture of the substrate.

The second embodiment shown in FIG. 7 is a structure that does not require a step of removing the gate shorting bar 200.

In the second embodiment, the connecting shapes of the first and second auxiliary lines 410 and 420 and the gate connecting portions 101, 102, 103, ... are the same as those of the first embodiment, The gate extension portions 101, 102, 103, ... between the first auxiliary lines 410 and the first auxiliary lines 410 and the gate insulating layer 150 and the protective layer 250 are removed, 103, ... are separated from the gate shorting bar 200. At this time, the gate extension portions 101, 102, 103, ... and the gate shorting bar 200 are separated at the end during the manufacturing process of the substrate, which will be described later in detail.

As described above, in the second embodiment, since the gate shorting bar 200 and the auxiliary lines 410 and 420 are separated from each other, there is no need to cut off the gate shorting bar 200 before the array inspection.

When the inspection is completed, the auxiliary lines 410 and 420 are cut along the cutting line L2 in the same manner as in the preceding embodiments.

FIG. 9 is an enlarged view of a portion C of FIG. 4, that is, a data shorting bar portion, FIG. 10 is a sectional view taken along the line XX 'of FIG. 9 and shows a connection form of a data shorting bar and third, fourth, Fig.

Third, fourth and fifth auxiliary lines 210, 220 and 230 are formed on the substrate 1 in the lateral direction with the same metal as the gate line and the gate insulating layer 150 is stacked thereon. Data lines D1, D2, D3, D4, ..., data pads 510, 520, 530, 540, ..., and data pads 510, 520, 530, 540, ... are formed on the gate insulating layer 150. Data extension portions 501, 502, 503, 504, ... extending from the data buses 400, ... and a data shining bar 400 connected thereto are formed. And a protective film 250 is formed thereon.

(F, h, j) are formed in the protective film 250 above the data extensions 501, 502, 503, .... which intersect the third, fourth and fifth auxiliary wires 210, 220, G and g are formed in the gate insulating film 150 and the protective insulating film 250 on the third, fourth and fifth auxiliary lines 210, 220, 230, i, k are respectively formed. The connection patterns 301, 302 and 303 formed on the protective film 250 are connected to the third, fourth and fifth auxiliary lines 210 and 220 through the openings f, h, j; , 230 and the data extension units 501, 502, 503, ... are alternately connected.

In addition, as in the case of the gate shorting bar 200, the data extensions 501, 502, 503, ... and the opening 1 in which the protective film 250 is partially opened are formed inside the data shorting bar 400 So that the data extender 501, 502, 503, 504, ... may be separate from the data shooter bar 400, in which case the data shooter bar 400 need not be cut off for array testing.

The data extension units 501, 502, 503, ... connected to the data lines D1, D2, D3, ... are alternately connected to the three auxiliary lines 210, 220, Therefore, different signals can be applied to the third, fourth, and fifth auxiliary lines 210, 220, and 230 to inspect the pixel defects and short defects of the thin film transistor substrate.

When a different signal is applied to each of the data lines D2, D3 and D4 when a short circuit (S3) defect occurs in the two or more data lines D2, D3 and D4, Is easily detected.

In this embodiment, three separate auxiliary lines 210, 220 and 230 are provided, but it is also possible to form two or more auxiliary auxiliary shorting bars.

Hereinafter, a method of manufacturing a liquid crystal display device having a shorting bar structure according to an embodiment of the present invention will be described with reference to FIGS. 11A to 11F and FIGS. 12A to 12F.

Figs. 11A to 11F are cross-sectional views taken along line VIII-VIII 'of Fig. 7, and Figs. 12A to 12F are cross-sectional views taken along a line X-X' of Fig.

A metal layer 50 for gate wiring is formed on a transparent insulating substrate 1 and gate lines G1, G2, G3, G4, ..., gate pads 100, 110, 120, The gate wiring 50 including the bar 200, the gate extension portions 101, 102, 103, ..., and the first, second and third auxiliary lines 210, 220, 230 and the like is patterned A gate insulating film 150, an amorphous silicon film (not shown) and an n ⁺ amorphous silicon film (not shown) are successively laminated, and the two layers are photo-etched to form a pattern in the pixel PX.

Next, a metal layer 55 for a data line is formed and the data lines D1, D2, D3, D4, ..., and source-drain electrodes (not shown), the data pads 500, 510, 520, 530, ..., a data shorting bar 400, data extensions 501, 502, 503, 504, ..., and first and second gate assisted shorting bars 410, 55 are patterned. Then, the n ⁺ amorphous silicon film is etched using the data line 55 as a mask.

A protective film 250 is formed thereon and then etched together with the gate insulating film 150 to form contact holes for exposing gate pads 110, 120, ..., data pads 510, 520, 530, and the first to fifth auxiliary lines 410, 410, 210, 220, 230, gate and data extensions 101, 102, ..., 501, 502, 503, (a, b, c, d, e, f, g, h, i, j, k).

Thereafter, the ITO material is stacked and etched to form a pixel electrode (not shown) in the pixel region PX. In this process, the ITO connection patterns 310, 320, 301, 302, and 303 are also formed. The ITO connection patterns 310 and 320 are connected to the first auxiliary line 410 and the second auxiliary line 420 and the gate extension portions 101, 102, ... by contact holes a, b, c, And the other connection patterns 301, 302 and 303 are connected to the third, fourth and fifth auxiliary lines 210, 220 and 230 through the contact holes f, g, h, i, The data extension units 501, 504, 502, ... are alternately connected.

Finally, the gate shorting bar 200 and the gate extensions 101, 102, 103, ... are separated from the first auxiliary line 410 and the gate shorting bar 200, And the data extension part 501, 502, 503, ... are separated from the third auxiliary line 210 and the data shorting bar 400.

As described above, in the etching process of the protection film 250, the gate extension portions 101, 102, 103, ... located between the first auxiliary line 410 and the gate shorting bar 200, The step of exposing the data extension portions 501 located between the auxiliary line 210 and the data shot bar 400 and forming the connection patterns 301, 302, 303, 310, The gate extension portions 101, 102, 103, ... and the data extension portions 101, 102, 103, ... which are exposed after that are etched and removed. The gate shorting bar 200 and the data shorting bar 400 are cut along the cut line L1 after the connection patterns 301, 302, 303, 310 and 320 are formed, It is also possible to separate them.

As described above, by forming two or more gate assisted shorting bars or data assisted shorting bars respectively, and separating them from the gate shorting bar and data shorting bar after the process is completed, it is also easy to detect short failure in the substrate without being susceptible to static electricity .

Claims (31)

A plurality of first wires parallel to each other, A plurality of second wires formed in parallel with the first wires, A first shorting bar connected to the first wiring, A second shorting bar connected to the second wiring, And a second shorting bar formed outside the first and second shorting bars, And the liquid crystal display substrate. The method of claim 1, Wherein the first and second wirings are gate lines to which a scanning signal is applied. The method of claim 1, Wherein the first and second wirings are data lines to which image signals are applied. The method of claim 1, And the main shorting bar is connected to the first and second wirings. The method of claim 1, Wherein the first and second wirings are alternately arranged. Transparent insulating substrate, A plurality of gate lines formed in the horizontal direction on the substrate, A gate insulating film covering the gate line and having a first opening exposing the gate line, A plurality of data lines formed in the vertical direction on the gate insulating film so as to cross the gate lines, A first auxiliary shorting bar formed in the longitudinal direction on the gate insulating film, A second auxiliary shorting bar formed on the gate insulating film in parallel with the first auxiliary shorting bar, A protective film formed on the data line and the first and second auxiliary shorting bars, the protective film having a second opening on the first opening and having third and fourth openings respectively on the first and second auxiliary shorting bars, A first connection pattern formed on the protection film and connected to the gate line and the first auxiliary shorting bar via the first and second openings and the third opening, And a second connection pattern formed on the protection film and connected to the gate line and the second auxiliary shorting bar which are not connected to the first connection pattern through the first and second openings and the fourth opening, And the liquid crystal display substrate. The method of claim 6, Third, fourth, and fifth auxiliary shorting bars formed on the substrate in parallel to each other in the lateral direction, and third, fourth, and fifth connection patterns formed on the protective film, And the fourth and fifth connection patterns electrically connect the data lines and the third, fourth, and fifth auxiliary shorting bars, respectively. 8. The method of claim 7, Wherein the protective film has sixth, seventh and eighth openings for exposing the data line, the gate insulating film and the protective film exposing the third, fourth and fifth auxiliary shorting bars, respectively, and the third, Fourth and fifth auxiliary shorting bars are connected to different data lines through the fifth opening and connected to the third, fourth and fifth auxiliary shorting bars through the sixth, seventh and eighth openings, respectively, Display substrate. The method of claim 6, And a gate shorting bar formed on the substrate and connected to the gate line. The method of claim 9, And a data shorting bar formed on the gate insulating film and connected to the data line. 11. The method of claim 10, And the data shorting bar is electrically connected to the gate shorting bar. The method of claim 6, And a gate shorting bar located outside the first and second auxiliary shorting bars and formed in a vertical direction on the substrate and separated from the gate line. The method of claim 12, And a data shorting bar located outside the third, fourth, and fifth auxiliary shorting bars and formed in a lateral direction on the gate insulating film and separated from the data line. The method of claim 13, And the data shorting bar is electrically connected to the gate shorting bar. Transparent insulating substrate, A plurality of gate lines formed in the horizontal direction on the substrate, A first auxiliary shorting bar formed on the substrate in a lateral direction, A second auxiliary shorting bar formed on the substrate in parallel with the first auxiliary shorting bar, A gate insulating film covering the gate line and the first and second auxiliary shorting bars and having first and second openings for respectively exposing the first and second auxiliary shorting bars, A plurality of data lines formed in the vertical direction on the gate insulating film so as to cross the gate lines, A protective film formed on the data line and the first and second auxiliary shorting bars, the protective film having third and fourth openings respectively on the first and second openings and having a fifth opening above the data line, A first connection pattern formed on the protective film and connected to the data line and the first auxiliary shorting bar via the first and third openings and the fifth opening, And a second connection pattern formed on the protection film and connected to the data line and the second auxiliary shorting bar which are not connected to the first connection pattern through the second and fourth openings and the fifth opening, And the liquid crystal display substrate. 16. The method of claim 15, And a gate shorting bar formed on the substrate and connected to the gate line. 17. The method of claim 16, And a data shorting bar formed on the gate insulating film and connected to the data line. The method of claim 17, And the data shorting bar is electrically connected to the gate shorting bar. 16. The method of claim 15, And a data shorting bar located outside the first and second auxiliary shorting bars and formed in a lateral direction on the gate insulating film and separated from the data line. 20. The method of claim 19, And a gate shorting bar formed on the substrate in a longitudinal direction and separated from the gate line. 20. The method of claim 20, And the gate shorting bar is electrically connected to the data shorting bar. Laminating a metal layer, Forming a gate line by patterning the metal layer, Forming a gate insulating film on the gate line, Forming first and second auxiliary shorting bar data lines for testing the gate line on the gate insulating film, Laminating a protective film, Etching the passivation layer and the gate insulator layer to form a first opening portion and a second and third opening portions respectively exposing the gate line and the first and second auxiliary shorting bars, Depositing a transparent conductive layer, Patterning the transparent conductive layer to connect the gate line and the first shorting bar via the first and second openings, and connecting the gate line and the second shorting bar through the first and third openings And a step of forming a pixel electrode Wherein the liquid crystal display substrate is a liquid crystal display substrate. The method of claim 22, And patterning the metal layer to form an electrostatic discharge shorting bar connected to the gate line. 24. The method of claim 23, Further comprising the step of removing the connection between the static eliminating shorting bar and the gate line after forming the connection pattern. Forming first, second and third auxiliary shorting bars for testing gate lines and data lines on the substrate, Forming a gate insulating film, Depositing a metal layer on the gate insulating film, Forming a data line by patterning the metal layer, Laminating a protective film, Forming a first opening and a second, third, and fourth openings that expose the data line and the first, second, and third auxiliary shorting bars by etching the protective film and the gate insulating film; Depositing a transparent conductive layer, Patterning the transparent conductive layer to form a connection pattern and a pixel electrode connected to the data line and the first through third auxiliary shorting bars through the first and second through fourth openings, Wherein the liquid crystal display substrate is a liquid crystal display substrate. 26. The method of claim 25, And forming an electrostatic discharge shorting bar connected to the data line by patterning the metal layer. 26. The method of claim 26, Further comprising the step of removing the connection between the static eliminating shorting bar and the data line after the step of forming the connection pattern. A plurality of gate lines and data lines on the substrate, a main shorting bar for preventing static electricity connected to the gate lines and the data lines, first and second auxiliary shorting bars for gate testing alternately connected to the gate lines, Forming a wiring such as a third and a fourth auxiliary shorting bar for data test connected thereto, Separating the main shorting bar from the gate and data lines, Applying a voltage to the first and second auxiliary shorting bars and the third and fourth auxiliary shorting bars to detect a failure of the data line and the gate line A method of manufacturing a liquid crystal display substrate 29. The method of claim 28, And applying different voltages to the first auxiliary shorting bar and the second auxiliary shorting bar. 29. The method of claim 28, And applying a different voltage to the third auxiliary shorting bar and the fourth auxiliary shorting bar. 29. The method of claim 28, And removing the first, second, third, and fourth auxiliary shorting bars after the failure detection step.