TW396370B - Liquid crystal displays, manufacturing methods and testing methods thereof - Google Patents

Abstract

A plurality of gate lines are formed on an insulating substrate in the horizontal direction, a gate shorting bar connected to the data lines is formed in the vertical direction and a gate insulating film is formed thereon. A plurality of data lines intersecting the gate lines are formed on the gate insulating film in the vertical direction, and a data shorting bar connected to the data lines is formed outside the display region. A first shorting bar is formed on the gate insulating film, located between the gate lines and the gate shorting bar, and connected to the odd gate lines. A second secondary shorting bar is formed parallel to the first shorting bar and connected to the even gate lines.

Description

V. Description of the invention (1) Background of the invention (a) The scope of the invention _ Law book: related to a liquid crystal display device (hereinafter referred to as LCD), its manufacturing method τ '^ test method, especially with two or less short circuit The method of using the shorting bar to test defects in the LCD. (b) Relevant technical description = day by day, the nuisance line is used to discharge the electrostatic charge during the manufacturing process of the liquid crystal display and test the liquid crystal display after the manufacturing method is completed. 0 Detailed description of the conventional liquid crystal display with reference to the drawings . Fig. 1 is a schematic diagram of a conventional thin-film electric body (hereinafter referred to as 1'15'1 ') substrate for a liquid crystal display having a shorting bar. Fig. 2 is an enlarged view of a section Λ in Fig. 1 3 is a cross-sectional view taken along line II-IIΓ in FIG. 2. As shown in Figs. 1 to 3, the gate lines G1, G2, G3, G4, ... are located on the substrate 1 and extend in the horizontal direction, and the gate pads 10 are located at one end of each gate line. The gate shorting strips that electrically connect the gate lines G1, G2, G3, and G4 are located on the substrate 1 and extend in a vertical direction. With respect to the gate pads, "" is located at the gate lines G1, G2, and G2. G3, G4, and two short-circuit strips 20 form a pair of test pads 2 at opposite ends. The opposite position. Covers the gate circuit 5 such as the gate lines G1, G2, G3, 4 at the idle gate insulation mold 15; ,,, gate pad 10 and gate shorting bar 20. Data lines…, D2, μ,), 4, are located on the gate insulation film 15 and extend in a vertical direction, and the data pad 30 is located at The five ends of each data line. The data shorting bar 4 that connects the data lines D1, D3 ,,), 4, and is electrically located at the gate insulation.

5. Description of the invention (2) The top two extend in the horizontal direction. A pair of test pads 3 & road strip 20 and data short strip 40 are formed at both ends of the data shorting bar 40, and can be connected to each other by a resistor. The insulating film 2 covers the material line including the data lines Dd 2, d 3, D4, the material pad 30 and the material short-circuit bar 40, and the insulation film 15 and 25 are located on the data pad 30 and the gate pad 10. The 7L area is defined as the area surrounded by two adjacent gate lines and two adjacent data lines: and the display area includes pixels in each pixel area to form a scanning signal from the gate line. Connected to transmit the image signal from the data line to the thin film transistor in the pixel area. In this structure, the static electricity generated during the manufacturing process is discharged or dispersed through the gate short-circuit bar 20 and the data short-circuit bar 40. In the meantime, after the manufacturing process and the completion of the array test, the substrate was cut without the L line to remove the gate shorting strips 20 and the data shorting strips 40. The mechanism of the conventional array test will be described with reference to FIGS. 1 and 4. Figure 4 shows the signal polarity applied to the array test in the pixel area. The voltage used for the array test is applied to the test pads 2 and 3. Because the gate lines, G2, G3, G4 ', and data lines ..., D2, D3 are individually connected to the short bars 20 and 40, so the pixel area The thin film transistors are connected at the same time, and a test signal is applied to all R, 0, and B pixels as shown in FIG. 4. Therefore, in the normal * white clay mode, the pixel area PX shows a dark state. The disc A data line or the gate line is interrupted or the thin film transistor has a defect. Then, the defective and related pixels become bright, and the defective element can be easily tested. However, if there are more than two gate lines or data lines (such as the fifth in Figure 1, the description of the invention (3) data lines D2 and D3) short-circuit (S1), because the voltage added here has the same magnitude and Polarity, ^ two shell material lines D2 and D3 are applied. It is difficult for the enemy to test the short circuit element. At the same time, if the short circuit bar is divided into equal or more wires or data lines to solve the aforementioned disadvantages, different gates of the connection may be damaged, and the protection ability against electrostatic charges will be reduced. a plus test capabilities. Summary of the Invention The object of the present invention is to provide a thin panel with a short panel, which is good at detecting short-circuit defects. Does not reduce the ability to resist static charges. Another object of the present invention is to provide a method for testing short-term determination between adjacent data lines or adjacent gate lines. Pixel defects. Some defects in high-resolution substrates. It can effectively detect that to achieve these purposes of the present invention, the line is formed to form two test short bars, and every other plurality of gates parallel to each other form a gate line connecting all the gate lines outside the short bar And individually connected. The closed-pole wires and short-circuit bars used for testing may be short-circuit bars. 1¾ go. ^ The conductive light-weight wiring pattern can form a plurality of data short-circuit bars that are perpendicular to the gate line, and can be individually connected to the data line sequence in sequence. In addition, it is expected that all the two gate lines and data lines will be joined by the main short-circuit bar. ; Shell material ^ 2 outside the road

Page 7 V. Description of the invention (4) In the method for manufacturing a liquid crystal display, a conductive braided wiring pattern is formed in the step of forming a transparent pixel electrode. ^ Question and data lines can be used to form conductive coupling wiring diagrams. Say, Wang Yao according to the invention of the LCD-road strips or other information is short :; ... system, to form other very short separation. It is for this reason that the crystal display: After completing this method, it will discharge static electricity with the main shorting bar. The soil plate is good at detecting short-circuit defects of the substrate and the two lines of polar lines and odd-numbered gate lines in the specific examples of the present invention, which are individually connected to even-numbered gates and individually connected to continuous R, and the test lines A gate pulse is applied and a data signal is applied on the road. For the three secondary test lines of one of the G and ^ pixels, the second of the two having the first polarity, when the pulse is applied to the even gate line, and the three adjacent ^ is applied to the three adjacent data Signals of two opposite polarities in a line. A signal with the first polarity applied to the remaining one of the three adjacent data lines is applied to a combination of the three adjacent data lines that is different from the first selection), and Polarity signal. The next one has the opposite to the first. In the test method of the present invention, the short-circuit defect is increased, and the visible increase can be described as measuring the pattern between adjacent pixels or adjacent lines. The test capability and credibility of the defect are simply explained. FIG. 1 is a schematic diagram of a substrate having a short-strip < (TFT) substrate; a thin film transistor of a liquid crystal display for driving; FIG. 2 is an enlarged configuration diagram of the eight-blade knife in Part A of FIG. 1;

Page 8 V. Description of the invention (5) Figure 3 is a cross-sectional view taken along the II-plate 'line in Figure 2; Figure 4 is a schematic diagram of a pixel matrix to which an array test signal is applied; Figure 5 is the present invention Schematic diagram of a thin-film transistor array panel for a liquid crystal display with a shorting bar; FIG. 6 is an enlarged configuration diagram of the first specific example of the present invention and part B in FIG. 5; FIG. 7 is a diagram of the second specific example of the present invention. Enlarged configuration diagram of part B in Fig. 5; Fig. 8 is a sectional view taken along the line M-VT of Fig. 7; Fig. 9 is an enlarged arrangement diagram of part C in Fig. 5; A cross-sectional view taken along the line X-X '; Figs. 11A to 11F are cross-sectional views of the liquid crystal display substrate according to the manufacturing method of Figs. 7 and 8; Figs. 1 A to 1 2 F are manufactured according to Figs. 9 and 10 A sectional view of a liquid crystal display substrate of the method; FIG. 13 is a schematic diagram illustrating a method of connecting a line and a shorting bar according to the present invention; and FIG. 14 illustrates a wave of an array test signal applied to a gate and a data line according to a first specific example Figures 1 5 A to 1 5 C illustrate application to R, G, B according to a first specific example The polarity of the element signal; Figure 16 illustrates the wave pattern of the array test signal applied to the gate and data lines according to the second specific example; Figures 17 A to 17 B illustrate the application to R, G, and Pixel B

5. Polarity of the signal of the invention. Array of data lines and array of data lines Figure 18 illustrates a waveform pattern applied to a gate test signal according to a third specific example. Fig. 19 illustrates a waveform of a test signal applied to a gate according to a fourth specific example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. However, the present invention may be embodied in many different forms and is not limited to the specific examples listed in the present invention. The invention is provided to complete the present disclosure and to fully transfer the scope of the present invention to those skilled in the art and In the figure, the thicknesses of the thin layers and regions are exaggerated for clear display. The same elements are denoted by the same numbers throughout the text. It is known that when a thin layer, region, or substrate is alleged to be on the "upper layer" of another element, it may be directly on the other element or an intermediate element may also be stored. The LCD monitor is described below with reference to FIG. 5 Its manufacturing method ... FIG. 5 is a schematic diagram of a thin film transistor array panel used in a liquid crystal display having a short-circuit bar according to a specific example of the present invention, in which the circuits of “electrostatic discharge protection and testing defects” have not been removed. The gate lines G1, G2, G3, G4 made of materials such as A1 extend in the horizontal direction, and on one end of each gate line and the gate = U 〇, 1 2 0, 1 3 〇, !! 4 〇 、、、。 The gate · 'made of Cr or M〇, and Yan 2 D 3 D 4 is located on the insulating film (not shown, covering the transition line). The data extends in the vertical direction, and the data pads 510, 5 2 0, 5 3 0 and 540 are located at the fifth end of the line.

Page 10 V. Description of Invention (7) Where: Ϊ 界定 is defined as two adjacent interpolar lines and two adjacent data lines

7: the & domain, and the display area includes the pixel area. In each pixel area, the shape of the :: mouth crystal, and when it comes from the gate line G1, G J, and the film transistor, the image signal from the data _ ,: the second ... is transmitted to the pixel. The electrostatic charge formed in the step of passing through the circuit can cause defects in the thin film transistor data circuit. In order to avoid these shortcomings, gate button bars and data short bars 2 0 and 400 are required. = Gate extension bar 200 extension made of the same material as the pole circuit *. , Located outside the display area, and connected to the gate extension lines 2, 103, 104 (they extend from the gate pads 110, 120, 13 and 14 in the horizontal direction). The material short made of the same material as the data line = strip 40 0 extends in the horizontal direction 'is located outside the display area and is connected to the extension lines 510, 520, 530, 540 (from the data pad 51, 52, 530 440 extends in the vertical direction). The gate short-circuit bar 200 and the data short-circuit bar 400 are connected to each other through a contact hole located in the insulation pad. The slabs 200 and 4 00 discharge and disperse static electricity generated in the substrate circuit during the manufacturing process, and are removed from the substrate by cutting the substrate along the cutting line L 丨. Second, perform an array test of the display area. Use auxiliary lines 41 0 and 4 2 0, 2 1 0, 2 2 0, and 2 3 0 for array testing. '' The first and second lines 410 and 420 made of data metals such as Cr and Mo are arranged on the gate shorting bar 20 () and the gate pads 11 (), 120, and 13.

Page 11 V. Description of the invention (8) and 140 'and a gate shorting bar 200 is parallel. The third, fourth, and fifth lines 21 0, 220, and 230 made of a gate metal such as A1 are arranged between the data short strip 400 and the data pads 510, 520, and 530, parallel to the data short strip 400. Manufactured from a gate metal such as A1. The first and second lines 41 0 and 420 are connected to the odd-numbered gate lines 61 and ⑵ and the even-numbered gate lines G2 and G4, respectively. The third, fourth and fifth auxiliary lines 21 〇, 22 〇, and 2 30 are respectively connected to the data line (3n-2), the data line (---), and (3n) Data line.疋 故 'can apply different signals to even and odd gate lines and apply r, G and b signals to (3n-2), ( 3n-1) and (3n) data lines to detect certain defects in the substrate. Now referring to FIGS. 6 to 10, the gate short-circuit bar 2000, the first and first auxiliary lines 410 and 42 0, the data short-circuit bar 400, and the third, fourth, and fifth lines will be described in detail. The structure of two auxiliary lines 2 1 0, 2 2 0 and 2 3 0. 6 and 7 are enlarged layout diagrams of part B in FIG. 5 according to the first and second specific examples of the present invention, and FIG. 8 is a cross-sectional view taken along the line of FIG. 7, wherein Shows the connection between the gate short-circuit bar and the auxiliary line. Gate extension line 1 〇 1 ,! 〇2 and 丨 〇3 From the gate pads 1 1 0, 1 2 0, and 1 3 0 on the substrate 丨 Yan Zhongman 4c 1 A to the vertically extending gate shorting bar on the substrate 1 to form the gate insulation The film 150 is on the gate insulating film 150 and the second auxiliary lines 41 ° and 42 °. Clauses-2 and 5 and 42 ° are located between the question pads 10 °, 110 and 120 and the question short circuit strip 200, and parallel to the gate short-circuit strip 200. Blunt

Page 12

Chemical film 25 0. Road ί: = ° Λ, where the Λ pole extension line overlaps the first or second auxiliary line, and the connecting elements 31 and 320 are made of the same material as the pixel electrode (not shown). The connecting element 31o is connected to the first auxiliary circuit 21o through a contact hole (a) located in the passivation medium 2 ^ 〇, and connected to the first auxiliary line 21o through a contact hole (b) located in the passivation film 250 and the gate insulating film 150 Ask the polar extension 101. The connecting element 3 20 is connected to the second auxiliary line 22 through a contact hole (c) in the passivation film 250, and is connected to the contact hole (d) through the passivation film 25 and the gate insulating film 150. Gate extension line 102. This means that the gate extension lines 101 and 102 are individually connected by the connecting elements 4 10 and 4200 "on the first and second auxiliary lines 2 10 and 22". As mentioned above, before the array test, the gate short-circuit bar is insulated from the auxiliary lines 41 and 42 by cutting the substrate along the cutting line L1, and after the array test, it is located along the display area by The outer L2 line is cut and the auxiliary lines 41 0 and 42 0 are cut. The second specific example shown in FIG. 7 has a structure in which an additional step of removing the gate shorting bar is not required before the array test. In the second specific example, the connection structure between the first and second auxiliary lines 41o and 420 and the gate extension lines 1101, 102, and 103 is the same as that in the first specific example. , But each gate extension line is separated from the gate short bar 2 0 'to remove the gate extension line 1 01! 〇 2 and 1 〇 3. The gate insulating film 150 and the passivation film 250 are located between the gate short-circuit bar 200 and the first auxiliary line 4 1 〇. The gate extension lines 101, 102, and 103 are separated from the gate short-circuit bar 200 in the final manufacturing step, and are described in detail below.

Page 13 V. Description of the invention (10) In the second specific example, the step of cutting the substrate before the array test is not required 'because the gate shorting bar 200 and the auxiliary lines 410 and 420 are separated from each other. The knife or the first specific example, after the test, cuts the substrate along the cutting line L2, and simultaneously removes the auxiliary lines 41 and 420. Fig. 9 is an enlarged configuration diagram of part C in Fig. 5, and Fig. 〇 is a cross-sectional view taken along the line X-X in Fig. 9, which particularly shows that the short-circuit bar of the data is relative to the third, fourth, and third sections. Contact point for five auxiliary lines. As shown in FIGS. 9 and 10, the third 210, the fourth 220, and the fifth 2 3 0 auxiliary lines made of the same metal as the gate line are located in the horizontal direction of the substrate 1, and the gate The insulating film 150 is deposited on the upper layer. Data line 55 (including data lines D1, D2, D3, and D4), data lines 510, 520, 530, and 5 40, data extension lines 5 (n, 502, 503, and 504) and connections extending from the data pad The data shorting bar 400 on the data extension line is located on the gate insulating film 150. A passivation film 25 is formed on the upper layer. The passivation film 2 50 is located on each of the data extension lines 501, 50, and 5. The contact holes F, Η, and J are formed on the part 〇3, and the third, fourth, and fifth auxiliary lines 21, 220, and 2 30 are located in the passivation film 25 and the gate insulating layer 150. A contact hole G is formed on the upper part. The connection elements 301, 302, and 303 located on the upper layer of the passivation film 250 are individually connected to the third, fourth, and third via the contact holes f, h, J, G, I, and K. Five auxiliary lines 2, 0, 220, and 230 are connected to the third data extension lines 5101, 502, and 503, which are separated by one at a time. In addition, 'remove the data short-circuit bar 4 00 and data 5101'. , 5 2 0, 5 3 0

Page 14

And 540 "between the passivation film 250 and the data extension lines 501, 502, and 503, that is, the shell material extension lines 501, 502, and 503 are detached from the data short-circuit bar 400. As a result, the array test does not require the additional step of cutting the data short strip 400. As mentioned above, three other signals can be applied to the third, fourth and fifth auxiliary lines 2 10, 2 2 0 and 2 3 0 to detect the pixels of the thin film transistor array panel. Defects and short-circuit defects because each of the three auxiliary lines 210, 220, and 230 is connected to a third material extension line that is separated by one at a time. 'If two or more of the data lines D3 and]) 4 are short-circuited as shown in Figure 5, if different signals are applied to the data lines D2 and D3, they can be easily detected by the difference in brightness between them and other pixels. Measure short circuit defects. Although in this specific example there are three separate auxiliary lines 2o0, 220, and 230 ', two or more auxiliary lines may be formed. Next, a method of manufacturing a liquid crystal display according to a specific example of the present invention will be described below with reference to FIGS. 1A to 1F and FIGS. 12A to 12F. 11A to 11F are sectional views of the intermediate structure of the liquid crystal display panel shown in FIGS. 7 and 8, and FIGS. 12A to 12F are sectional views of the intermediate structure of the liquid crystal display panel shown in FIGS. 9 and 10. Illustration. As shown in FIGS. 11A and 12A, a metal layer is deposited on the insulating substrate 1, and a wiring pattern is formed to form a gate circuit including gate lines G1, G2, G3, and G4, closed electrode pads 100, 110, and 120. Gate shorting strip 200, gate extension lines 101, 102, and 103, and auxiliary lines 210, 220, and 230. After that, an electrode insulating film 150, an amorphous stone film (not shown) and a mixed stone film (not shown) are successively deposited, and a wiring pattern is formed on the upper two layers to form an active wiring pattern.

Page 15 V. Description of the invention (12) As shown in FIGS. 11B and 12B, a metal layer is deposited and a wiring pattern is formed to form a data line 55 including data lines D1, d2, D3 and D4, a source and a drain (not shown) ), Data pads 50 0, 51, 52, and 53, data short bar 400, data extension lines 501, 50 02, 50 03, and 504, and auxiliary lines 410 and 420. After that, use the data line 5 5 as a veil to engrave a part of Shi Xi 骐 with a surname. The passivation film 50 is deposited as shown in Figs. UC, 1 ID, 12C, and 12D. Thereafter, the passivation film 50 and the gate insulating film 150 are etched to form contact holes e and μ, and the gate pads 110 and 120 and the data pads 51, 520, and 530 are exposed, and the contact holes A, B, C, and D, F, G, H, I, J, and K to expose the first to fifth auxiliary lines 410, 420, 210, 220, 230, gates and data extension lines 101, 102, 501, 502, 503 . Next, 'indium tin oxide (I T 0) is deposited and etched to form a pixel electrode. In the engraving method, the first and second connection elements 31 and 32, and the third and fifth connection elements 301, 302, and 303 are formed simultaneously. The first and second connection elements 3 10 and 320 respectively connect the first and second auxiliary lines 410 and 420 to the gate extension lines 101 and 102 via the contact holes a, c, B, and D. . The second, fourth, and fifth connecting elements 301, 302, and 303 respectively connect the second, fourth, and fifth auxiliary lines 5I, 502, and 503 to the gate extension via the contact holes GΗIJ and K. Line 2 10 '220 and 230. As shown in Figures 11 F and 1 2 F, the gate short-circuit bar is from the gate extension lines 100, ι〇2, and 丨 between the first auxiliary line 410 and the gate short-circuit bar 200. 3 Detachment 'and the data short-circuit bar 408 is detached from the data extension line 5 〇1… 5 〇2 and 503 between the third auxiliary line 2 丨 〇 and the data short-circuit bar 400.

For details, it is between the first auxiliary line with 0 and the gate short-circuit bar 200: between the gate extension lines 101 and 102 and between the third auxiliary line 21 and the data and road section 400 The data extension lines 501, 502, and 503 are exposed in the step of etching the passivation film 50. After forming the connecting elements 301, 302, 303, 31, and 32, the exposed portions of the extension wires 101, 102, 501, 502, and 503 are etched and removed. The gate short bar 2000 and the data short bar 400 can be removed by cutting along the cutting line before the array test. As mentioned above, since two adjacent gate lines are connected to two different auxiliary lines' and three adjacent data lines are connected to three different auxiliary lines, the display quality of the liquid crystal display can be easily tested. Λ Now, the structure of the connection between the auxiliary line and the gate line is also described. As shown in FIG. 13, a plurality of gate lines G1, G2, G3, G4, G5, and G6 intersect with a plurality of data lines D1, D2, D3, D4, D5, and D6 to define a plurality of arrays arranged in a matrix. Pixels. Odd gate lines G1, G3, and G5 and even gate lines G2, G4, and G6 are connected to the first and second auxiliary lines 410 and 420 respectively, so they can be used in odd pixel rows and even images. Element columns apply different signals. Three adjacent data lines (ie, (3η-2), (3η-1), and (3η) data lines) are connected to different pixels and arranged in three segments, such as Lines R, G, and B. Because the third, fourth, and fifth auxiliary lines are individually connected, three additional signals are applied to the three adjacent pixels via auxiliary lines 210, 220, and 230. Lines are formed separately at the ends of auxiliary lines 410, 420, 210, 2 20, and 23 0

V. Description of the invention (14) Test pads 4, 5, 6, 7 and 8. Hereinafter, the display test method of the first specific example will be described with reference to Figs. 13, 14, and 15A to 15C. ^ Figure 14 illustrates the wave pattern of the array test signal applied to the gate and data lines via the various auxiliary lines, and Figures 15A to 15C illustrate the polarities of the signals applied to the / G, B pixels in modes] to 3. As shown in Figs. 13 and 4, the odd and even numbers of the signal voltage G are applied to a plurality of gate lines in odd columns and a plurality of gate lines in even columns. Signal voltage, DG and 08 are applied to (3n-2), (3n-1) and (3n-2) and (3n-2) via the first to fifth auxiliary lines 4 丨 〇, 42〇, 2 丨 〇, 220 and 230 respectively. Articles (3n). The signal voltage will be described in more detail below. The signal voltage G odd and pulses including pulses connected to the thin film transistor are individually applied to the " odd gate line and even gate line via the first and second auxiliary lines 4 1 0 and 4 2 0. If the period from the time when one pulse is applied to the time when subsequent pulses are applied is defined as a frame, the signal voltage G of the even gate lines and the signal voltage G of the odd gate lines differ by half a frame. As a result, the connection of the thin film transistors in the even-numbered pixels with respect to the thin film transistors in the odd-numbered pixels has a half frame difference. During this period, the data signal voltages Dr, w, and DB that are individually applied to the pixel rows of r, G, and B are switched once in a frame. At this time, pulses are applied to the odd or even gate lines. In detail, the signal voltages applied to the selected two rows of the r, G, and B pixel rows are simultaneously switched 'and the signal polarities are opposite. For example, as shown in Figure 4, apply a signal with the same polarity to two rows of three pixel rows, and apply

Page 18 V. Description of the invention (15) Switching with even gate pulse. A signal with opposite polarity is applied to the remaining rows of the three-pixel row and switched when an odd-numbered gate pulse is applied. Figure 14 shows the signals of the three modes. First, 'in the first mode (mode 1)', the test surfactant DR applied to the r pixel row and the test signal% applied to the G pixel row have opposite polarities, and are switched when the pulse is applied to the even gate line The test signal applied to the β pixel row is switched when the pulse is applied to the odd gate line. When the first and second frames are activated, the polarities of the test signals Dr, ㈣ are ⑴, ㈠, and (-) respectively. In the first mode (mode 2), the wire · Λττ ^ λρ λ 铗 η η β η is identified % The test letters added to the R, G, and β pixel rows apply DR, DG, and DB in the first mode (magnetic 4t rod evening: head | 丨 bismuth produced by arsenic η η formula 1) applied to B, R, and G pixel element test. Equation || 5 says that DB, DR, and DG are the same. Furthermore, in the third mode (Hibiscus < 5 Test 俨 轳 D, D 'Formula 3), R, G, and β pixels are applied to the sum of JW1) R dg and DB and the first-hibiscus r The test signal Dg of the R pixel row is applied to G and B in the "J mode" and the test R added to the β, β, and G pixel rows is applied to the aforementioned first mode (mode 2). The signals are the same for each of B, Dr, and%. First, if the pulse is of pixel polarity. When the transistor is connected and the test signal is applied, the force is equal to the thin film of the adjacent pixel. When the thin film transistor is disconnected, the pulse “] is like a fan. When the columns of pixels pass through the even-column pixels, they are applied to the even-numbered gate lines, and the test signal is therefore -th to -th; ;;; The film transistor is applied to the even-numbered pixels. This is illustrated in Figures 15 A to 15C. The polarity of the pixels in the first frame (1 F) of the policy 1 t is shown in Figure 15A, and the polarity of the frame (2F) is reversed. Pixels are ordered in the first mode (mode 1), page 19 V. One of the invention description (16) and one of the pixels in the G pixel row has) and (_) or (―) and (+) Polarity 'and the polarity is switched depending on the number of lines. However, all the pixels in the B pixel row have the same polarity (-). In the column direction, the G and B pixels of the odd sequence have a polarity 'and the R pixels of the odd sequence have the opposite polarity to the B and G pixels. In the even-numbered columns, the β and R pixels have a polarity, and in the even-numbered columns, the G pixels have the opposite polarity to the B and R pixels. As shown in FIG. 15B, in the second mode (mode 2), one of the pixels in the g pixel row and one of the pixels in the β pixel row have (+) and (_) or (_) and ( +) Polarity, and the polarity is switched by the number of rows. All pixels in the R pixel row have the same polarity (-). If it is in the column direction, the β and ruler pixels in the odd sequence have a polarity, and the G pixel in the odd sequence has the opposite polarity to the B and r pixels. The R and G pixels in the even columns have a polarity, and the B pixels in the even columns have the opposite polarity to the R and G pixels. In addition, as shown in FIG. 15C, in the third mode (mode 3), one of the R-line pixels and one of the B-line pixels have (+) and (_) or (_) and (+) polarities, respectively. And the polarity is switched by line number. All (; row pixels have the same polarity (_). If it is column-oriented, R and (; pixels in odd columns have a polarity, while B pixels in odd columns have the same polarity as R and (^ pixels) The opposite polarity. The g-number in the even-numbered column has-polarity, and only the pixels in the even-numbered column have the opposite polarity to the G and 6 pixels. You can use one of the modes to test two adjacent gate lines. Or the short-circuit defect between two adjacent data lines. If the short-circuit defect occurs when two adjacent pixels with the phase == are applied, the signal strength of the signal applied to the pixel becomes an earlier value, that is, two voltages. The average value, the result is the same voltage is applied to pixel five, invention description (π) —----. Therefore, because of the gray image of adjacent short-circuit pixels, short-circuit defects can be detected. Moreover, if 4 does not The same as between adjacent lines, because the same signal is applied to the short circuit line = defect system, it can easily detect short circuit defects. Several columns or rows However, it is difficult to detect the adjacent between the same test signal Short circuit defect and determine its cutting position. With any two tests in these three modes, it is easy to detect pixel defects such as-诸如 defects between adjacent pixels, and determine the location of the defect, because at least once in the column direction, = adjacent image Different polarities are applied to the element. # In addition, in the test method of the first specific example, because the polarities of the signals DR, DG, and DB applied to the auxiliary lines 2 1 0, 2 2 0, and 2 3 0 continue a frame, and the signal The fluctuation is negligible, so the uniformity can be detected and displayed. The display method of the second specific example will now be described with reference to Figs. 16, 17A and 17B. Fig. 16 illustrates the array test signal applied to the gate and data lines by the second specific example. Figs. 17A to 17B illustrate the polarities of the signals applied to only pixels G, B, and B in the second specific example. The signal voltages C odd and G even and DR, RG, and h shown in Fig. 16 Individual nickel is applied from the first to the fifth auxiliary lines 410, 42 0, 210, 22 0, and 230 to the odd and even pixel rows and (3n-2), (3n-1), and (3n) Data line. As in the first specific example, if the time from applying a pulse to applying the subsequent pulse is It is defined as a frame period, the source lines of the even gate channel

Page 21 V. Description of the invention (18) During the signal period of voltage G even-numbered and odd-numbered gate lines, it is applied to J ?, G, and β pixels and the odd-numbered difference is half a frame. Converted several times in the-frame, the cycle and: the redemption degree I,

The polarities of DG, DB and DB are switched when the gate pulse is ’° No. 4 voltage DK gate line, and the pulse is applied to; the polarity of the odd gate line and the even number is opposite when applied to the even gate line? The polarity at the time of 5 lines is opposite to that of the pulses generated in the r, g, and b pixel lines. The signals with opposite polarities are applied to R and G. There are two kinds of _ and the two-element line circle 16 shows two kinds. Signal of mode. The remaining 70 lines. In the fourth mode (mode 4), the image with the same test signal is applied to the R pixel row and the same conversion period, and the same number of pixels in the test signal team and the 0 to 8 cycle as the test cell. The signal DG is applied to the rest of the G pixel rows, and the cycle is reversed. In the fifth mode (mode 5), the pixel of $ and the edge of the G pixel row are applied to the R image. The yuan line is added to the pixels of the beta cell line. In contrast, test signals with opposite polarities are shown in Figures 17A and 17B. In the fifth mode, when the signal is applied, in the fourth mode as shown in FIG. 17A, the polarities are opposite to each other, and the adjacent pixels have the same polarity. All the polarities have the opposite polarity / all adjacent pixels (except the phase). The adjacent B and R images shown in Figure 17B have opposite polarities to each other, and 4 /: 'All adjacent pixels in all row directions are outside) have opposite polarities. (Except for adjacent R and G

Two i: As described in the specific example of the text, the short-circuit defect can be tested by using Zenggu in the second specific example. If two modes are applied, the test capabilities can be easily compared, and it is easy to test for pixel defects such as short-circuit defects between images like 7L where test signals with the same polarity are applied.

In the specific example of L2 test, the switching period of m ® 4 applied to R, G, and B ^ k polarities is the same as the gate pulse width, and the signal is not sent into the pixel. As a result, a flicker effect is generated. In addition, it is not suitable to measure the uniformity of the display confirmed by the naked eye, and it is difficult to test the pixel defects in the high state or the broken state. Figure 18 shows the test pattern of the third specific example to improve this problem. In Fig. 18, the signals Dr,%, and D applied to the pixel rows of r, g, and b, and the signals G odd and even applied to the odd and even gate lines are mostly the same as those in the second specific example. The signal switching period applied to the pixel rows of r, G, and b is twice the gate pulse width. Therefore, the r, G, and 8 signals can be applied to the picture element without difficulty, synchronizing the gate pulse and the data signal 'to reduce the flicker effect. As a result, the test method of the third specific example is good at testing the uniformity and defects in the high state and the off state. FIG. 19 illustrates the waveform of the array test signal of the fourth specific example, in which pulses are applied to the odd gate lines and even gate lines, and the two pulses are synchronized under a half frame difference. The test signal conversion cycle is twice the gate pulse width. In the fourth specific example, the gate pulse is applied more slowly than the signals DR, DG, and DB applied to the r, G, and B pixel rows. So when thin film transistors

Page 23 V. Description of the invention (20) When connected, the signal can shorten the charging space at high original charging value, and the signal charging can be easily performed by applying the gate pulse even on the south resolution substrate. As described above, in the liquid crystal display of the present invention, the road bar or the data-assisted short-circuit bar is formed separately and has a line, which is separated from the gate short-circuit bar and the data short-circuit bar, and has an electrostatic charge. In addition, ‘because the test signal can be the same as the gate and data’, the detection capacity of the substrate is increased. The substrate that is defective is not continuously used in subsequent steps. 3 It is discarded, which can reduce manufacturing costs. In addition, the data signal can be activated at Shi to make the data signal fill the resolution substrate in the human pixel. In the drawings and the specification, a typical example of the present invention has been disclosed. Although a specific substance is used, it is only used for general description. The scope of the present invention is set in the following patent application scope. As a result, it is charged at the time of charging. Therefore, because the gate assist is shorter than two points, the substrate is good at resisting the short-circuit bar. As a result, it is easy to test the detailed description of the better and better because it is before the gate pulse is added in the test step, and does not constitute a limit.

Claims (1)

6. Scope of Patent Application 1. A liquid crystal display device comprising: a plurality of first lines transmitting a first signal extending in one direction and being substantially parallel to each other; a plurality of second lines transmitting a second signal substantially in line with the The first line is parallel; the first short-circuit bar is connected to the first line; the second short-circuit bar is connected to the second line; and the main short-circuit bar is located outside the first and second lines. 2. For the liquid crystal display of the first scope of the patent application, wherein the first and second lines are gate lines, and the first and second signals are scanning signals. 3. For the liquid crystal display of the first patent application scope, wherein the first and second lines are data lines, and the first and second signals are image signals. 4. For the liquid crystal display of item 1 of the patent application scope, wherein the main short circuit is connected to the first and second lines. 5. For the liquid crystal display of the first scope of the patent application, wherein the first and second circuits are alternately arranged with each other. 6. A liquid crystal display comprising: an insulating substrate; a plurality of gate lines located in a horizontal direction on an upper layer of the substrate; a gate insulating film covering the gate lines and having a first contact hole to expose a part of the gate Lines; multiple data lines, located above the gate insulation film, extending vertically Page 25 VI. The patent application is oriented, and it intersects with the gate line. · The first short-circuit grid, A &direction; ', on the upper layer of the gate insulation film, and extends to the vertical side first' Jiang H ya Bei ≫ Λν VA short-circuit bar; 〃 is on the upper layer of the gate insulation film, substantially parallel to the first passivation film, and covers 杳 #A with the branch line on the first contact hole and the first and second short-circuit bars, and The second contact holes of the first and second shorting strips, and the four contact holes of the first-connecting element are individually connected to the first layer and the upper layer of the passivation film. A short-circuit bar; and f 5 line, which is connected to the first contact hole through the third contact hole to the first layer, and through the first and second via 7: four contact holes are connected to the second group of idler wires connected to the second , *. Item 凊: The liquid crystal display of item 6 of the scope of interest, which additionally includes. Horizontal =;:;, The fourth and fifth shorting bars are located on the upper layer of the substrate, and extend to the upper part of the piece, located on the upper layer of the passivation film; Connected to the third, dagger and == connecting elements are individually connected to the data line 8. If the scope of patent application The fifth contact element with the exposed data line in item 7, said without saying: 'wherein the passivation film individually exposes the third, fourth, and 犋 and gate insulating film with eight contact holes, wherein the third The fourth, fourth, and sixth sixth, seventh, and fifth connecting elements are individually connected to the contact hole connection and the second line through the sixth and fifth contact holes, and are connected through the sixth, seventh, and eighth. : On the second, fourth and fifth short-circuit bars. The short-circuit bar, 1-pass #f 4 member LCD display, which additionally includes a gate, such as Shen Pei, Zhi: Λ upper board, and is connected to the gate line. Material short-circuiting strip, which is the liquid crystal display which has been surrounded by item 9, which additionally includes data such as applying for a patent; "on the insulating film and connected to the data line. The new two bars are electrically connected to the short circuit bar. _Buqi, where the information • If the 6th pole short-circuit bar in the scope of the patent application, the liquid display around the 6th item, it also includes the first and second extensions in the vertical direction, separated by polar lines— The road is located in the same direction as the gate line ># $ 对 刀 &.位置 position, and the liquid crystal & direction of the patent scope No. 12 of the patent scope, the phase # f · 2 /, is located on the upper layer of the gate insulation film. The decree 'extends 14 ^ horizontally and is separated from the data line. The bar is located opposite to the data line. The short-circuit bar is a liquid crystal display of item 13 of the private application patent scope. It is not electrically connected to the gate short-circuit bar. No. 15: a type of liquid crystal display, which includes: a plurality of open-pole wires, a short-circuit bar, and an insulating substrate; 'the water on the upper layer of the substrate is also directed; Θ 'on the gate insulating film is substantially parallel to the Page 27 is located on the gate insulation film; ^; 6. Patent application scope short circuit strip; Gate insulation film covers the gate line and the first ~ has the first and second contact holes to expose an eight second short Strips, and strips; are the first and second short-circuited multiple data lines, located above the gate insulation film and intersecting with the gate lines; a layer, extending in a vertical passivation film, covering the data lines and the The first has a third and second shorting bar on the first contact hole and the second, and a fifth contact hole on the data line, a fourth contact hole, and a bit-first-connecting element located on the upper layer of the passivation film , The contact hole is connected to the first group of gate lines, and the first and third short-circuit bars are connected through it; and the Le Wu contact hole is connected to the second connection element, which is located on the upper layer of the passivation ridge, and the contact hole is connected to the The first connection element connection t is connected to the second short-circuit bar via the second and fourth via the fifth contact hole. The second set of gate lines, and HH, please refer to the liquid crystal fin of item 15 of the patent scope. Q, the new road strip, which is located on the upper layer of the substrate, and the device, which additionally includes the 16th patent scope of J.Λ application for patents. The LCD of the item is connected to the gate line. / Ugly strip, which is located on the gate insulation film, and it also includes a short-circuit bar V, please apply the liquid crystal of item 17 of the patent scope to the data line. Another bar is electrically connected to the gate short-circuit bar. "Shoulder device, which includes the following information: Lushen / Patent No. 15 LCD • Thousands. It is located on the gate insulation film, and it also includes ° for the first and second short-circuit bars. ^ And extend to the horizontal side ^ The opposite of the data line on page 28 6. Separate from the data line when applying for a patent scope. 20. As for the liquid in the 19th scope of the patent application, ΛΛΛλ. Separate from the gate line. 埯狎 In the vertical direction, and ―21. The liquid crystal button strip of item 20 of the patent application range is electrically connected to the data shorting strip. ', The gate 22. A method of manufacturing a liquid crystal display, which deposits a metal layer; Layer to make a wiring pattern to form a gate line; to form a gate insulating film to cover the gate line; to form a data line and the first and second short, > gate lines above the edge film; to test Located on the gate electrode, the product is purified; contact Γ] ί: the film and the open-pole insulating film 'to form the first, second, and third contact lines and the first and second short-circuit strips; Build a conductive layer; and make a great line pattern on the conductive layer to) The element is connected to the second short-circuiting bar via the first and the first contact a * imaging electrodes. The second contact hole is connected to the gate line and the method of manufacturing a liquid crystal display according to item 22 of the Λ3 'Λ7 patent scope, Patterns: Connect: Steps of “short circuit”, which uses metal layers to make wiring; f-pole wires, to protect against electrostatic discharge. 4. For example, the method of manufacturing a liquid crystal display for claim 23 of the patent, 29 Stomach 6. The scope of patent application also includes the step of detaching the third short-circuit bar from the gate line after forming the first and second connecting elements. 25_ —A method for manufacturing a liquid crystal display, which includes the steps of: forming a closed-electrode line And first, second, and third shorting bars to test the data lines on the substrate; forming a gate insulating film; depositing a metal layer on the gate insulating film;-making wiring patterns on the metal layer to form data lines, · Depositing a passivation film; etching the passivation film and the gate insulating film to form first, second and third contact holes, which individually expose data lines and first, second and third shorting bars; depositing a conductive layer; and Make a wiring pattern on the conductive layer to form pixel electrodes and connection elements, connect to the data lines through the first and second contact holes, and connect to the first, second, and second lines through the second, third, and fourth contact holes. The third short-circuiting strip. 2 6. The method for manufacturing a liquid crystal display according to item 25 of the patent application scope, further comprising a step of forming a fourth short-circuiting strip, which is connected to the data line by using a metal layer to make a wiring pattern to obtain 27. The method of manufacturing a liquid crystal display according to item 26 of the patent application scope, further comprising the step of detaching the fourth short-circuit bar from the data line after forming the first, second and third connecting elements. 2 8. A method for manufacturing a liquid crystal display, comprising the steps of: forming a circuit including a plurality of gate lines, a plurality of data lines, a main short-circuit bar connected to the gate lines and the data lines for electrostatic discharge protection, and Measurement Page 30 6. The first and second short-circuit bars and J-four short-circuit bars of the test gate line in the scope of patent application. The first and second short-circuit bars in # are: alternative materials: the third and fourth short-circuit bars. The bars are individually connected at two intervals each time = detached from the gate and data lines, and the main short-circuit and trial capital; force :! Press the first, third [, third, and fourth short-circuit bars to measure the defects of the * Zike line and the gate line. j 29. The method for manufacturing a liquid crystal display according to item 28 of the scope of patent application, wherein the voltages applied to the first short bar and the second short bar by the target are different. 30. The method for manufacturing a liquid crystal display according to item 28 of the scope of patent application, wherein the voltages applied to the third short-circuit bar and the fourth short-circuit bar are different. 31. The method for manufacturing a liquid crystal display according to item 28 of the patent application scope, further comprising the step of removing the first, second, third, and fourth short-circuit bars after the voltage application step. 3 2. —A method for testing a liquid crystal display having a plurality of pixels arranged in a matrix shape, a plurality of pixels connected to odd-numbered pixels — a gate line, and a plurality of pixels connected to even-numbered pixels Two gate lines and a plurality of first, second and third data lines, which are connected to different rows of pixels and arranged in three segments, include the steps of: first applying a first pulse to the first gate line; The second pulse is applied for the second time to the second gate line; the first and second signals with the same polarity are applied to the first and second data lines once, and the polarity and the first and second signals are applied to the third data line. A third signal opposite the second signal; and IH1 page 31 6. Scope of patent application The first and second signals are applied to the second and third data lines for the second time, and the third signals are applied to the first data line. 3 3. The test method according to item 32 of the scope of patent application, wherein the first and second pulses are periodically applied, and the first and second pulses are separated from each other by half a frame. 3. The test method according to item 32 of the scope of patent application, further comprising the steps of: applying a third pulse to the first gate line for the third time; applying a fourth pulse to the second gate line for the fourth time; third Applying the first and second signals to the second and third data lines, and applying the third signal to the first data line, and applying the first and second signals to the first and third data lines, A third signal is applied to the second data line. 3 5. The test method according to item 34 of the scope of patent application, wherein the third and fourth pulses are applied periodically, and the third and fourth pulses are separated by half a frame from each other. 3 6. —A method for testing a liquid crystal display having a plurality of pixels arranged in a matrix shape, a plurality of first gate lines connected to pixels in odd columns, and a plurality of first electrodes connected to pixels in even columns Two gate lines and a plurality of first, second and third data lines, which are connected to different rows of pixels and arranged in three segments, include the steps of: applying a first pulse to the first gate for the first time Line; a second pulse is applied to the second gate line for the second time; and a first conversion period is applied to the first and second data lines for the first time Page 32 6. The first signal with polarity conversion in the scope of the patent application, and the second signal with the opposite polarity to the first signal is applied to the third data line; and the second signal is applied to the first and second signals for the second time Data line, and the first signal is applied to the third data line. 3 7. The test method according to item 36 of the patent application scope, further comprising the steps of: applying a third pulse to the first gate line for the third time; applying a fourth pulse to the second gate line for the second time; third The first signal is applied to the first and third data lines, and the second signal is applied to the second gate data line; and the fourth signal is applied to the second data line, and the second signal is applied to the first data line. First and third data lines. 3 8. The test method according to item 37 of the scope of patent application, wherein the first and second times, or the third and fourth times are separated by a half frame. 39. The test method according to item 37 of the scope of patent application, wherein the first, second, third, and fourth times are the first and second signal transitions. 40. The test method according to item 39 of the scope of patent application, wherein the first conversion period is the same as the individual width of the first to fourth pulses. 4 1. The test method according to item 39 of the patent application range, wherein the conversion period is twice the individual width of the first to fourth pulses. 4 2. The test method according to item 37 of the scope of patent application, wherein the first to fourth times are clamped between the first and second signal conversion times. 4 3. The test method according to item 42 of the scope of patent application, wherein the first conversion period is larger than the individual widths of the first to fourth pulses. Page 33