JP3356839B2 - Active matrix array inspection system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of gate signal lines and a large number of data signal lines which are insulated from each other and arranged in rows and columns so as to be orthogonal to each other in a matrix. The present invention relates to an inspection apparatus for an active matrix array (liquid crystal display substrate) incorporated in an active matrix array type liquid crystal display (liquid crystal display device), to which a transistor (transistor) is connected and a pixel (pixel) electrode is driven through each thin film transistor.

[0002]

2. Description of the Related Art In recent years, the number of scanning lines has increased due to the increase in the number of pixels accompanying the increase in the size and definition of a liquid crystal display, and the display contrast and response speed of a conventional simple matrix type display have been reduced. An active matrix type liquid crystal display in which a switching element is arranged in each pixel is being used. However,
An active matrix array (liquid crystal display substrate) incorporated in such an active matrix type liquid crystal display must form thin film elements and thin film circuits including tens of thousands of thin film transistors as switching elements on a single glass substrate, for example. No. For this reason, to manufacture the active matrix array without defects over the whole requires a very advanced technique. Current technology produces a significant number of defective active matrix arrays, so it is necessary to inspect the active matrix array for defects, determine pass / fail, detect defects, and repair defective areas. is there. In addition, since the active matrix array is considerably expensive, detecting and repairing defects is considerably more advantageous in terms of cost than disposal.

FIG. 7 schematically shows an example of an active matrix array used in a conventional active matrix type liquid crystal display. As shown, the active matrix array, a row (horizontal) number in parallel with the wiring at predetermined intervals in the direction of gate signal lines X ₁ ~X m + _1,
A large number of source signal lines (also called data signal lines) Y _{1 to} Y _n wired in parallel at predetermined intervals in the column (vertical) direction
The gate signal lines X _{1 to} X _{m + 1} and the source signal lines Y _{1 to} Y _n arranged in a matrix are insulated from each other and are in an orthogonal state.

The last gate signal line X_{m + 1} Gate signal excluding
Line X₁ ~ X_mAnd source signal line Y₁~ Y_nAt each intersection
Thin film transistor (generally thin film field effect transistor
T) T ₁₁~ T_mnAre provided, and each thin film field effect
The gate electrode of the transistor is connected to the corresponding gate signal line X₁ ~ X
_mAnd its source electrode is connected to the corresponding source signal line Y
₁ ~ Y_nConnected to the
The pole is both signal lines X₁ ~ X_{m + 1} And Y₁ ~ Y_nInside square
Pixel electrode P arranged in the region of₁₁~ P_mnOne terminal of
Connected to each other. These pixel electrodes P₁₁~ P_mn
Are arranged in a matrix, and the other of each pixel electrode
Each terminal is an auxiliary capacitance element (storage capacitance element) C₁₁~ C
_mnThrough the gate signal line X of the next row_Two ~ X_{m + 1} Niso
Each is connected.

[0005] In an active matrix array having the above structure, for example a short circuit defect 12 between the gate and the drain as transistor T ₂₁ is generated, when configured as a liquid crystal display, the pixel electrode connected to the transistor having the defect Is abnormal, and the display quality is significantly reduced. Factors Further, even when a short-circuit defect 13 between the source and the drain as the transistor T ₁₂ is generated, the display state of the pixel electrode by the short circuit when configured as a liquid crystal display becomes abnormal, which significantly reduces the display quality also Becomes Therefore, by detecting these defective thin film transistors and defective parts,
It is important to repair the defective transistor or defective part.

For this reason, conventionally, active mat
The lix array was inspected as follows. That is,
Signal line X₁ ~ X_{m + 1} ON / OFF at one end
Switch S₁₁~ S_{1m + 1}Are connected in series, and these switches S
₁₁~ S_{1m + 1}Are connected in common to the resistance measuring means 14.
Continue. Also, the source signal line Y₁ ~ Y_nAt one end of it
ON / OFF switch S_{twenty one}~ S_2nConnected in series.
These switches S_{twenty one}~ S _2nConnect the other end of the
Connect to anti-measurement means 14. In addition, defect points are detected
To a predetermined position of the active matrix array
Test probe position with test probe 16 to be touched
A determination means 15 is provided, and the position of the test probe is determined.
The test probe 16 is activated by the positioning means 15.
Position at a predetermined position in the
It is to detect.

The resistance measuring means 14 is also connected to the test probe 16 so that the resistance between the arbitrary gate signal line or the source signal line and the pixel electrode connected to the drain electrode of the arbitrary thin film field effect transistor. The resistance value can be measured. Hereinafter, components having the same symbol and the same number have the same configuration. In conventional inspection apparatus having the above structure, to check the gate-drain defects of the transistor T ₁₁ closes the switch S ₁₁ of the gate signal line X ₁ together opens the switch S ₂₁ of the source signal line Y _1. Next, positioning the test probe 16 to the pixel electrode P _11, which is connected to the drain electrode of the thin film transistor T ₁₁ by a test probe location means 15. Then, by the resistance measuring means 14 for measuring the resistance between the gate and the drain of the thin film transistor T _11. A defect can be detected from the measured resistance value. Similarly, the thin film transistor T ₂₁
Opens the switch S ₁₁ of the gate signal line X ₁ for,
Closing the switch S ₁₂ of the gate signal line X _2, positioning the test probe 16 to the pixel electrode P _12, which is connected to the drain electrode of the thin film transistor T _21, the resistance measuring means 14
It may be repeated operation of measuring the resistance value between the gate and the drain of the thin film transistor T ₂₁ by. When finished with thin film transistors T _m1, then the source signal line Y ₂
Open the switch S _22, the thin-film transistor T ₁₂ ~T _m2
, The same operation as described above may be repeated to measure the resistance value between the gate and drain of each transistor. The above operation is repeated up to the thin film transistor _Tmn .

Next, a method for detecting a source-drain defect
Will be described. In this case, first, the gate signal line X
₁ Switch S₁₁And the source signal line Y₁ 
Switch S_{twenty one}Close. Next, test probe positioning
Means 15 by means of₁₁Drain current
Pixel electrode P connected to the pole₁₁Test probe 16
Position. Thereafter, the thin film transistor is
Lanista T₁₁The resistance between the source and drain of the
You. Defects can be detected from the measured resistance value.
You. Similarly, the thin film transistor T_{twenty one}About the gate
Signal line X_Two Switch S₁₂Open the test probe 1
6 is a thin film transistor T _{twenty one}Connected to the drain electrode of
Pixel electrode P_{twenty one}And its transistor T _{twenty one}No so
The operation of measuring the source-drain resistance is repeated
I should do it. Thus, the thin film transistor T_m1For up to
When the resistance value measurement is completed,₁ of
Switch S₁₂And the source signal line Y_Two Switch S
_{twenty two}Closed, this time the thin film transistor T₁₂And above
The same operation may be repeated to measure the resistance value. Less than
The above operation is performed by the thin film transistor T._mnRepeat until

However, in the conventional configuration as described above, since the inspection is performed using the test probe 16, it is necessary to directly contact the test probe 16 with the drain electrode of the thin film transistor or the pixel electrode connected to the drain electrode. May be damaged. In addition, there is also a disadvantage that defect detection leakage due to a contact failure of the test probe 16 easily occurs. In addition, it is necessary to perform the defect detection while moving the test probe 16, and there is a problem that an enormous amount of time is required for the positioning time because all the mechanical positioning is performed.

For this reason, as disclosed in, for example, Japanese Patent Laid-Open No. 5-11000, there has been proposed an inspection apparatus capable of detecting a defect of an active matrix array in a non-contact manner. In the invention described in this publication, the gate signal generation means 17 and the source signal generation means 18 are provided, and the active matrix array 1 to be inspected is provided.
1, each of the gate signal lines X _{1 to} X _{m + 1} is switched by the gate signal line selecting means 19 to any one of the output terminal of the gate signal generating means 17, the open terminal, and the ground terminal;
Further, the source signal line selection means 20 switches and connects each of the source signal lines Y _{1 to} Y _n to any one of the output terminal of the source signal generation means 18, the open terminal, and the ground terminal,
The gate signal generating means 17 and the source signal generating means 18 applies a high level signal or a low level signal, the drain of the TFT T ₁₁ through T _mn, which is connected to the signal lines at each intersection of the gate signal line and the source signal line Non-contact probe detects the electrical state of the electrode without contact,
The quality of the thin film transistor is determined based on the detection output.

In the case of an active matrix array in which gate signal lines and source signal lines are short-circuited by short rings (also called short buses) 38 and 39, the gate signal lines in the active matrix array are short-circuited. The gate signal generation means 17 is connected to the gate signal line short ring 38 through the gate switch S1 and the source signal generation means 18 is connected to the source signal line short ring 39 shorting the source signal line through the source switch S2. After the connection, the non-contact probe and the determination means determine the quality of the thin film transistor in the same manner as described above.

Further, in the case of an active matrix array having a built-in drive circuit, a signal capable of sequentially driving gate signal lines by operating the built-in vertical shift register is connected to the vertical shift register through gate switch means. A signal generated from the gate signal generating means, which can drive the built-in horizontal shift register and the source line driving circuit to sequentially drive the source signal lines,
The non-contact probe and the judging means are used to judge pass / fail of the thin film transistor in the same manner as described above, generated from the source signal generating means connected to the horizontal shift register and the source line driving circuit through the source switch means.

It is also described that a charge optical probe is used as a non-contact probe, and an electro-optic probe or an electron beam probe can be used instead of the charge optical probe.

[0014]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 5-110 is disclosed.
As described in Japanese Unexamined Patent Publication No. 00-2000, an active matrix array generally has a data (source) signal line and a gate signal line which are active in order to prevent breakdown of a thin film field effect transistor due to static electricity generated in a manufacturing process. It is connected to a short bus (short ring) formed around the matrix array. In the above publication, short buses are formed on two sides of the active matrix array. However, every other data signal line is drawn out (alternately) to the opposite side, and every other gate signal line is alternately (alternately). A) Active matrix arrays of the type in which the signal lines of each side (four sides) which are drawn out to the opposite side are connected to short buses formed on each side, respectively, and are short-circuited are also manufactured. . Also, every other data signal line is drawn out to the opposite side, but the storage capacitor elements arranged in the row direction are not connected to the next gate signal line but to the common signal line parallel to the gate signal line. A common bus line and a gate signal line to which the storage capacitance elements are connected are led out to the opposite sides, and the shorted bus is formed on each side with the led-out signal lines on each side (four sides). Active matrix arrays of the type connected to and short-circuited have also been manufactured considerably. The short bus is removed at the end of the manufacturing process.

Incidentally, gate signal lines and data signal lines,
Alternatively, in the case of an active matrix array in which the common signal lines are short-circuited by short buses, the active matrix array must be inspected for defects while the short bus remains attached. JP-A-5-1
In the invention disclosed in JP-A-1000-1000, as described above, the gate signal generating means is connected to the gate signal line short ring that shorts the gate signal line in the active matrix array through the gate switch, and the source signal is The source signal generating means is connected to the short ring for the source signal line, which short-circuits the source signal, through a source switch, and a high-level or low-level signal is applied from the signal generating means. , Is determined to be defective. In this case, when detecting a short circuit between the gate signal line and the drain electrode, that is, between the gate and the drain of the transistor, a high-level signal is applied from the gate signal generation means 17 to all the gate signal lines, and the source signal generation means 18 From this, a low level signal is applied to all the source signal lines, and a pixel electrode having a high level is determined to have a defect. Also,
When detecting a short circuit between the source and the drain, a low level signal is applied from the gate signal generation means 17 to all gate signal lines, and a high level signal is applied from the source signal generation means 18 to all source signal lines. If the electrode is at a high level, it is determined that there is a defect. When detecting a short circuit between the auxiliary capacitance element and the gate signal line,
A high level signal is applied from the gate signal generation means 17 to all gate signal lines, and a low level signal is applied from the source signal generation means 18 to all source signal lines. I judge. Further, when detecting a short circuit between the auxiliary capacitance element and the source signal line, a low level signal is applied from the gate signal generation means 17 to all the gate signal lines, and the source signal generation means 18
From the above, a high level signal is applied to all the source signal lines, and it is determined that a pixel electrode having a high level has a defect.

Therefore, although a defective transistor can be detected and a defect between the auxiliary capacitance element and the gate signal line or the source signal line can be detected, the disconnection of the gate signal line or the source signal line or the disconnection of the gate signal line, which also significantly lowers the display quality. Leakage between the signal line and the source signal line or between the signal line and the pixel, or defect of the pixel, etc., cannot be detected. Of course, it is impossible to specify the disconnection position of the signal line (determination at which signal line level the disconnection is). It is. Therefore, there is a serious disadvantage that the active matrix array inspection apparatus disclosed in the above-mentioned publication cannot sufficiently detect defects.

An object of the present invention is to detect a defective transistor in an active matrix array in which a signal line is short-circuited by a short bus and a defect between a storage capacitor element and a signal line, as well as disconnection of a signal line and a signal line. Alternatively, an active matrix that can accurately and easily detect a leak between a signal line and a pixel electrode, a transistor leak, or a defect of a pixel electrode without contact, and can also accurately specify a defect detection position. An object of the present invention is to provide an array inspection device.

[0018]

According to the present invention, a large number of gate signal lines and a large number of data signal lines are insulated from each other and arranged in rows and columns in a matrix at right angles, and each intersection of these signal lines is provided. , The thin film transistor is connected to the gate signal line and the data signal line, the remaining electrode of each thin film transistor is connected to one terminal of the pixel electrode, and the other terminal of each pixel electrode is connected to the next gate signal line through the storage capacitor element. Connected, the gate signal line and the data signal line are separated and taken out, the data signal line is connected to a short bus for the corresponding data signal line, and the gate signal lines are alternately placed on the opposite side. Or, in the case of an active matrix array of a type that is pulled out in the same direction and separately connected to the corresponding short bus for the gate signal line. An AC voltage for adhering a liquid containing a voltage-sensitive dye to the circuit pattern forming surface of the active matrix array and charging the storage capacitor to a gate signal line connected to one of the short buses for the gate signal line. And a pulse-like bias synchronized with an AC voltage for charging the storage capacitor, for conducting the thin-film transistor to the gate signal line connected to the other short bus for the gate signal line. A voltage is applied collectively, and the color change state of the voltage-sensitive dye based on the voltage charged in the storage capacitance element is imaged by a color imaging unit, and various defects of the active matrix array are determined based on the captured color image. For example, defective transistors, defective pixels, disconnection of data signal lines, disconnection of gate signal lines, and leakage between signal lines. , To detect the leakage of a transistor or the like.

In addition, a large number of gate signal lines and a large number of data signal lines are insulated from each other and arranged in rows and columns in a matrix at right angles. At each intersection of these signal lines, a thin film transistor forms a gate signal line and a data line. A signal line, the remaining electrode of each thin film transistor is connected to one terminal of a pixel electrode, and the other terminal of each pixel electrode arranged in the row direction is connected in parallel with the gate signal line through a storage capacitor. Connected to a communication line, the gate signal line and the common signal line and the data signal line are separated and taken out, the data signal line is connected to a corresponding short bus for the data signal line, and the gate The signal line and the common signal line to which the storage capacitance element is connected are drawn out on opposite sides or in the same direction, and the corresponding gate signal In the case of an active matrix array of a type separately connected to a short bus for the common signal line and a short bus for the common signal line, a liquid containing a voltage-sensitive dye is attached to the circuit pattern forming surface of the active matrix array, While applying an AC voltage for charging the storage capacitor element to the common signal line connected to the short bus for the common signal line at a time, the gate signal line connected to the short bus for the gate signal line is applied to the gate signal line. A pulse-like bias voltage synchronized with an AC voltage for charging the storage capacitor for applying the thin film transistor is applied collectively, and the color change of the voltage-sensitive dye based on the voltage charged to the storage capacitor is performed. The state is imaged by a color imager, and the active matrix array is Defects such defects transistor, a defective pixel, disconnection of data signal lines, the disconnection of the gate signal line, leakage between the signal lines, for detecting the leakage of a transistor or the like.

[0020]

According to the structure of the present invention, a voltage can be applied collectively to a circuit pattern, a thin film transistor, a pixel electrode, and a storage capacitor element formed in an active matrix array, and the voltage can be changed according to the state of color development of a voltage-sensitive dye. Since the various defects are detected, the defects of the active matrix array can be surely and collectively known in a non-contact manner. In addition, since a voltage that repeatedly changes between positive and negative is used as a voltage for charging the storage capacitor, the voltage-sensitive dye causes oscillation of coloring / decoloring, and the reaction amplitude of the portion to which the voltage is applied is detected. Therefore, unnecessary interference components can be removed. Further, data is extracted in time series for each observation point, and the time-series observation value is synchronized with the applied voltage, so that the color change state can be reliably detected and the S / N ratio is improved. In addition, since the color image formed on the active matrix array can be detected with the resolution of the color imaging means, the color image can be detected in a unit much smaller than the circuit unit of the active matrix array, and the detection resolution is improved. improves. Further, the defect detection position can be specified accurately.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the present invention, a large number of gate signal lines and a large number of data signal lines are insulated from each other, are arranged in rows and columns in a matrix, and are orthogonally arranged. At each intersection of these signal lines, a thin film transistor (thin film field effect transistor) ) Is connected to the gate signal line and the data signal line, the drain (collector) or source (emitter) electrode of each thin film transistor is connected to one terminal of the pixel electrode, and the other terminal of each pixel electrode is immediately connected to the storage capacitor element. In the case of an active matrix array (liquid crystal display substrate) of the type connected to the next gate signal line, the gate signal line and the data signal line are separated and taken out,
The extraction terminals (bonding pads) of the data signal lines are connected to the corresponding short buses for the data signal lines, and the gate signal lines are alternately alternately drawn out to the opposite side or in the same direction, and their extraction is performed. The present invention is particularly effective when applied to an active matrix array in which terminals (bonding pads) are separately connected to corresponding short buses for gate signal lines, and also includes a large number of gate signal lines and a large number of data. The signal lines are insulated from each other and arranged in rows and columns in a matrix at right angles. At each intersection of these signal lines, a thin film transistor is connected to a gate signal line and a data signal line, and the drain (collector) or source ( An emitter) electrode is connected to one terminal of the pixel electrode, and the other of the pixel electrodes arranged in the row direction. In the case of an active matrix array in which terminals are respectively connected to common signal lines substantially parallel to gate signal lines through storage capacitance elements, gate signal lines and common signal lines and data signal lines are separated and taken out, The extraction terminal (bonding pad) of the data signal line is connected to the corresponding short bus for the data signal line, and the gate signal line and the common signal line to which the storage capacitance element is connected are drawn out on the opposite side or in the same direction. In particular, the present invention is particularly effective when applied to an active matrix array in which these take-out terminals (bonding pads) are separately connected to corresponding short buses for gate signal lines and short buses for common signal lines. .

FIG. 1 is a block diagram schematically showing an example of the former active matrix array which is particularly effective when the present invention is applied. As shown in the figure, this active matrix array has a large number of gate signal lines G1 to Gm + 1 wired in parallel in a row (horizontal) direction at a predetermined interval and in a column (vertical) direction at a predetermined interval. , And a plurality of data signal lines S1 to Sn arranged in a matrix. The gate signal lines G1 to Gm + 1 and the data signal lines S1 to Sn arranged in a matrix are provided.
Are insulated from each other and are in an orthogonal state.

Except for the last gate signal line Gm + 1, thin film transistors (field effect transistors in this embodiment) T11 to Tmn are provided at intersections of the gate signal lines G1 to Gm and the data signal lines S1 to Sn, respectively. The gate electrodes of the thin film field effect transistors T11 to Tmn are connected to the corresponding gate signal lines G1 to Gm, the source electrodes are connected to the corresponding data signal lines S1 to Sn, respectively, and the drain electrode D is connected to both signal lines. Lines G1 to Gm + 1 and S1 to Sn
Pixel electrodes P11 to Pmn arranged in a rectangular area inside
Are connected to one of the terminals. The pixel electrodes P11 to Pmn are arranged in a matrix, and the other terminal of each pixel electrode is connected to the gate signal line G2 of the next row through the storage capacitance element (auxiliary capacitance element) C11 to Cmn, respectively.
To Gm + 1. Therefore, the number of gate signal lines G1 to Gm + 1 is an even number (hence, m is an odd number), and the last gate signal line Gm + 1 is the one to which only the storage capacitor elements Cm1 to Cmn of the last row are connected. Become. Note that the drain electrodes D of the transistors T11 to Tmn may be connected to the data signal lines, and the source electrodes thereof may be connected to the pixel electrodes.

The number of gate signal lines G1 to Gm + 1 in the active matrix array of this embodiment is 480 (thus, m
= 479), and the number of data signal lines S1 to Sn is 1920 (hence, n = 1920). Therefore, the number of thin film field effect transistors T11 to Tmn, pixel electrodes P11 to Pmn, and storage capacitors C11 to Cmn is It becomes 919680 pieces each. Since such an active matrix array having a number of elements close to one million is constructed on a large glass substrate, the wiring of each signal line is extremely long, and furthermore, in order to realize a liquid crystal display with high light transmittance. Since the ratio of the pixel electrode needs to be increased, the area of the wiring portion is small. Therefore, each wiring (signal line) is extremely thin, and its width is usually several tens μm. Further, the distance between the signal line and the pixel electrode is extremely small in order to enlarge the pixel electrode to the limit, and is usually about several tens μm. As a result, in addition to the leak between the signal lines, a leak (short circuit) between the signal line and the pixel electrode easily occurs, and the signal line is easily broken. Recently, active matrix arrays for high-definition televisions have been actively developed, and some active matrixes for high-definition televisions have a number of elements close to two million. The distance between them is further narrowed, and leakage between signal lines, leakage between signal lines and pixel electrodes, disconnection of signal lines, and the like are more likely to occur.

The gate signal lines G1 to Gm + 1 and the data signal lines S1 to Sn are separated and taken out, and every other gate signal line G1 to Gm + 1 is taken out (alternately) to the opposite side. . That is, the odd-numbered gate signal lines G1, G3
.. Gm are drawn out to the left in the row direction, and the even-numbered gate signal lines G2, G4... Gm + 1 are drawn out to the right in the row direction.

The odd-numbered gate signal lines G1 to Gm, the even-numbered gate signal lines G2 to Gm + 1 drawn to each side of the active matrix array, and in this example, the data signal lines S1 to S1 drawn to the same side. Sn extraction terminals (bonding pads) PG1 to PGm, PG2 to PGm + 1, and PS1 to PSn are short buses SBG1, SBG2 for the corresponding gate signal lines formed on the respective sides, and data buses for the data signal lines. Each is connected to the short bus SBS1. In this embodiment, in order to facilitate the measurement, the output terminals of the respective signal lines are denoted by P G1, P G3..., P G2, P G4.
, And terminals (bonding pads) pg1, pg3 ..., pg2, pg4 at the opposite ends of PS1, PS2 ...
, And ps1, ps2,... Are provided, but these terminals pg1 to pgm, pg2 to pgm + 1, and ps1 to psn are not necessarily formed.

Next, a method of inspecting the active matrix array configured as described above will be described. FIG. 2 is a schematic configuration diagram schematically showing the basic configuration of the active matrix array inspection device of the present embodiment. The active matrix array 10 having the configuration shown in FIG. 1 is immersed in a solution 11 containing a voltage-sensitive dye. In this case, the active matrix array 10 is immersed in a solution 11 containing a voltage-sensitive dye with the circuit pattern forming surface thereof facing upward. In this example, as a voltage-sensitive dye, a styryl-like compound electrochromic dye that changes from colorless to red when a predetermined voltage is applied was used, and an electrochromic (EC) solution was configured with the supporting electrolyte and an organic solvent. Other electrochromic dyes used in an electrochromic display device (ECD) may be used, and other dyes that change color by application of a voltage can also be used. Since the electrochromic dye is known, its description is omitted, but the color is formed / decolored due to the difference in light absorption characteristics between the oxidized state and the reduced state, and both states are switched by an electrochemical reaction.

Normally, a solution containing an electrochromic dye is filled between a pair of electrodes facing each other at an interval of about 50 μm, and the electrochromic dye develops / decolors depending on the potential between the electrodes. Since the circuit pattern of the active matrix array is formed on a flat surface, the present invention relates to a circuit pattern in which a solution containing an electrochromic dye is applied to the circuit pattern forming surface of the active matrix array and wired with a gap of several tens μm or less. Alternatively, attention is paid to the fact that when a voltage is applied between the electrode and the electrode, the electrochromic dye in the gap portion develops / discolors, and this change in color is converted into an electric signal by a color imaging unit which is an optical-electric conversion unit. After conversion, the color image is used to detect a defective transistor, a defective pixel, a disconnection of a signal line, a short circuit or a leak, and to specify a defective position.

First, even-numbered gate signal lines G2 to Gm + 1 are collectively connected in order to collectively detect defects in the odd-numbered gate signal lines, thin film transistors, pixel electrodes, and storage capacitors. An AC voltage (pulse signal) Vsig for charging is applied to the short bus SBG2 for the gate signal line, and the thin-film transistors T11 to T1n, T31 to T3n,.
mn drain electrodes D are pixel electrodes P11 to P1n, P31 to P3
,... Cm1 to Cmn are charged through the storage capacitors C11 to C1n, C31 to C3n,. This charging AC voltage Vsig is supplied to the pulse generator 1
2, which is an AC pulse signal that changes positively and negatively with the ground potential (0 V) as a reference potential. As shown in FIG. 1, a short bus SBS1 for the data signal line and a short bus for the even-numbered gate signal line. Applied between the buses SBG2.
On the other hand, a bias voltage (pulse signal) Vg is applied to the gate signal line short bus SBG1 to which the odd-numbered gate signal lines G1 to Gm of the active matrix array 10 are collectively connected, and these thin film transistors T11 to Tg are applied.
1n, T31 to T3n,... Tm1 to Tmn are made conductive. The bias voltage Vg is a pulse-like signal synchronized with the AC voltage Vsig for charging the storage capacitor, and is also generated from the pulse generator 12, and as shown in FIG. 1, the short bus SBS1 for the data signal line is grounded. The potential is applied to the odd-numbered short bus SBG1 for the gate signal line.

As a result, the thin film transistors T11 to T1
n, T31 to T3n,..., Tm1 to Tmn are turned on, the storage capacitors C11 to C1n, C31 to C3n,... Cm1 to Cmn are charged to a predetermined voltage, and the pixel electrodes P11 to P1n,
.., Pm1 to Pmn include these storage capacitors C11 to C1n,
C31 to C3n,... Since an alternating voltage Vsig that repeatedly changes positively and negatively is applied via Cm1 to Cmn,
The electrochromic dye existing in the gap of μm or less repeats coloring / decoloring. Therefore, some defects can be found by observing the color image of the circuit pattern forming surface of the active matrix array.However, as described above, the thin film transistors, pixel electrodes, and signal lines are very densely arranged. Accurate judgment with the naked eye is difficult.

Therefore, the active matrix array 10
The color change due to the electrochemical reaction of the electrochromic dye on the circuit pattern forming surface, that is, the color image is converted into color image pickup means 13 such as a photodiode array or a CCD camera.
The image is taken out in the memory 1 and taken out as a change in the electric signal.
4 is stored. In this case, the color imaging means 13 takes time-series data (voltage value data corresponding to the state of color development at the observation point) for each observation point of the color image of the active matrix array 10 for each pixel of the color imaging means 13. Is stored in the memory 14. Of course, the entire surface on which the circuit pattern of the active matrix array 10 is formed may be scanned by the color imaging unit 13 and data extracted in time series may be stored in the memory 14 for each pixel of the color imaging unit 13, In addition, unnecessary images are also stored in the memory 14, so that the memory capacity is increased. Therefore, in the present embodiment, necessary observation points of the color image of the active matrix array 10, for example, near the connection between the thin film transistor and the data signal line and the gate signal line, near the intersection of the data signal line and the gate signal line, Peripheral portions and the like close to the electrode signal lines are determined in advance, and data obtained by capturing color images of these observation points and extracting them in time series are stored in the memory 14. This allows you to retrieve the data you need,
Moreover, the memory capacity does not need to be very large.

In the change amount detecting means 15, the memory 14
Are stored in the storage capacitors C11 to C1n and C31.
To C3n,... AC voltage Vsig applied to Cm1 to Cmn
The data is taken out in synchronization with the data and supplied to the two-dimensional display device 17 for display. The display color image of the two-dimensional display device 17 and an expected value pattern obtained when the same bias voltage and AC voltage are applied to a reference substrate having no defect and having the same circuit pattern as the active matrix array of FIG. (Color image) 16 is superimposed and compared for each pixel, and a defect portion of the active matrix array is detected by an observer's eyes. In this case, a defective portion can be detected by superimposing the detected color image of the active matrix array and the expected value pattern 16 as they are (overall), but it is clearer to superimpose and compare each pixel. Defective parts can be detected with high accuracy. Also, an output (print) indicating the defect position is displayed from the display device 17.
By generating 18, it is possible to know exactly what kind of defect exists at which position. Next, in order to detect defects in the even-numbered gate signal lines, the thin film transistors, the pixel electrodes, and the storage capacitor elements, the odd-numbered gate signal lines G1 to Gm are collectively connected to the short bus for the gate signal lines. An AC voltage (pulse signal) Vsig for charging is applied to SBG1, and these thin film transistors T21 to
T2n, T41 to T4n,... T (m-1) 1 to T (m-1) n have drain electrodes D of pixel electrodes P21 to P2n, P41 to P4n,.
Storage capacitance elements C21 to C2n, C41 to C4n connected via (m-1) 1 to P (m-1) n, ..., C (m-1) 1 to C (m-1) n Charge. On the other hand, a bias voltage (pulse signal) Vg is applied to the short bus SBG2 for the gate signal lines to which the even-numbered gate signal lines G2 to Gm + 1 of the active matrix array 10 are collectively connected, and these gate signal lines are Thin film transistors T21 to T2n, T41 to T4n,... T (m-1) 1 to T (m) having gate electrodes connected to G2 to Gm + 1.
-1) Make n conductive. Subsequent processing is the same as that for the odd-numbered rows described above, and a description thereof will be omitted. Incidentally, after the data of the odd-numbered rows and the even-numbered rows are stored in the memory 14, the processing after the change amount detecting means 15 may be collectively performed.

Next, application timings of the gate bias voltage Vg and the AC voltage Vsig will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 3 shows a thin film transistor T11 in which a gate electrode G and a source electrode S are connected to a gate signal line G1 and a data signal line S1, and a pixel electrode P connected to a drain electrode D of the thin film transistor T11.
11 shows the storage capacitor C11 connected to the pixel electrode P11. Gate bias pulse Vg
Denotes a short bus SBG1 (not shown) for a gate signal line,
The AC signal pulse Vsig is applied to the gate electrode G through the takeout terminal PG1 and the gate signal line G1, while the storage capacitor C is supplied through the short bus SBG2 (not shown) for the gate signal line and the takeout terminal PG2 and the gate signal line G2.
11 is applied.

Here, as shown in FIG. 4, a gate bias pulse Vg for making the thin film transistor T11 conductive is provided.
Is an AC signal pulse V for charging the storage capacitor C11.
It is applied in synchronization with the negative peak of sig. Therefore,
When the thin film transistor T11 is turned on, the potential on the pixel electrode side of the storage capacitor C11 becomes equal to the source potential of the transistor T11 (accordingly, the ground potential), and the storage capacitor C11 is charged to the voltage Vp of the negative peak value of the input AC signal pulse Vsig. Is done. When the input AC signal pulse Vsig passes the negative peak, the transistor T11 is turned off, so that the charge stored in the storage capacitor C11 is held without being discharged. Therefore, the charging voltage Vp of the storage capacitor C11 is applied to the pixel electrode P11.
A voltage in which the input AC signal pulse Vsig is superimposed on (DC component potential) is applied. That is, the charging voltage of the storage capacitor element C11 periodically changes negatively and positively according to the input AC signal pulse Vsig, and the electrochromic dye existing in the gap around the pixel electrode P11 develops color accordingly. / Decoloring will be repeated. Note that the voltage Vp in the waveform indicating the pixel electrode potential in FIG. 4 indicates a DC voltage component of the pixel electrode potential. In this embodiment, a 1 MHz AC signal pulse was used as Vsig, and a good result was obtained.
The frequency of the AC signal Vsig is not limited to this, and any frequency may be used as long as the change in the coloring / decoloring of the electrochromic dye can be detected.

Since each pixel electrode and each storage capacitor are independent, even if they are commonly controlled or charged through a gate signal line or a common signal line to which one end of the storage capacitor is connected, completely independent voltages are obtained. This will occur at the pixel electrode. The AC signal for charging the storage capacitor is not limited to the pulse signal, but may be a sine wave signal,
It goes without saying that a triangular wave signal or the like may be used. In addition, as shown in FIG.
A synchronization signal pulse Vsc synchronized with the sig is generated and supplied to the change amount detection means 15 to change the change amount detection means 1.
By using the data stored in the memory 14 as a synchronizing signal in step 5, an error component due to the flow of liquid or the like can be removed, and color development / decoloration due to voltage application can be clearly separated and detected.

Although the charging voltage of the storage capacitor is periodically changed by periodically changing the voltage polarity of the AC signal pulse applied to the storage capacitor in the above embodiment, the phase of the AC signal pulse is changed periodically. The change such as periodically changing the charging voltage of the storage capacitor element in place of the above is arbitrary. Defects detected by generating a voltage that periodically changes in a non-contact manner in each pixel electrode in this manner will be described for each case with reference to FIGS.

FIG. 5 shows a gate bias pulse Vg for conducting a thin film transistor and a charge of a storage capacitor in the active matrix array having the structure shown in FIG. 1 as shown in FIG. 4 by the inspection apparatus having the structure shown in FIG. FIG. 4 is a diagram schematically showing a state when the AC signal pulse Vsig is applied in synchronization. As described above, first, the gate bias pulse Vg is applied to the odd-numbered (or even-numbered) gate signal lines, and the AC signal pulse Vsig is applied to the even-numbered (or odd-numbered) gate signal lines. The thin-film transistors in the row (or even-numbered row) conduct, and the pixel electrode has a periodically and negatively and positively varying voltage in which an AC signal pulse Vsig is superimposed on the voltage charged in the storage capacitor (for convenience, the average value is Vp). Is applied),
No voltage is applied to the pixel electrodes in the even rows (or the odd rows).

First, the potential difference around pixel electrodes in odd rows to which the voltage Vp is applied will be considered. The potential difference between the side (shown by a double solid line) on the side close to the gate signal line to which the gate bias pulse Vg is applied is Vp-Vg when the bias pulse Vg is applied, and Vp at other times.
p. The potential difference between two sides (shown by dotted lines) on the side close to the data signal line is Vp since the data signal line is always at 0V. Further, the remaining side (shown by a solid line) on the side close to the gate signal line to which the AC signal pulse Vsig is applied becomes Vp-Vsig.

Next, when the voltage Vp is not applied,
Considering the potential difference around the pixel electrodes in the even-numbered rows of V, the potential difference on the side (indicated by a dashed line) on the side close to the gate signal line to which the AC signal pulse Vsig is applied is Vsi
g. Further, the potential difference between two sides (shown by dotted lines) on the side close to the data signal line is 0V. Further, the remaining sides (shown by thick solid lines) on the side close to the gate signal line to which the bias pulse Vg is applied become Vp-Vg when Vg is applied and Vp at other times.

Since the gap between the periphery of each pixel electrode and the signal line, that is, the gap, is several tens μm or less, when an electrochromic dye which develops a color when a predetermined voltage is applied is used, the predetermined voltage is reduced. The electrochromic dye in the applied gap develops color, and the electrochromic dye in the unapplied gap does not. Therefore, it can be understood that the electrochromic dye in the gap around each pixel electrode develops / decolors in accordance with the potential difference, and a color image is formed.

From the above description, the state where the data signal line is not connected, the state where the gate signal line is not connected, the state where the transistor is not conducting,
In the state where the pixel electrode and the peripheral wiring are short-circuited, and in the state where there is no storage capacitor, no charge is charged in the storage capacitor element, so that it is understood that the voltage Vp is not generated in the pixel electrode. Therefore, when the color does not change around the pixel electrode to which the voltage is applied, it can be understood that one of the above five defects exists.

More specifically, 1) a case where the gate signal line to which the gate bias pulse Vg is applied is disconnected in the middle. In this case, the transistor to which the bias pulse Vg is applied becomes conductive, so that the voltage Vp is generated at the pixel electrode up to that point, and the voltage Vp is not generated at the break point. Therefore, since a change appears in the potential gradient around the pixel electrode, it can be determined at which address position the gate signal line is disconnected. 2) The data signal line is disconnected. In this case, as in the case of the disconnection of the gate signal line, the transistors up to the portion where there is no disconnection conduct, so that the voltage Vp is applied to the pixel electrode up to that point.
Occurs, and no voltage Vp is generated at the point where the wire is disconnected. Therefore, since a change appears in the potential gradient around the pixel electrode, it is possible to determine at which address position the data signal line is disconnected. 3) When the transistor does not function. In this case, no voltage Vp is generated at the pixel electrode connected to the defective transistor. Therefore, a change appears in the potential gradient around the pixel electrode to which the defective transistor is connected, so that it can be detected as a point defect on the substrate. Also, the address can be specified. 4) When the gate signal line and the pixel electrode are short-circuited. In this case, the pixel electrode has the same potential as the short-circuited gate signal line, and the pixel electrode has no potential difference only on the short-circuited side, so that the detected peripheral contour pattern of the pixel electrode is missing. Therefore, it can be detected as a short circuit between the gate signal line and the pixel electrode, and the address can be specified. 5) When the data signal line and the pixel electrode are short-circuited. In this case, the same phenomenon as the short-circuit between the gate signal line and the pixel electrode in the above item 4) is exhibited. That is, since the potential difference disappears only on the short-circuited side of the pixel electrode, the detected peripheral contour pattern of the pixel electrode is missing. Therefore, it can be detected as a short circuit between the data signal line and the pixel electrode, and the address can be specified. 6) When the storage capacity is missing. In this case, the voltage Vp is not applied to the pixel electrode, and a change appears in the potential gradient around the pixel electrode, so that the pixel electrode can be detected as a point defect. Also, the address can be specified. 7) When the storage capacitor element is short-circuited. In this case, the same phenomenon as the short circuit between the gate signal line and the pixel electrode in the above item 4) is exhibited.

As described above, according to the present invention, the color development of a voltage-sensitive dye such as an electrochromic dye /
A color image formed on the active matrix array by decoloring is picked up by a color image pick-up means, and various defects of the active matrix array are detected based on the color image.
This eliminates the need to individually apply a voltage to the book, and eliminates the need to accurately apply many needles to the minute extraction terminals for probing. In addition, since a voltage can be applied collectively to a circuit pattern, a thin film transistor, a pixel electrode, and a storage capacitor element formed in an active matrix array, various defects can be collectively known based on a color-developed state of a voltage-sensitive dye. . In addition, since a voltage that repeatedly changes between positive and negative is used as a voltage for charging the storage capacitor, the voltage-sensitive dye causes oscillation of coloring / decoloring,
Since it is possible to detect the response amplitude of the portion to which the voltage is applied, it is possible to remove unnecessary interference components.
Further, data is extracted in time series for each observation point, and the time-series observation value is synchronized with the applied voltage, so that the color change state can be reliably detected and the S / N ratio is improved. In addition, since the color image formed on the active matrix array can be detected with the resolution of the color imaging means, the color image can be detected in a unit much smaller than the circuit unit of the active matrix array, and the detection resolution is improved. improves. Thus, according to the present invention, detection of a defective transistor in an active matrix array in which a signal line is short-circuited by a short bus and identification of its position, detection of a defect between a storage capacitor element and a signal line, and identification of its position are, of course, performed. , The disconnection of the signal line, the leak between the signal lines or between the signal line and the pixel electrode, the leak of the transistor, the defect of the pixel electrode, the defect of the storage capacitor element, etc. in a non-contact and accurate,
In addition, the defect can be easily detected, and the defect detection position can be accurately specified.

In the above embodiment, the present invention is applied to a case where a large number of gate signal lines and a large number of data signal lines are insulated from each other and arranged in rows and columns in a matrix at right angles, and a thin film transistor is provided at each intersection of these signal lines. Is connected to the gate signal line and the data signal line, the drain or source electrode of each thin film transistor is connected to one terminal of the pixel electrode, and the other terminal of each pixel electrode is connected to the next gate signal line immediately through the storage capacitor element And the gate signal line and the data signal line are separated and taken out, the take-out terminal of the data signal line is connected to the corresponding short bus for the data signal line, and the gate signal lines are alternately (alternately) alternately. Active matrix array of the type drawn out to the opposite side and separately connected to the short bus for each corresponding gate signal line Although the description has been given of the case where the present invention is applied, in the present invention, every other gate signal line is drawn out (alternately) in the same direction, and two short buses are formed almost in parallel on the same side. It goes without saying that the present invention can also be applied to an active matrix array in which gate signal lines drawn in the direction are connected to corresponding short buses for gate signal lines. In this case, of course, every other gate signal line connected to the outer gate signal line short bus is insulated from the inner gate signal line short bus.

A large number of gate signal lines and a large number of data signal lines are insulated from each other and arranged in rows and columns so as to be orthogonal to each other in a matrix form. Connected to a signal line, the drain or source electrode of each thin film transistor is connected to one terminal of a pixel electrode, and the other terminal of each pixel electrode arranged in the row direction is connected in parallel with the gate signal line through a storage capacitor. Each is connected to a communication line,
The gate signal line and the common signal line and the data signal line are separated and taken out, the take-out terminal of the data signal line is connected to the short bus for the corresponding data signal line, and the gate signal line and the storage capacitor are connected. Similarly, the active matrix array of the type which is drawn out in the opposite direction or the same direction as the common signal line and separately connected to the corresponding short buses for the gate signal lines and the common signal lines, respectively. Applicable.

FIG. 6 shows that the gate signal line, the common signal line and the data signal line are separated and taken out, and the take-out terminal of the data signal line is connected to the corresponding short bus for the data signal line. An active matrix array of a type in which the common signal line to which the storage capacitance element is connected is drawn out to the opposite side and separately connected to the corresponding short buses for the gate signal line and the common signal line, respectively. It is a block diagram which shows an example typically. Parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted unless necessary.

As shown in the figure, this active matrix array has a large number of gate signal lines G1, G2,... Arranged in parallel in a row (horizontal) direction at a predetermined interval, and a column ( A number of data signal lines S 1, S 2,... Arranged in parallel in the (vertical) direction and rows (horizontal) at predetermined intervals
The same number of common signal lines CS1, CS2,... As the number of gate signal lines wired in parallel in the direction are provided, and these gate signal lines, data signal lines, and common signal lines wired in a matrix are insulated from each other, In orthogonal state.

At the intersections of the gate signal lines and the data signal lines, thin film transistors (field effect transistors in this embodiment) T11, T12,... Are provided, and the gate electrode of each thin film field effect transistor has a corresponding gate. A signal line and its source electrode are connected to corresponding data signal lines, respectively, and its drain electrode D is connected to pixel electrodes P11, P11 arranged in a rectangular region inside both signal lines.
12 are connected to one terminal. These pixel electrodes are arranged in a matrix, and the other terminals of the pixel electrodes are connected to common signal lines CS1, C2 through storage capacitance elements (auxiliary capacitance elements) C11, C12,.
S2,... Respectively. Therefore, a transistor, a pixel electrode, and a storage capacitor are substantially connected between one gate signal line and one common signal line. Note that the drain electrode D of each transistor may be connected to the data signal line, and its source electrode may be connected to the pixel electrode.

The gate signal line, the common signal line, and the data signal line are separated and taken out, respectively, and the gate signal line and the common signal line are led out to the opposite sides in the row direction. That is, the gate signal lines G1, G2,... Are drawn to the left in the row direction, and the common signal lines CS1, CS2,. Note that the data signal line S
.. Are drawn in the same direction (downward in the figure).

The gate signal lines G1, G2,..., Common signal lines CS1, CS2,.
,..., PC,
, And PS1, PS2,... Are respectively connected to the corresponding short bus SBG1 for the gate signal line, the short bus SBC1 for the common signal line, and the short bus SBS1 for the data signal line. You.

The other configuration is the same as that of FIG. 1 and the description is omitted. 6, the gate signal lines G1, G2,... Of the active matrix array 10 are used to detect defects in the gate signal lines, thin film transistors, pixel electrodes, and storage capacitors during measurement. A bias voltage (pulse signal) Vg is applied to the short bus SBG1 for the gate signal line connected collectively to make the thin film transistors T11 to Tmn conductive. As shown in FIG. 6, the bias voltage Vg is applied to the short bus SBG1 for the gate signal line using the short bus SBS1 for the data signal line as the ground potential. On the other hand, the drain electrodes D of the thin film transistors T11 to Tmn are connected to the pixel electrodes P11 to Pmn.
The common signal lines CS1, CS2,... are connected together to charge the storage capacitance elements C11 to Cmn connected via the mn.
Is applied with a charging AC voltage (pulse signal) Vsig. The charging AC voltage Vsig is equal to the ground potential (0 V).
Is a positive and negative AC pulse signal that changes with the reference potential, and is applied between the short bus SBS1 for the data signal line and the short bus SBC1 for the common signal line as shown in FIG.

The following processing is the same as that of the first embodiment, so that the description is omitted. In the case of the active matrix having the structure shown in FIG. 6, the gate bias pulse Vg and the AC signal pulse Vsig are switched and applied. Therefore, it is possible to detect various defects of the active matrix array at one time. It is apparent that the same operation and effect as those of the first embodiment can be obtained in the present embodiment, and the description thereof is omitted. However, the present invention draws the gate signal line and the common signal line in the same direction. Two short buses are formed substantially parallel to the same side, and the gate signal line and the common signal line drawn in the same direction are connected to the corresponding short buses for the gate signal line and the common signal line, respectively. It goes without saying that the present invention can be applied to an active matrix array.

The above embodiment is merely an exemplification of the present invention, and is not limited to the configuration, structure, and connection mode of the illustrated active matrix array. For example, a thin film transistor is not necessarily limited to a field effect transistor. When a bipolar thin film transistor is used, a base electrode is connected to a gate signal line, a collector (or emitter) electrode is connected to a pixel electrode, and an emitter (or A (collector) electrode is connected to the data signal line. Therefore, in this specification, the gate electrode is generally referred to as a gate signal line. For example, in the case of a bipolar transistor, the base electrode is connected to the gate signal line. Further, the circuit configuration and connection mode of the inspection apparatus, the mode of extracting the color image formed on the circuit pattern forming surface of the active matrix array, the mode of detecting the extracted data, and the like are not limited to those of the embodiment, and may be changed as necessary. Needless to say, various changes and modifications are possible.

Further, the present invention is not limited to the active matrix array, and can be applied to, for example, detection of disconnection or short circuit of a signal line of a circuit pattern formed on a printed circuit board or the like. For example, when the gap between two adjacent signal lines is several tens μm or less, as described above, a solution containing a voltage-sensitive dye is applied to the circuit pattern formation surface and a voltage is applied to these signal lines. Disconnection, short circuit, etc. can be detected. In particular, when signal lines are formed in a comb shape from the opposite sides of the substrate or alternately with a gap of several tens μm or less, it becomes easy to apply a voltage to these signal lines at once, so
Detection of a short circuit or the like can be performed collectively.

The inspection method of the present invention using the voltage-sensitive dye can also be applied to the detection of a defect or the like in an insulating thin film. For example, when detecting pinholes in an insulating thin film of a material in which an insulating thin film is applied to a conductive material, the entire material is immersed in a liquid containing a voltage-sensitive dye, and the conductive portion and a separate material immersed in the liquid When a voltage is applied between the electrodes, a potential difference occurs in the pinhole portion of the insulating thin film, which changes the color of the voltage-sensitive dye. Can be detected.

[0056]

As described above, according to the present invention, the color image of the voltage-sensitive dye formed / decolored attached to the circuit pattern forming surface of the active matrix array in which the signal lines are short-circuited by the short bus. Is picked up by a color image pickup means, and various defects of the active matrix array are detected based on the color image. It can be known collectively by the coloring state of the dye. In addition, since it is not necessary to individually apply a voltage to each of the wires as in the related art, it is not necessary to accurately apply many needles to the minute extraction terminals for probing. In addition, since a voltage that repeatedly changes between positive and negative is used as a voltage for charging the storage capacitor, the voltage-sensitive dye causes oscillation of coloring / decoloring, and the reaction amplitude of the portion to which the voltage is applied is detected. Therefore, unnecessary interference components can be removed. Further, data is extracted in time series for each observation point, and the time-series observation value is synchronized with the applied voltage, so that the color change state can be reliably detected and the S / N ratio is improved. In addition, since the color image formed on the active matrix array can be detected with the resolution of the color imaging means, the color image can be detected in a unit much smaller than the circuit unit of the active matrix array, and the detection resolution is improved. There are many remarkable effects such as improvement.

[Brief description of the drawings]

FIG. 1 is a configuration diagram schematically showing an example of an active matrix array to which the present invention can be applied.

FIG. 2 is a configuration diagram schematically showing a basic configuration of an embodiment of an active matrix array inspection apparatus according to the present invention.

FIG. 3 is a circuit diagram for explaining an operation mode in which a voltage is applied to a pixel electrode of an active matrix by the inspection device of the present invention.

FIG. 4 is a timing chart showing a time relationship among a gate bias pulse, a charging AC signal pulse, and a pixel electrode potential generated by the inspection device of the present invention.

FIG. 5 is a diagram for explaining a potential difference between a pixel electrode to which a voltage is applied, a pixel electrode to which a voltage is not applied, and a signal line around the pixel electrode;

FIG. 6 is a configuration diagram schematically showing another example of an active matrix array to which the present invention can be applied.

FIG. 7 is a schematic configuration diagram for explaining a conventional active matrix array inspection apparatus and method.

[Explanation of symbols]

G1 to Gm + 1 Gate signal line S1 to Sn Data signal line T11 to Tmn Thin-film field-effect transistor P11 to Pmn Pixel electrode C11 to Cmn Storage capacitance element P G1 to G psn
Extraction terminal (bonding pad) SBG1, SBG2 Short bus for gate signal line SBS1 Short bus for data signal line CS1 to CSm Common signal lines PC1 to PCm, pC1 to pCm Extraction terminal (bonding pad) SBC1 Short for common signal line Bus 10 active matrix array 11 solution containing voltage sensitive dye 12 pulse generator 13 color imaging means 14 memory 15 change amount detection means 17 two-dimensional display device

Claims (2)

(57) [Claims] 1. A large number of gate signal lines and a large number of data signal lines are insulated from each other and arranged in rows and columns in a matrix at right angles. At each intersection of these signal lines, a thin film transistor forms a gate signal line and a data line. Connected to a signal line, the remaining electrode of each thin film transistor is connected to one terminal of a pixel electrode, the other terminal of each pixel electrode is connected to the next gate signal line through a storage capacitor, and the gate signal line The data signal lines are separated and taken out, the data signal lines are connected to corresponding short buses for data signal lines, and the gate signal lines are alternately drawn out in the opposite direction or in the same direction, An active matrix for inspecting defects of an active matrix array of a type separately connected to the short bus for each corresponding gate signal line In the array inspection apparatus, a liquid containing a voltage-sensitive dye is attached to the circuit pattern forming surface of the active matrix array, and the thin film transistor is connected to a gate signal line connected to one of the short buses for the gate signal line. A bias voltage is applied collectively, and an AC voltage for charging the storage capacitor is collectively applied to a gate signal line connected to the other short bus for the gate signal line. The color change state of the voltage-sensitive dye based on the charged voltage is imaged by color imaging means,
An active matrix array inspection device, wherein various defects of the active matrix array are detected based on the captured color image. 2. A large number of gate signal lines and a large number of data signal lines are insulated from each other and arranged in rows and columns in a matrix at right angles. At each intersection of these signal lines, a thin film transistor forms a gate signal line and a data line. A signal line, the remaining electrode of each thin film transistor is connected to one terminal of a pixel electrode, and the other terminal of each pixel electrode arranged in the row direction is connected in parallel with the gate signal line through a storage capacitor. Connected to a communication line, the gate signal line and the common signal line and the data signal line are separated and taken out, the data signal line is connected to a corresponding short bus for the data signal line, and the gate The signal line and the common signal line to which the storage capacitance element is connected are pulled out in opposite directions or in the same direction, and are respectively connected to the corresponding gate signal lines. An active matrix array inspection device for inspecting various defects of an active matrix array of a type separately connected to a short bus and a short bus for a common signal line, comprising a voltage-sensitive dye on a circuit pattern forming surface of the active matrix array. A bias voltage for conducting the thin film transistor was collectively applied to the gate signal lines connected to the short bus for the gate signal lines, and the liquid was connected to the short bus for the common signal lines. An AC voltage for charging the storage capacitance element is collectively applied to a common signal line, and a color change state of the voltage-sensitive dye based on the voltage charged in the storage capacitance element is imaged by color imaging means. Detecting defects of the active matrix array based on the captured color image An active matrix array inspection apparatus, characterized in that: