JPH0272392A - Inspecting and correcting method for active matrix type display device - Google Patents
Inspecting and correcting method for active matrix type display deviceInfo
- Publication number
- JPH0272392A JPH0272392A JP63222386A JP22238688A JPH0272392A JP H0272392 A JPH0272392 A JP H0272392A JP 63222386 A JP63222386 A JP 63222386A JP 22238688 A JP22238688 A JP 22238688A JP H0272392 A JPH0272392 A JP H0272392A
- Authority
- JP
- Japan
- Prior art keywords
- active matrix
- display device
- auxiliary capacitor
- repairing
- matrix display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims description 28
- 239000003990 capacitor Substances 0.000 claims abstract description 36
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000012360 testing method Methods 0.000 claims description 17
- 239000010408 film Substances 0.000 claims description 9
- 238000007689 inspection Methods 0.000 claims description 8
- 238000012937 correction Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 2
- 238000012790 confirmation Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 210000002858 crystal cell Anatomy 0.000 abstract description 14
- 230000002950 deficient Effects 0.000 abstract description 9
- 238000005259 measurement Methods 0.000 abstract description 4
- 230000007547 defect Effects 0.000 description 7
- 238000011156 evaluation Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000000523 sample Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000001182 laser chemical vapour deposition Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/1306—Details
- G02F1/1309—Repairing; Testing
Landscapes
- Engineering & Computer Science (AREA)
- Liquid Crystal (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Liquid Crystal Display Device Control (AREA)
- Thin Film Transistor (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は平面表示装置に係り、特に補助容量を有するア
クティブマトリクス型表示装置の検査及び修正方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flat display device, and more particularly to a method for inspecting and repairing an active matrix type display device having an auxiliary capacitor.
TPTなどのスイッチング素子と液晶あるいはエレクト
ロルミネッセンス等を組合せたアクティブマトリクスは
、+3 、 J 、 Lecherらが、プロシーディ
ング、アイ・イー・イー・イー・59 y’ 1566
(1971) (Proc、IEEE59.1566(
1971乃に発表されて以来、各種の方式について研究
が続けられ、液晶デイスプレィは実用化の段階に達した
。An active matrix that combines a switching element such as TPT with a liquid crystal or electroluminescence is described in +3, J. Lecher et al., Proceedings, I.E.E. 59 y' 1566
(1971) (Proc, IEEE59.1566(
Since its announcement in 1971, research has continued into various methods, and liquid crystal displays have reached the stage of practical use.
画素部の基本構成は、1画素に1個のTPTを設けて液
晶等を駆動する構造である。The basic configuration of the pixel section is such that one TPT is provided in one pixel to drive a liquid crystal or the like.
第8図に具体的な構成図を示す。ガラスのような透明の
アクティブマトリクス基板1に、多結晶シリコンあるい
は非晶質シリコンからなるTPTのスイッチング素子2
を各画素に配し、信号線3及び走査線4でマトリクス状
に接続する。このアクティブマトリクス基板1と対向基
板の共通電極5との間に液晶を封入して液晶セル6を形
成する。FIG. 8 shows a specific configuration diagram. A TPT switching element 2 made of polycrystalline silicon or amorphous silicon is mounted on a transparent active matrix substrate 1 such as glass.
are arranged in each pixel and connected in a matrix by signal lines 3 and scanning lines 4. A liquid crystal cell 6 is formed by sealing liquid crystal between the active matrix substrate 1 and the common electrode 5 of the counter substrate.
走査線4に順次信号を加え、信号線3に信号電圧を加え
、液晶セル6に電圧を加えて光の透過率を制御して表示
を行なう。Display is performed by sequentially applying signals to the scanning line 4, applying a signal voltage to the signal line 3, and applying a voltage to the liquid crystal cell 6 to control the light transmittance.
第9図は画素のスイッチング素子2近傍の断面形状を示
す。アクティブマトリクス基板1に例えば多結晶シリコ
ン7を形成し島状に加工する。ここにゲート絶縁膜8.
多結晶シリコンゲート9、トレイン電極11、ソース電
極12、絶縁膜10、透明電極13を形成して成る。FIG. 9 shows a cross-sectional shape near the switching element 2 of the pixel. For example, polycrystalline silicon 7 is formed on the active matrix substrate 1 and processed into an island shape. Gate insulating film 8.
A polycrystalline silicon gate 9, a train electrode 11, a source electrode 12, an insulating film 10, and a transparent electrode 13 are formed.
以上の様なアクティブマトリクス型液晶表示装置におい
て、例えば対角5インチの表示領域に約10万個のスイ
ッチング素子2と、約650本の走査線4と信号線3が
形成されている。この様な大型基板において、無欠陥を
達成するのは難しく、歩留りが問題となる。例えばTP
T素子に欠陥が発生した場合には点欠陥が発生する。ま
た、断線等が発生した場合には線欠陥が発生し、表示素
子としての商品価値を失う。In the active matrix type liquid crystal display device as described above, for example, about 100,000 switching elements 2 and about 650 scanning lines 4 and signal lines 3 are formed in a display area of 5 inches diagonally. In such large substrates, it is difficult to achieve defect-free production, and yield becomes an issue. For example, T.P.
When a defect occurs in the T element, a point defect occurs. Further, if a wire breakage or the like occurs, a line defect occurs and the commercial value as a display element is lost.
これらの欠陥の存在を知るには、アクティブマトリクス
基板に対向ガラスを積層し、液晶を封入してデイスプレ
ィの形状とした後、目視あるいは光学的測定により欠陥
の存在を知る方法がある。In order to know the existence of these defects, there is a method of laminating a counter glass on an active matrix substrate, sealing liquid crystal to form a display shape, and then visually or optically measuring the presence of the defects.
または特開昭57−38498号に記載されているよう
に、画素または配線に付いた寄生容量に蓄積された電荷
量の変化量を測定することにより、配線間の短絡等を検
出する方法等が提案されている。Alternatively, as described in Japanese Patent Application Laid-Open No. 57-38498, there is a method of detecting short circuits between wirings by measuring the amount of change in the amount of charge accumulated in the parasitic capacitance attached to pixels or wirings. Proposed.
上記第1の従来技術においては、欠陥の有無の判定はで
きるが、それを修正することは非常に難しい。また欠陥
液晶に対しては無駄な液晶工程を施したことになり、生
産性の低下の原因となる。In the first conventional technique, it is possible to determine the presence or absence of a defect, but it is very difficult to correct it. Moreover, a wasteful liquid crystal process is performed on defective liquid crystals, which causes a decrease in productivity.
また後者の方法は、液晶封入前にTPT基板を検査する
ことが可能であるが、基板内に存在する浮遊容量を用い
ていることなどにより、TPT特性まで正確に知ること
が不可能である。またTPT素子の特性を正確に知るた
めには、画素部の透明電極上に探針を接触せしめ、諸特
性を測定することが最も確実な方法であるが、表示画素
数が膨大なデイスプレィにおいては測定時間が長時間と
なり、また探針等の機械的な接触により表面に傷などを
生じせしめるため、実用的な方法とはいえない。In addition, although the latter method makes it possible to inspect the TPT substrate before filling the liquid crystal, it is impossible to accurately know the TPT characteristics because it uses stray capacitance existing within the substrate. In addition, in order to accurately determine the characteristics of a TPT element, the most reliable method is to bring a probe into contact with the transparent electrode of the pixel section and measure the various characteristics. However, in displays with a large number of display pixels, This is not a practical method because the measurement time is long and mechanical contact with the probe or the like causes scratches on the surface.
本発明の目的は、TPT基板が完成した時点で確実な検
査を可能とし、その不良モード、不良位置を判別できる
検査法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an inspection method that enables reliable inspection of a TPT board once it is completed, and that can determine the failure mode and position of the TPT substrate.
上記目的は、TPT基板に作り込まれた画素補助容量共
通電極を第3の測定端子として使うことによって達成さ
れる。The above object is achieved by using the pixel auxiliary capacitance common electrode built into the TPT substrate as the third measurement terminal.
補助容量はスイッチング素子に容量結合しており、スイ
ッチング素子を介してこの補助容量に充放電される電流
信号を観測することにより、確実にスイッチング素子及
びアクティブマトリクスの動作を評価することができる
。The auxiliary capacitor is capacitively coupled to the switching element, and by observing the current signal that is charged and discharged to the auxiliary capacitor via the switching element, the operation of the switching element and the active matrix can be reliably evaluated.
以下本発明の実施例を第1図〜第5図において説明する
。Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.
まず第1図に補助容量付アクティブマトリクス基板の基
本構成を示す。補助容量14が、液晶セル6と並列に配
置され、補助容量共通電極17で外部に引き出され電位
が固定されている。この構造において、液晶セル6に印
加された電圧は同時にも補助容量14にも書き込まれる
。通常補助容量14の静電容量は液晶セル6の数倍以上
と大きく、液晶セル6又はスイッチング素子2のリーク
電流を補償することから、液晶セル6に印加された電圧
を正常に保持し、表示品質の信頼性を高めることが知ら
れており、製品化された液晶表示装置にはこの補助容量
が形成されている。First, FIG. 1 shows the basic configuration of an active matrix substrate with auxiliary capacitance. An auxiliary capacitor 14 is arranged in parallel with the liquid crystal cell 6, and is drawn out to the outside by a auxiliary capacitor common electrode 17, and its potential is fixed. In this structure, the voltage applied to the liquid crystal cell 6 is simultaneously written into the auxiliary capacitor 14. Normally, the capacitance of the auxiliary capacitor 14 is several times larger than that of the liquid crystal cell 6, and it compensates for the leakage current of the liquid crystal cell 6 or the switching element 2, so that the voltage applied to the liquid crystal cell 6 is maintained normally and the display is displayed. This auxiliary capacitance is known to improve quality reliability, and commercialized liquid crystal display devices are provided with this auxiliary capacitance.
第2図は、スイッチング素子2の近傍の断面図を示す。FIG. 2 shows a cross-sectional view of the vicinity of the switching element 2. As shown in FIG.
TPT領域の構造は第9図とは同じであり、層間膜15
.補助容量透明電極16、補助容量共通電極17を有す
る点が特徴である。The structure of the TPT region is the same as that in FIG. 9, and the interlayer film 15
.. It is characterized by having an auxiliary capacitor transparent electrode 16 and an auxiliary capacitor common electrode 17.
第3図は本発明を実施するための、アクティブマトリク
ス基板評価法の概略構成を示す。垂直走査回路18、水
平走査回路19を介して走査線4及び信号線3、補助容
量共通電極17が評価装置に接続されている。接続には
プローブ法、フレキシブル配線等が用いられる。この構
成において、補助容量共通電極17に入力した電圧波形
により補助容量14に書き込まれる電流波形を、走査に
よりスイッチング素子2を切り替えながら評価すること
により、アクティブマトリクス基板の特性評価を行なう
ことができる。FIG. 3 shows a schematic configuration of an active matrix substrate evaluation method for carrying out the present invention. The scanning line 4, the signal line 3, and the auxiliary capacitor common electrode 17 are connected to the evaluation device via a vertical scanning circuit 18 and a horizontal scanning circuit 19. The probe method, flexible wiring, etc. are used for connection. In this configuration, the characteristics of the active matrix substrate can be evaluated by evaluating the current waveform written in the auxiliary capacitor 14 based on the voltage waveform input to the auxiliary capacitor common electrode 17 while switching the switching element 2 by scanning.
第4図は本発明による具体的なスイッチング素子の特性
評価法を示す。テスト電圧発生器21により、補助容量
14に電圧を印加する。この間にゲート電圧発生器22
によりゲートをオン状態とする。この信号に同期させて
流れる電流を電流測定器23で測定することにより、ス
イッチング素子2の特性を評価できる。FIG. 4 shows a specific method for evaluating characteristics of a switching element according to the present invention. A voltage is applied to the auxiliary capacitor 14 by the test voltage generator 21 . During this time, the gate voltage generator 22
turns the gate on. By measuring the current flowing in synchronization with this signal using the current measuring device 23, the characteristics of the switching element 2 can be evaluated.
第5図は第4図における具体的な電圧電流波形を示す。FIG. 5 shows specific voltage and current waveforms in FIG. 4.
(a)Vtは印加されるテスト電圧波形である。この電
圧が印加されている間に(b)Vaを印加するとTPT
のゲートがオン状態となる。(a) Vt is the applied test voltage waveform. When (b) Va is applied while this voltage is applied, TPT
gate is turned on.
この時流れる電流波形が(c)11の時は正常なTPT
動作を示している。(d)Izの場合、Vaがオフとな
っても電流が流れており、ソース・ドレイン間がショー
ト状態であることを示す。If the current waveform flowing at this time is (c) 11, it is normal TPT.
Showing operation. (d) In the case of Iz, current continues to flow even when Va is turned off, indicating a short-circuit between the source and drain.
(e)Iaの波形は電流が流れないことを示しており、
ソース・ドレイン間が開放状態、信号線又は走査線の断
線を示す。前者後者の分離は、複数のTPTを走査して
評価することで分離できる。(e) The waveform of Ia shows that no current flows,
Indicates an open state between the source and drain, or a break in the signal line or scanning line. The former and the latter can be separated by scanning and evaluating a plurality of TPTs.
例えば、又又はY方向に走査して連続して評価を行ない
、特定位置を境界として連続して(、)のモードが続い
た場合、その境界部分で断線があることがわかる。(Q
)〜(e)の具体的な判定は、X又はY点の電流値を比
較することで可能である。For example, if evaluation is performed continuously by scanning in the Y direction, and the (,) mode continues with a specific position as a boundary, it can be seen that there is a disconnection at the boundary. (Q
) to (e) can be specifically determined by comparing the current values at the X or Y points.
補助容量の層間膜耐圧が不良な場合は、テスト電圧によ
る(a)と同様な波形の大きな電流が流れることから、
この電流レベルを検出することができる。また信号線と
操作線のクロス部分の耐圧が不良の場合は、Vaに同期
した波形の大きな電流が流れるため、この電流レベルを
検出することで、その位置とともに検出できる。さらに
スイッチング素子2の保持特性は、補助容量を充電し。If the interlayer film breakdown voltage of the auxiliary capacitor is poor, a large current with a waveform similar to (a) will flow due to the test voltage.
This current level can be detected. Furthermore, if the withstand voltage at the intersection of the signal line and the operation line is defective, a large current with a waveform synchronized with Va flows, and by detecting this current level, it can be detected along with its position. Furthermore, the retention characteristic of the switching element 2 charges the auxiliary capacitor.
所定時間保持させた後再びスイッチング素子をオンさせ
、補助容量の電圧又は電流を評価することで検査できる
。なお、クロス部分の耐圧は、補助容量を介さなくても
評価は可能である。The test can be performed by turning on the switching element again after holding it for a predetermined time and evaluating the voltage or current of the auxiliary capacitor. Note that the withstand voltage of the cross portion can be evaluated without using an auxiliary capacitor.
以上め実施例においては、テスト電圧を補助容量共通電
極側から入れたが、逆に、信号線側からテスト電圧を入
れ、補助容量共通電極側から電流波形を観察しても良い
。またテスト電圧、電流波形も測定法、測定器、評価対
象によって任意に選択できる。In the above embodiments, the test voltage was applied from the auxiliary capacitor common electrode side, but it is also possible to apply the test voltage from the signal line side and observe the current waveform from the auxiliary capacitor common electrode side. Furthermore, the test voltage and current waveform can be arbitrarily selected depending on the measurement method, measuring instrument, and evaluation target.
次に第6図において、本発明の応用例を述べる。Next, referring to FIG. 6, an application example of the present invention will be described.
この例では表示部分を駆動するための垂直、水平回路が
、スイッチング素子と同一の透明基板に内蔵された場合
であり、この回路を評価に利用することを特徴とする。In this example, the vertical and horizontal circuits for driving the display portion are built into the same transparent substrate as the switching elements, and this circuit is characterized in that it is used for evaluation.
測定現理は第4図、第5図で述べた内容と同一であるが
、内蔵垂直走査回路24、内蔵水平走査回路25を使う
ことにより、評価装置20への外部接続数を減少でき、
検査効率を」二げることかできる。この場合も、テスト
信号は、補助容量共通電極側、内蔵水平走査回路側、い
ずれから入れても良い。また表示領域の駆動用の回路以
外に検査を容易にする補助回路、端子等を設けることも
有効である。例えば補助容量共通電極を複あつブロック
に分割しておき、これを走査するための回路を設けるこ
とができる。The measurement principle is the same as that described in FIGS. 4 and 5, but by using the built-in vertical scanning circuit 24 and built-in horizontal scanning circuit 25, the number of external connections to the evaluation device 20 can be reduced.
It is possible to increase inspection efficiency. In this case as well, the test signal may be input from either the auxiliary capacitor common electrode side or the built-in horizontal scanning circuit side. In addition to the circuit for driving the display area, it is also effective to provide auxiliary circuits, terminals, etc. to facilitate inspection. For example, the auxiliary capacitor common electrode can be divided into multiple blocks, and a circuit for scanning the blocks can be provided.
次に液晶表示装置以外の応用例としてエレクトロルミネ
ッセンス(E L)素子を第7図において示す。第2図
と同様MOS型のスイッチング素子のソース側透明電極
13の上に発光層26、上部透明電極27が形成され、
ELセル28が構成されている。この場合も液晶セルと
同様にアクティブマトリクス方式で駆動できる。また補
助容量を形成し、液晶セルと同様に表示の信頼性、安定
性を高めることができる。この例でも、第3〜第6図に
示した方法で同様な検査を実施することができる。Next, as an example of application other than liquid crystal display devices, an electroluminescent (EL) element is shown in FIG. Similar to FIG. 2, a light emitting layer 26 and an upper transparent electrode 27 are formed on the source side transparent electrode 13 of a MOS type switching element.
An EL cell 28 is configured. In this case as well, it can be driven using an active matrix method like a liquid crystal cell. In addition, by forming an auxiliary capacitor, it is possible to improve the reliability and stability of display in the same way as a liquid crystal cell. In this example as well, similar tests can be carried out using the methods shown in FIGS. 3 to 6.
以上述べた実施例では、スイッチング素子として多結晶
シリコンMO3FETについて述へたが、半導体材料、
スイッチング素子の構造に限定されるものではない。In the embodiments described above, a polycrystalline silicon MO3FET was described as a switching element, but semiconductor materials,
It is not limited to the structure of the switching element.
また、本発明によって得られた不良モード、不良位置を
基に、断線部の修理、ショート部の分離。Furthermore, based on the failure mode and failure position obtained by the present invention, broken wires can be repaired and short circuits can be separated.
不良スイッチング素子の切り離し、耐圧不良補助容量部
の絶縁化等の修正が可能である。たとえば、配線の切断
部はメタルのレーザCVD等により修復できる。クロス
部分のショートは、上部配線の除去、層間絶縁膜の局部
CVD、上部配線の再配線による接続の手段を踏むこと
により修複が可能である。不良スイッチング素子は、レ
ーザビーム、集束イオンビーム、電子ビーム等で切断分
離が可能である。耐圧不良の補助容量部は、不良部の透
明電極をレーザビーム等を使い環元除去する、又はさら
に局所的に絶縁膜を形成する等で修正できる。It is possible to make corrections such as separating the defective switching element and insulating the defective auxiliary capacitor with withstand voltage. For example, a cut portion of a wiring can be repaired by metal laser CVD or the like. A short circuit at the cross portion can be repaired by removing the upper wiring, local CVD of the interlayer insulating film, and connecting by rewiring the upper wiring. Defective switching elements can be cut and separated using a laser beam, focused ion beam, electron beam, or the like. An auxiliary capacitance section with a breakdown voltage defect can be corrected by removing the ring of the transparent electrode in the defective section using a laser beam or the like, or by forming an insulating film locally.
本発明によれば、表示装置基板の不良モード、不良位置
を特別な手段を新たに用いずに確実に検査できる。また
この結果、不良部分の修正も可能となる。According to the present invention, the failure mode and failure position of a display device substrate can be reliably inspected without using any special means. As a result, it is also possible to correct defective parts.
第1図、第3図、第6図は本発明を説明するためのアク
ティブマトリクス基板平面概念図、第2図は本発明を説
明するためのスイッチング素子近傍断面図、第4図は本
発明を実施するための測定回路図、第5図は本発明を説
明するためのテスト電圧、電流波形図、第7図は本発明
の応用例を示すスイッチング素子近傍断面図、第8図及
び9図は従来例を説明するためのアクティブマトリクス
基板平面概念図及びスイッチング素子近傍断面図を示す
。
1・・・アクティブマトリクス基板、2・・・スイッチ
ング素子、13・・・透明電極、14・・補助容量、1
5・・層間膜、16・・・補助容量透明電極、17・・
補助容量共通電極。
第
図
第4図
7丁
第5図
(e)
工3
第3図
第
図
第7図
2g1, 3, and 6 are conceptual plan views of an active matrix substrate for explaining the present invention, FIG. 2 is a cross-sectional view of the vicinity of a switching element for explaining the present invention, and FIG. FIG. 5 is a test voltage and current waveform diagram for explaining the present invention; FIG. 7 is a sectional view of the vicinity of a switching element showing an application example of the present invention; FIGS. 8 and 9 are A conceptual plan view of an active matrix substrate and a cross-sectional view of the vicinity of a switching element are shown for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Active matrix substrate, 2... Switching element, 13... Transparent electrode, 14... Auxiliary capacitor, 1
5...Interlayer film, 16...Auxiliary capacitance transparent electrode, 17...
Auxiliary capacitor common electrode. Fig. 4 Fig. 7 Fig. 5 (e) Fig. 3 Fig. 3 Fig. 7 Fig. 2g
Claims (1)
において、補助容量用共通電極を前記表示装置の検査用
電極として使うことを特徴とするアクティブマトリクス
型表示装置の検査方法。 2、第1項において、補助容量が画素電極と、独立した
単一又は複数の補助容量用電極で構成されたことを特徴
とするアクティブマトリクス基板の検査方法。 3、第1項または第2項において、表示装置が駆動回路
を内蔵していることを特徴とするアクティブマトリクス
型表示装置の検査方法。 4、第3項において、内蔵した駆動回路を検査手段とし
て使用することを特徴とするアクティブマトリクス型基
板の検査方法。 5、第1項、第2項、第3項または第4項において、検
査のための補助回路、端子等検査のための補助手段を有
することを特徴とするアクティブマトリクス基板の検査
方法。 6、第1項から第5項において、断線、ショート等の不
良モードとその位置を検出することを特徴とするアクテ
ィブマトリクス基板の検査方法。 7、アクティブマトリクス型表示装置において、クロス
部分ショートの修正を、上層導電体除去、絶縁膜修正、
上層導電体の再接続で行なうことを特徴とするアクティ
ブマトリクス型表示装置の修正方法。 8、アクティブマトリクス型表示装置において、補助容
量部のショートの修正をショート部上部電極の部分除去
、又はさらに絶縁膜の修正、又はさらに上部電極の再形
成で行なうことを特徴とするアクティブマトリクス型表
示装置の修正方法。 9、第7項、第8項の修正方法が、第6項の検査結果に
基づいて行なわれることを特徴とするアクティブマトリ
クス型表示装置の修正方法。 10、第1項から第9項におけるスイッチング素子が、
単結晶又は多結晶又は非晶質の半導体を使う薄膜トラン
ジスタであることを特徴とするアクティブマトリクス型
表示装置の検査及び修正方法。 11、第10項において、半導体がシリコンであること
を特徴とするアクティブマトリクス型表示装置の検査及
び修正方法。 12、第1項から第11項における表示装置が、液晶を
用いることを特徴とするアクティブマトリクス型表示装
置の検査及び修正方法。 13、第1項から第11項における表示装置が、ELを
用いることを特徴とするアクティブマトリクス型表示装
置の検査及び修正方法。 14、第1項から第13項の検査及び修正を行なつたこ
とを特徴とするアクティブマトリクス型表示装置。 15、第1項から第13項の検査、修正、修正確認の機
能を有することを特徴とするアクティブマトリクス型表
示装置の検査、修正装置。[Scope of Claims] 1. A method for testing an active matrix display device having an auxiliary capacitor, characterized in that a common electrode for the auxiliary capacitor is used as an electrode for testing the display device. 2. The method for inspecting an active matrix substrate according to item 1, wherein the auxiliary capacitor is composed of a pixel electrode and a single or plural independent auxiliary capacitor electrodes. 3. The method for inspecting an active matrix display device according to item 1 or 2, wherein the display device has a built-in drive circuit. 4. The method for testing an active matrix type substrate according to item 3, characterized in that a built-in drive circuit is used as a testing means. 5. The method for testing an active matrix substrate according to item 1, 2, 3, or 4, characterized by comprising an auxiliary circuit for testing, auxiliary means for testing terminals, etc. 6. A method for inspecting an active matrix substrate according to items 1 to 5, characterized in that failure modes such as disconnections and short circuits and their positions are detected. 7. In active matrix display devices, cross short circuits can be corrected by removing the upper layer conductor, repairing the insulating film,
A method for repairing an active matrix display device, characterized in that the repair method is performed by reconnecting an upper layer conductor. 8. An active matrix display device in which a short circuit in an auxiliary capacitance section is corrected by partially removing the upper electrode of the short section, further repairing the insulating film, or further re-forming the upper electrode. How to modify the device. 9. A method for repairing an active matrix display device, characterized in that the methods for repairing items 7 and 8 are performed based on the inspection results in item 6. 10. The switching elements in the first to ninth terms are
A method for inspecting and repairing an active matrix display device characterized by being a thin film transistor using a single crystal, polycrystalline or amorphous semiconductor. 11. The method for inspecting and repairing an active matrix display device according to item 10, wherein the semiconductor is silicon. 12. A method for inspecting and repairing an active matrix display device, wherein the display device according to items 1 to 11 uses liquid crystal. 13. A method for inspecting and repairing an active matrix display device, wherein the display device according to items 1 to 11 uses EL. 14. An active matrix display device characterized by having undergone the inspections and corrections described in Items 1 to 13. 15. An inspection and correction device for an active matrix display device, characterized by having the inspection, correction, and correction confirmation functions described in items 1 to 13.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63222386A JPH0272392A (en) | 1988-09-07 | 1988-09-07 | Inspecting and correcting method for active matrix type display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63222386A JPH0272392A (en) | 1988-09-07 | 1988-09-07 | Inspecting and correcting method for active matrix type display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0272392A true JPH0272392A (en) | 1990-03-12 |
Family
ID=16781548
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63222386A Pending JPH0272392A (en) | 1988-09-07 | 1988-09-07 | Inspecting and correcting method for active matrix type display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0272392A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5159477A (en) * | 1989-11-22 | 1992-10-27 | Sharp Kabushiki Kaisha | Active matrix display device having additional capacitors connected to switching elements and additional capacitor common line |
US5182661A (en) * | 1990-06-25 | 1993-01-26 | Nec Corporation | Thin film field effect transistor array for use in active matrix liquid crystal display |
US5208690A (en) * | 1990-03-24 | 1993-05-04 | Sony Corporation | Liquid crystal display having a plurality of pixels with switching transistors |
US5414278A (en) * | 1991-07-04 | 1995-05-09 | Mitsushibi Denki Kabushiki Kaisha | Active matrix liquid crystal display device |
EP0599623A3 (en) * | 1992-11-25 | 1995-08-02 | Sharp Kk | Inspecting method and apparatus for an active matrix substrate. |
US7639034B2 (en) | 2003-06-30 | 2009-12-29 | Sony Corporation | Flat display apparatus and flat display apparatus testing method |
JP2011215638A (en) * | 2000-05-12 | 2011-10-27 | Semiconductor Energy Lab Co Ltd | El display device |
JP2013257530A (en) * | 2012-06-12 | 2013-12-26 | Hannstar Display Corp | Liquid crystal display panel and pixel array substrate thereof |
KR20140113034A (en) * | 2013-03-15 | 2014-09-24 | 삼성디스플레이 주식회사 | Liquid crystal display |
EP2853940A4 (en) * | 2012-08-22 | 2016-05-18 | Toppan Printing Co Ltd | Electrophoretic display substrate, method for inspecting same, and electrophoretic display device |
-
1988
- 1988-09-07 JP JP63222386A patent/JPH0272392A/en active Pending
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5159477A (en) * | 1989-11-22 | 1992-10-27 | Sharp Kabushiki Kaisha | Active matrix display device having additional capacitors connected to switching elements and additional capacitor common line |
US5208690A (en) * | 1990-03-24 | 1993-05-04 | Sony Corporation | Liquid crystal display having a plurality of pixels with switching transistors |
US5182661A (en) * | 1990-06-25 | 1993-01-26 | Nec Corporation | Thin film field effect transistor array for use in active matrix liquid crystal display |
US5414278A (en) * | 1991-07-04 | 1995-05-09 | Mitsushibi Denki Kabushiki Kaisha | Active matrix liquid crystal display device |
EP0599623A3 (en) * | 1992-11-25 | 1995-08-02 | Sharp Kk | Inspecting method and apparatus for an active matrix substrate. |
JP2013029847A (en) * | 2000-05-12 | 2013-02-07 | Semiconductor Energy Lab Co Ltd | Display device |
JP2011215638A (en) * | 2000-05-12 | 2011-10-27 | Semiconductor Energy Lab Co Ltd | El display device |
JP2013228756A (en) * | 2000-05-12 | 2013-11-07 | Semiconductor Energy Lab Co Ltd | Display device |
JP2015148805A (en) * | 2000-05-12 | 2015-08-20 | 株式会社半導体エネルギー研究所 | display device |
JP2016194712A (en) * | 2000-05-12 | 2016-11-17 | 株式会社半導体エネルギー研究所 | EL display device |
KR101024621B1 (en) * | 2003-06-30 | 2011-03-25 | 소니 주식회사 | A flat display apparatus and the test method of a flat display apparatus |
US7639034B2 (en) | 2003-06-30 | 2009-12-29 | Sony Corporation | Flat display apparatus and flat display apparatus testing method |
JP2013257530A (en) * | 2012-06-12 | 2013-12-26 | Hannstar Display Corp | Liquid crystal display panel and pixel array substrate thereof |
EP2853940A4 (en) * | 2012-08-22 | 2016-05-18 | Toppan Printing Co Ltd | Electrophoretic display substrate, method for inspecting same, and electrophoretic display device |
US9874798B2 (en) | 2012-08-22 | 2018-01-23 | Toppan Printing Co., Ltd. | Electrophoretic display substrate, method of inspecting same, and electrophoretic display device |
KR20140113034A (en) * | 2013-03-15 | 2014-09-24 | 삼성디스플레이 주식회사 | Liquid crystal display |
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