JPS62151769A - Inspecting method for active matrix substrate - Google Patents

Inspecting method for active matrix substrate

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Publication number
JPS62151769A
JPS62151769A JP60295012A JP29501285A JPS62151769A JP S62151769 A JPS62151769 A JP S62151769A JP 60295012 A JP60295012 A JP 60295012A JP 29501285 A JP29501285 A JP 29501285A JP S62151769 A JPS62151769 A JP S62151769A
Authority
JP
Japan
Prior art keywords
potential
charging
active matrix
electrode
matrix substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60295012A
Other languages
Japanese (ja)
Inventor
Koichi Kasahara
笠原 幸一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60295012A priority Critical patent/JPS62151769A/en
Publication of JPS62151769A publication Critical patent/JPS62151769A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

PURPOSE:To inspect a short circuit and a leak between substrate electrodes easily and accurately by charging one electrode of an active matrix substrate at a specific potential based on the other electrode, and utilizing the difference between the potential in the charging and a potential which is certain time later. CONSTITUTION:Address lines Y1, Y2...Yn of the active matrix substrate 17 are connected in common to the negative electrode of a DC power source 22. A charging/measurement changeover switch 23 is placed on the side of the power source 22 to set a charging mode. Then, signal lines X1, X2...Xn are selected with a signal selection switch 18 for a certain time each and charged to the potential of the power source 22. The switch 23 is switched to the side of a potential measuring instrument 24 to set a measurement mode. The signal lines X1...Xn are selected with the switch 18 for a specific time each and their potentials are measured. In this measurement, even a slight leak between electrodes is measured as large potential variation, so a short circuit or slight leak between a signal line and an address line is inspected easily and securely according to how much the measured value decreases below said charging voltage.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明はスイッチ素子アレイが形成された表示装置用の
アクティブマトリクス基板の検査方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for inspecting an active matrix substrate for a display device on which a switch element array is formed.

[1明の技術的背景とその問題点] 最近、画像や図形表示などを指向した多画素の表示装置
として、液晶などを用いたアクティブマトリクス形表示
装置の開発が盛んである。この種の表示装置では、各画
素の輝度または点灯・非点灯を制御するためのスイッチ
素子アレイが形成されたアクティブマトリクス基板が用
いられる。
[1.Technical background and problems thereof] Recently, active matrix display devices using liquid crystals and the like have been actively developed as multi-pixel display devices for displaying images and graphics. This type of display device uses an active matrix substrate on which a switch element array is formed to control the brightness or lighting/non-lighting of each pixel.

第4図はスイッチ素子として薄膜トランジスタ(TPT
)を用いたアクティブマトリクス基板の電気的等価回路
図で、1はTPT、2は必要により設けられる信号蓄積
用キャパシタ、3は画素電極で透明導電膜などで形成さ
れ、TFTlのソースと電気的に接続されている。TF
TIのゲートは行毎に共通接続されてアドレス線Yr 
、Y2・・・Ynが設けられ、ドレインは列毎に共通接
続されて信@taXs 、X2・・・Xmが設けられる
。前記TFT1、キャパシタ2、画素電極3、アドレス
線および信号線は例えばガラス基板上に1躾技術を用い
て形成される。
Figure 4 shows a thin film transistor (TPT) as a switch element.
) is an electrical equivalent circuit diagram of an active matrix substrate using a TFT. It is connected. TF
The gates of TI are commonly connected for each row and connected to the address line Yr.
, Y2...Yn are provided, and the drains are commonly connected for each column, and signals @taXs, X2...Xm are provided. The TFT 1, capacitor 2, pixel electrode 3, address line, and signal line are formed, for example, on a glass substrate using a one-step technique.

第5図は上記のアクティブマトリクス基板を用いた表示
装置の一例として液晶表示装置の構造を説明するだめの
断面図である。同図において、4〜12はアクティブマ
トリクス基板の一例における各部材を示しており、4は
ガラス基板、5はクロムなどの金属で形成される光じゃ
へい、1を兼ねた接地電極、6は層間絶縁膜、7はTF
Tのドレイン電極兼信号線、8はTPTのソース電極兼
画素電極で、7および8はIT○などの透明導電膜で形
成される。9はアモルファスシリコンなどの半導体層、
10は窒化シリコンなどで形成されるゲート絶縁液、1
1はアルミニウムなどの金属で形成されるTPTのゲー
ト電極、12はポリイミドなどによる保護層である。前
記画素電極8と接地電極5の重なり部分が、第4図のキ
ャパシタ2を構成している。一方、13は透明導電膜を
用いた対向共通電極14が形成されたガラス基板である
。側基板4および13はその表面に液晶配向膜15が形
成された後、10μl程度の間隔を保って周辺部で封着
され、内部間隙に液晶16が封入されて液晶表示装置と
なる。
FIG. 5 is a cross-sectional view for explaining the structure of a liquid crystal display device as an example of a display device using the above active matrix substrate. In the same figure, 4 to 12 indicate each member in an example of an active matrix substrate, 4 is a glass substrate, 5 is a light shield made of metal such as chromium, a ground electrode also serves as 1, and 6 is an interlayer. Insulating film, 7 is TF
T is a drain electrode/signal line, 8 is a TPT source electrode/pixel electrode, and 7 and 8 are formed of a transparent conductive film such as IT◯. 9 is a semiconductor layer such as amorphous silicon,
10 is a gate insulating liquid made of silicon nitride, etc.;
1 is a TPT gate electrode made of metal such as aluminum, and 12 is a protective layer made of polyimide or the like. The overlapping portion of the pixel electrode 8 and the ground electrode 5 constitutes the capacitor 2 shown in FIG. On the other hand, 13 is a glass substrate on which a common electrode 14 made of a transparent conductive film is formed. After a liquid crystal alignment film 15 is formed on the surfaces of the side substrates 4 and 13, the peripheral portions are sealed with a gap of about 10 μl maintained, and a liquid crystal 16 is filled in the internal gap to form a liquid crystal display device.

第5図の液晶表示装置の動作は次のように行なわれる。The operation of the liquid crystal display device shown in FIG. 5 is performed as follows.

すなわち、第4図において、アドレス線Y1.Y2・・
・YnはYドライバからの走査信号により順次走査駆動
され、TFTlは行毎に順次導通状態にもたらされる。
That is, in FIG. 4, address lines Y1. Y2...
-Yn is sequentially scanned and driven by a scanning signal from a Y driver, and TFTl is brought into conduction state sequentially row by row.

上記走査と同期して信号線X1.X2・・→0にXドラ
イバからの表示信号電圧を例えば同時に供給すると、前
記表示信号電圧はキャパシタ2および液晶16の容量に
行毎に順次書込まれ、フレーム走査周期にわたって保持
される。この保持された表示信号電圧に応じて液晶16
が励起され、画像などの表示がなされる。
In synchronization with the above scanning, signal line X1. For example, when a display signal voltage from an X driver is simultaneously supplied to X2 . The liquid crystal 16 responds to this held display signal voltage.
is excited, and an image or the like is displayed.

ところで、前記信号線XI 、X2・・・X11とアド
レス線Y1.Y2・・・ynとの間あるいは信号線X1
.X2・・→0と接地電極との間などに電気的漏洩また
は短絡などが存在すると、表示に線状の欠陥を生ずる結
果となるためアクティブマトリクス基板が完成した時点
でこれらの検査が必要である。
By the way, the signal lines XI, X2...X11 and the address lines Y1... Between Y2...yn or signal line X1
.. If there is an electrical leak or short circuit between X2...→0 and the ground electrode, it will result in linear defects on the display, so these inspections are necessary when the active matrix board is completed. .

第6図はアクティブマトリクス基板の従来の検査方法を
説明するための図で、17は第4図で説明したアクティ
ブマトリクス基板、18は切換スイッチ(又は回路“)
、19は直流’Rm、20は電流計(又は電流測定回路
)、21は電流制限用の抵抗である。同図(a )はア
ドレス線Y1.Y2・・・Ynを共通接続し、これと信
号線Xt 、X2・・・xIllの夫々との間の電気的
漏洩電流または短絡電流を電流計(又は電流測定回路)
20で測定する検査方法を例示したものであり、同図(
b)は信号線Xt 、X2・・・X11の夫々と接地電
極との間の電気的漏洩電流又は短絡電流をN流計(又は
電流測定回路)20で測定する検査方法を例示したもの
である。
FIG. 6 is a diagram for explaining the conventional inspection method for active matrix boards, where 17 is the active matrix board explained in FIG. 4, and 18 is a changeover switch (or circuit).
, 19 is a direct current 'Rm, 20 is an ammeter (or current measuring circuit), and 21 is a current limiting resistor. Figure (a) shows the address line Y1. Connect Y2...Yn in common, and measure the electrical leakage current or short-circuit current between this and each of the signal lines Xt, X2...xIll using an ammeter (or current measurement circuit).
This is an example of the inspection method measured in 20, and the same figure (
b) is an example of an inspection method in which the electrical leakage current or short-circuit current between each of the signal lines Xt, X2...X11 and the ground electrode is measured using the N current meter (or current measuring circuit) 20. .

アクティブマトリクス基板を用いた表示装置においては
、成るアドレス徨が選択されている期間中、信号線への
表示信号電圧が常に供給されるとは限らず、アドレス選
択期間内の一部短時間に信号線容量を表示信号電圧まで
充電または放電する形式で表示信号電圧が供給され、ア
ドレス選択期間の残りの期間は信号線容量に保持された
表示信号電圧により、画素E1mへの書込みを行なわせ
ることもよくある。このような場合には、信号線と他電
極間とのわずかな漏洩も許されない。なぜならば、成る
アドレス線に沿った画素電極は、そのアドレス線が選択
されている期間中、TPTを介して夫々の信号線と接続
されているので、信号線に保持されている表示信号電圧
が前記漏洩により変化すると画素電極に正規の表示信号
電圧が書込めなくなるためである。このような電極間の
わずかな漏洩の有無は第6図で説明した従来の検査方法
では電流計の撮れが小さく、検査が困難であるという問
題があった。
In a display device using an active matrix substrate, the display signal voltage is not always supplied to the signal line during the period when the address selection period is selected; The display signal voltage is supplied in a form that charges or discharges the line capacitance to the display signal voltage, and during the remaining period of the address selection period, writing to the pixel E1m may be performed using the display signal voltage held in the signal line capacitance. It happens often. In such a case, even the slightest leakage between the signal line and other electrodes is not allowed. This is because the pixel electrodes along the address line are connected to the respective signal lines via TPT during the period when the address line is selected, so the display signal voltage held on the signal line is This is because if the change occurs due to the leakage, a normal display signal voltage cannot be written to the pixel electrode. The conventional inspection method described in FIG. 6 has a problem in that the ammeter cannot capture a small amount of leakage between the electrodes, making it difficult to inspect.

[発明の目的] 本発明は上記問題を解決し、アクティブマトリクス基板
の任意の電極間のわずかな漏洩に対しても容易に且つ確
実に検査可能としたアクティブマトリクス基板の検査方
法を提供することを目的とする。
[Object of the Invention] The present invention solves the above problems and provides an active matrix substrate inspection method that enables easy and reliable inspection of even the slightest leak between arbitrary electrodes of an active matrix substrate. purpose.

[発明の慨要] 本発明は、互に複数の信号線とアドレス線の夫々の交差
部に少なくともスイッチ素子と画素電極が設けられた表
示装置用のアクティブマトリクス基板の電極間短絡また
は漏洩の検査を行なうに際し、一方の電極を基準として
他方の電極を所定の電位に充電する手段と、充電後所定
時間経過後前記充電した電極の電位を計測する手段とを
具備し、充電時電位と所定時間経過後の電位との差から
電極間の短絡または漏洩の程度を知るものである。
[Summary of the Invention] The present invention is a method for inspecting short-circuits or leakage between electrodes of an active matrix substrate for a display device in which at least a switch element and a pixel electrode are provided at each intersection of a plurality of signal lines and an address line. When performing this, the method includes means for charging one electrode to a predetermined potential with respect to the other electrode, and means for measuring the potential of the charged electrode after a predetermined time has elapsed after charging. The degree of short circuit or leakage between the electrodes can be determined from the difference in potential after the lapse of time.

板の検査方法の一実施例を説明するための回路図で、第
1図(a )は信号1I(Xs 、 X2 =→0)の
夫々とアドレス線(Yl 、Y2・・・Yn)間の短絡
または漏洩の有無を検査する場合を例示したものであり
、アクティブマトリクス基板17のアトi′□    
レスMJYx 、Y2・・・Ynは共通に接続されて直
流電源22の負Ti極に接続され、この直流電源22の
正電極は充電/計測切換スイッチ23の第1の固定端子
231に接続される。この充電/計測切換スイッチ23
の第2の固定端子232は電位計測器24に接続され、
充電/計測切換スイッチ23の可動端子230は信号線
】択スイッチ18の可動端子180に接続され、この信
号線選択スイッチ18の固定端子181.182・・・
18I11はアクティブマトリクス基板17の各信号線
X1゜×2・・・Xll+に夫々対応して接続される。
FIG. 1(a) is a circuit diagram for explaining an embodiment of the board inspection method. This is an example of a case where the presence or absence of short circuit or leakage is inspected.
The addresses MJYx, Y2, . . This charging/measurement switch 23
The second fixed terminal 232 of is connected to the potential measuring device 24,
The movable terminal 230 of the charging/measurement changeover switch 23 is connected to the movable terminal 180 of the signal line selection switch 18, and the fixed terminals 181, 182, . . .
18I11 are connected to the signal lines X1°×2 . . . Xll+ of the active matrix board 17, respectively.

また第1図(b )は信号線Xs 、X2・・・xlの
夫々と接地電極間の短絡または漏洩の有無を検査する場
合を例示したものであり、直流電i!122の負電極に
アクティブマトリクス基板17の接地電極を接続したも
のである。第1図(b)中第1図(a >と同一部分は
同一符号を付してその説明を省略する。第2図は第1図
の回路の動作を説明するための波形図である。すなわち
、第1図(a )の場合にはまず充電/計測切換スイッ
チ23を電源22側に倒して充電モードに設定する。次
に信号線選択スイッチ18により第2図のXl、X2・
・・XllのT1の期間に示すように信号線Xt。
FIG. 1(b) is an example of a case where the presence or absence of short circuit or leakage between the signal lines Xs, X2, . . . . . . xl and the ground electrode is inspected. The ground electrode of the active matrix substrate 17 is connected to the negative electrode of the active matrix substrate 122. In FIG. 1(b), the same parts as those in FIG. 1(a) are given the same reference numerals, and the explanation thereof will be omitted. FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG. 1. That is, in the case of FIG. 1(a), the charge/measurement changeover switch 23 is first turned to the power supply 22 side to set the charge mode.Next, the signal line selection switch 18 is used to select Xl, X2,
...The signal line Xt as shown in the period T1 of Xll.

×2・・・xIiを順次所定時間tずつ選択し、N源2
2の電位Eaまで充電する。全ての信号線Xt。
×2...xIi is sequentially selected for each predetermined time t, and N source 2
Charge to the potential Ea of 2. All signal lines Xt.

×2・・→0の充電が終ると、充電/計測切換スイッチ
23を電位計測器24側に倒して計測モードに設定する
。次に信号線選択スイッチ18により第2図のXs 、
X2・・・X1llのT2の期間に示すように信号線X
I 、X2・・・Xl1lを順次所定時間tずつ選択し
、それらの電位EXt 、EX2・・・EXmを夫々計
測する。そして計測値が先の充電電圧EOに対してどの
位低下しているかにより、その信号線とアドレス線との
短絡または漏洩の程度を知ることができる。
When the charging of ×2...→0 is completed, the charging/measurement changeover switch 23 is turned to the potential measuring device 24 side to set the measurement mode. Next, use the signal line selection switch 18 to select Xs,
As shown in the T2 period of X2...X1ll, the signal line
I, X2, . . . The degree of short circuit or leakage between the signal line and the address line can be determined based on how much the measured value has decreased with respect to the previous charging voltage EO.

第3図はこの様子を示しており、tlはある信号線の充
電期間を示し、T2はその信号線の電位計測期間を示す
。また、T3は必要により再計測を行なう場合の充電期
間である。充電期間t1において、電源22の電位Ea
まで充電された信号線の電位は、時間経過と共に、低下
していく。実@aは正常な信号線の電位変化を示し、電
位計測器24の入力インピーダンスなどによるわずかな
低下はあるが、充電電位EOに近い値が計測期間で2に
おいて保持されている。破線すはアドレス線との間にわ
ずかに漏洩が存在する信号線の電位変化示しており、計
測期間t2において充電電位Eaよりかなり低下してい
る。一点鎖線Cはアドレス線との間に順路状態に近い状
態が存在する信号線の電位変化を示しており、計測期間
t2における信号線電位は0ボルトに低下している。本
発明による検査方法においては、信号線の客員や電位計
測器の入力インピーダンスなどを考慮した上で、充電後
計測するまでの時間を設定することにより、わずかな漏
洩に対しても大きな電位変化として計測できる。
FIG. 3 shows this state, where tl indicates a charging period of a certain signal line, and T2 indicates a potential measurement period of that signal line. Further, T3 is a charging period when re-measurement is performed if necessary. During the charging period t1, the potential Ea of the power supply 22
The potential of the signal line, which has been charged up to 1, decreases over time. Actual @a indicates a normal potential change of the signal line, and although there is a slight decrease due to the input impedance of the potential measuring device 24, a value close to the charging potential EO is maintained at 2 during the measurement period. The broken line indicates a change in the potential of the signal line with slight leakage between it and the address line, which is considerably lower than the charging potential Ea during the measurement period t2. A one-dot chain line C indicates a change in the potential of a signal line in which a state close to a normal path state exists between the signal line and the address line, and the signal line potential in the measurement period t2 has decreased to 0 volts. In the inspection method according to the present invention, by setting the time from charging to measurement after considering the signal line guest and the input impedance of the potential measuring device, even a small leakage can be treated as a large potential change. It can be measured.

以上第1図(a )の場合について説明したが、第1図
(b )の場合は信号線との短絡または漏洩の検査を行
なう相手電極がアドレス線より接地電極に代っただけで
あり、第1図(a >の場合と同様の動作で検査を行な
うことが出来る。また、第1図(a)、(b)の場合に
限らず任意の電極間で検査することが出来る。さらに、
充電/計測切換スイッチ23、信号線選択スイッチ18
および電位計測器24などは電子回路的に一括構成する
ことが出来、電位計測器24に計測値に対する閾値を設
定することにより良否自動判定を行なわせることも出来
る。
The case of Fig. 1(a) has been explained above, but in the case of Fig. 1(b), the other electrode for testing for short circuits or leakage with the signal line is simply replaced by the ground electrode instead of the address line. Inspection can be performed using the same operation as in the case of FIG.
Charging/measurement switch 23, signal line selection switch 18
The electric potential measuring device 24 and the like can be collectively configured as an electronic circuit, and by setting a threshold value for the measured value in the electric potential measuring device 24, it is also possible to make automatic pass/fail judgment.

[発明の効果コ 以上説明したように本発明によれば、電極間のわずかな
漏洩に対しても大きな電位変化として計測することが出
来るので、アクティブマトリクス基板の電極間の短絡お
よび漏洩の検査を容易に且つ確実に行なうことが出来る
効果がある。
[Effects of the Invention] As explained above, according to the present invention, even a slight leakage between electrodes can be measured as a large potential change. This has the advantage of being easy and reliable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を説明するための回路図、第
2図および第3図は第1図の動作を説明するための波形
図、第4因はアクティブマトリクス基板を説明するため
の電気的等価回路図、第5図は第4図のアクティブマト
リクス基板を用いた;    表示装置の一例を説明す
るための断面図、第6図は従来のアクティブマトリクス
基板の検査方法を説明するための回路図である。 17・・・アクティブマトリクス基板、18・・・信号
線選択スイッチ、22・・・電源、23・・・充電/計
測切換スイッチ、24・・・電位計測器、×1〜XI・
・・信号線、Y1〜Yn・・・アドレス線。 出願人代理人 弁理士 鈴江武彦 第1図 第2図 第3図
Figure 1 is a circuit diagram for explaining one embodiment of the present invention, Figures 2 and 3 are waveform diagrams for explaining the operation of Figure 1, and the fourth factor is for explaining the active matrix board. FIG. 5 is an electrical equivalent circuit diagram using the active matrix substrate shown in FIG. 4; FIG. 6 is a cross-sectional view for explaining an example of a display device, and FIG. FIG. 17... Active matrix board, 18... Signal line selection switch, 22... Power supply, 23... Charging/measurement changeover switch, 24... Potential measuring device, ×1 to XI・
...Signal line, Y1-Yn...Address line. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 互に複数の信号線とアドレス線の夫々の交差部に少なく
ともスイッチ素子と画素電極が設けられた表示装置用の
アクティブマトリクス基板の検査方法において、前記ア
クティブマトリクス基板の任意の電極間のうち一方の電
極を基準として他方の電極を所定電位に充電する手段と
、充電後所定時間経過後前記充電した電極の電位を計測
する手段とを具備し、充電電位と所定時間経過後の電位
との差から当該電極間の短絡または漏洩の程度を知るこ
とを特徴とするアクティブマトリクス基板の検査方法。
In a method for inspecting an active matrix substrate for a display device, in which at least a switch element and a pixel electrode are provided at each intersection of a plurality of signal lines and an address line, one of the electrodes of the active matrix substrate is provided. The method includes means for charging the other electrode to a predetermined potential using the electrode as a reference, and means for measuring the potential of the charged electrode after a predetermined time has elapsed after charging. A method for inspecting an active matrix substrate, characterized by determining the degree of short circuit or leakage between the electrodes.
JP60295012A 1985-12-26 1985-12-26 Inspecting method for active matrix substrate Pending JPS62151769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60295012A JPS62151769A (en) 1985-12-26 1985-12-26 Inspecting method for active matrix substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60295012A JPS62151769A (en) 1985-12-26 1985-12-26 Inspecting method for active matrix substrate

Publications (1)

Publication Number Publication Date
JPS62151769A true JPS62151769A (en) 1987-07-06

Family

ID=17815190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60295012A Pending JPS62151769A (en) 1985-12-26 1985-12-26 Inspecting method for active matrix substrate

Country Status (1)

Country Link
JP (1) JPS62151769A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01129295A (en) * 1987-11-13 1989-05-22 Matsushita Electric Ind Co Ltd Segment drive ic for liquid crystal display panel
DE19532621A1 (en) * 1994-09-05 1996-03-07 Mitsubishi Electric Corp Semiconductor device for esp. field effect transistor
WO2018079636A1 (en) * 2016-10-31 2018-05-03 パナソニック株式会社 Liquid crystal display device and failure inspection method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01129295A (en) * 1987-11-13 1989-05-22 Matsushita Electric Ind Co Ltd Segment drive ic for liquid crystal display panel
DE19532621A1 (en) * 1994-09-05 1996-03-07 Mitsubishi Electric Corp Semiconductor device for esp. field effect transistor
US5652451A (en) * 1994-09-05 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Recessed gate field effect transistor
WO2018079636A1 (en) * 2016-10-31 2018-05-03 パナソニック株式会社 Liquid crystal display device and failure inspection method
JPWO2018079636A1 (en) * 2016-10-31 2019-09-19 パナソニック株式会社 Liquid crystal display device and failure inspection method

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