JPH07318980A - Liquid crystal display panel - Google Patents

Abstract

PURPOSE:To prevent the pattern destruction of storage wiring in an assembly process and to inspect a short circuit between wiring of a circuit in an LCD panel in which terminals of scan signal lines and data lines are taken out in the four sides directions of a substrate. CONSTITUTION:In the shunt bus structure of the LCD panel, the shunt buses are provided for respective scan signal lines 1 and data lines 3 such as 9-2, 9-4 connecting the scan signal lines 1 and 9-1, 9-3 connecting the data lines 3, and further, one line of storage wiring is provided in the shape of meandering along the scan signal lines 1, and a wiring inspecting measurement pad 12 is provided on its one end, and the other end is connected to the GND through a resistance pattern 8-4, and wiring inspecting pads are provided on the shunt bus lines 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a liquid crystal display panel, and more particularly to a shunt structure of an active matrix liquid crystal display panel.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display panel has a large number of thin film transistors (TFTs) arranged in a plurality of rows and columns. TFTs arranged in the same row
Are commonly connected to one scan signal line, and the drains (sources) of the TFTs arranged in the same column are commonly connected to one data line. The source (drain) of each TFT is connected to a transparent electrode such as ITO as a pixel electrode.

Each TFT is manufactured by repeating the steps of depositing a conductive layer and a semiconductor layer and selective etching, but static electricity is often generated in the manufacturing process and the transportation process between manufacturing devices, which causes the TFT. May be destroyed.

Therefore, TF is generated from static electricity generated during manufacturing.
Measures to protect T etc. are taken.

FIG. 3 is a schematic view of a conventional liquid crystal display panel provided with such protection means (Japanese Patent Laid-Open No. 63-106).
788). This liquid crystal display panel has a large number of pixels 4 arranged in a matrix and each having a TFT and a pixel electrode, the scan signal line 1 and the data wiring 3 described above, and is actually used as a liquid crystal panel. A shunt bus forming region is provided around a portion (enclosed by a dotted line), and a shunt bus line 5 is provided in the same region. This bus line 5 is used for all signal lines 1 and data lines 3.
Commonly connected to. The wiring 6 is a storage wiring pattern for holding charges.

The portion surrounded by the dotted line ABCD will be cut later as a liquid crystal display panel, but due to the presence of the ground shunt bus line 5 described above, static electricity generated during manufacturing is released.
The destruction of the TFT is prevented.

The portion of the shunt bus line 5 remaining inside the dotted line ABCD is used as a pad for connecting a drive circuit for driving the display panel.

[0008]

In recent years, the density of liquid crystal panels has been increasing and the number of display pixels has been increasing. That is, the width of each signal line is thin, the pitch is small, and the signal line interval is also narrowing. As a result, there is an increased risk of short circuits between adjacent signal lines or between intersecting signal lines, as well as the risk of disconnection of the signal lines.

Therefore, it is preferable to check for a short circuit between the signal lines and a disconnection of the signal lines when the signal lines of the same level are formed. This is because those that can be repaired are repaired, and those that cannot be repaired are restarted from the first step at that point, whereby the total manufacturing cost can be kept low.

However, in the structure shown in FIG. 3, the shunt bus 5 is formed continuously with all the scan signal lines 1 in the same step as the scan signal line 1, and the data line 3 is formed at the time of forming these. It is formed by connecting to 5. Therefore, it is impossible to detect a short circuit between the signal lines or a short circuit at the intersection.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a liquid crystal display panel which can easily inspect a short circuit between each wiring and a signal line while preventing the TFT from being broken by static electricity.

[0012]

A liquid crystal display panel according to the present invention has an active matrix portion in which TFTs are arranged in a matrix and a shunt bath forming portion provided around this portion, and the shunt bath forming portion is provided in the shunt bath forming portion. Have a first shunt bus and a second shunt bus independently formed, the first shunt bus being connected to a plurality of scan signal lines of the active matrix portion, while the second shunt bus being a plurality of active matrix portions. It is characterized by being resistant to the data line of.

[0013]

As described above, since the first and second shunt buses are provided independently, at least a short circuit between the scan signal line and the data line is inspected by checking the electrical continuity between both buses. be able to. Moreover, since the shunt bus structure is used, it is possible to prevent the TFT from being damaged by static electricity. At this time, it is preferable that each shunt bus is grounded via a resistor having a predetermined value in order to facilitate checking the electrical conductivity.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a liquid crystal display panel showing a first embodiment of the present invention. In this panel, four shunt buses 9-1 to 9-4 are formed independently of each other in the shunt bath forming portion. Each of the shunt buses 9-1 to 9-4 is connected to G via the resistance patterns 8-1 to 8-4.
It is connected to ND (grounded) and further connected to a predetermined scan signal line and data line. That is, the odd-numbered gate wirings 1-1, 1-3, ... Are connected to the shunt bus line 9-2 on the left side of the active matrix portion, and the even-numbered gate wirings 1-2, 1- are connected.
, ... are connected to the shunt bus line 9-4 on the right side of the matrix portion. In addition, odd-numbered data line 3
-1, 3-3, ... Are connected to the shunt bus 9-1 on the upper side of the matrix portion, and the even-numbered data lines 3-2, 3
-4, ..., Shunt bus 9 below the matrix portion
Connected to 3. Inspection and measurement pads 10-1 to 10-4 are provided on each shunt bath.

As described above, each shunt bus 9 is grounded though the corresponding resistor 8, so that static electricity generated during the process is released and the TFT is protected. Moreover, since the shunt bus structure is independent, it is possible to inspect the scan signal lines 1 and the data lines 3 or a short circuit between them. The details of this inspection will be described later.

Further, in this embodiment, the storage wiring 2 which connects one end of the signal charge holding capacitance portion, which is shown as a capacitor in each pixel 4, in common between the pixels 4, is also clear from a comparison with FIG. As the wiring, each scan signal line 1
It is configured as a single wire meandering along. One end of the one meandering storage wiring 2 is connected to the inspection / measurement pad 12, and the other end is grounded via the resistor 8-4. Further, in order to perform electrostatic discharge between each scan signal line 1 and the storage wiring 2 and between each data signal line 3 and the storage wiring 2, a discharging diode 7 is provided as shown.

Therefore, in this embodiment, the storage wiring 2 itself and the TFT via the wiring 2 can be protected from static electricity. Moreover, it is possible to inspect for a short circuit between the storage wiring 2 and the adjacent wiring.

That is, the measuring needle of the tester is placed on the pads 10-2 and 12 and the electrical conductivity between them is checked. Thus, it is possible to inspect whether the odd-numbered scan signal line 1 and the storage line 2 are short-circuited. At this time, if a short circuit occurs, the resistance value becomes substantially 0, while
If there is no short circuit, the sum of the resistors 8-2 and 8-4 is detected.
Similarly, by placing a tester needle on the pad 10-4 and the pad 12, the state between the even-numbered scan signal line 1 and the storage line 2 can be checked.

Further, by placing a tester needle on the pads 10-1 and 12, it is possible to inspect for a short circuit between the odd-numbered data wiring 3 and the storage wiring 2. At this time, if a short circuit occurs, the resistance value becomes 0, and if there is no short circuit, the sum of the resistors 8-1 and 8-4 is detected. Between the even-numbered data wiring 3 and the storage wiring 2, a tester needle is placed on the pads 10-3 and 12 for inspection.

Furthermore, the pad 10-2 and the pad 10
By placing the needle of the tester at -1, a short circuit between the odd-numbered data wiring 3 and the odd-numbered scan signal line 1 can be detected. At this time, if a short circuit occurs, the resistance value becomes 0, and if there is no short circuit, the sum of the resistances 8-1 and 8-2 is detected. Similarly, a tester needle is placed on the pads 10-2 and 10-3, the pad 10-4 and the pad 10-1, and the pad 10-4 and the pad 10-3 to detect a short circuit between the corresponding signal lines. .

As described above, by appropriately selecting the two pads to be inspected, it is possible to inspect a short circuit between various wirings. Therefore, by appropriately performing such an inspection step in a series of steps for manufacturing the panel, an undesired short circuit can be found at an early stage, repair can be performed, or manufacturing can be redone easily.

Next, a method for manufacturing the liquid crystal display panel in this embodiment will be described including the above-mentioned inspection.

First, C is formed on the entire surface of a transparent insulating substrate such as glass.
A metal such as r is provided by a sputtering method, the metal layer thus provided is selectively removed, and the scan signal line 1, the storage wiring 2-1, the shunt bus line 9-2, and the like as shown in FIG. 9-4, resistance patterns 8-2, 8-
4, 8-5 are formed.

Here, the resistance patterns 8-2, 8-4, 8
-5 is formed of the same metal as the shunt bus lines 9-2 and 9-4, etc., but the line width of the pattern is made sufficiently thinner than the shunt bus lines 9-2 etc., and the length is sufficient. As a result, it has a function as a resistor. These resistance values may be different for each pattern, but in consideration of simplification of manufacturing, the same value is preferable.

At this stage, it should be noted that the storage wiring is formed with only the portion 2-1 parallel to the scan signal line. Therefore, each part 2 of the storage wiring 2
The -1 portion is in an electrically floating state. In this state, a measuring probe is placed between the pads 10-2 and 10-4 to inspect for an electrically shorted state. If an electrical short-circuit condition is detected, this indicates that there is an unnecessary conductor left between two adjacent wirings 1 that makes them conductive. Therefore, it is possible to repair by finding out that portion and cutting the unnecessary conductor with, for example, a laser. If it is electrically open, wiring 1,
Since it is shown that there is a cut portion somewhere in 2, it is possible to repair the same portion.

Next, a gate insulating film such as a silicon oxide film or a nitride film is provided on the entire surface of the substrate, and a semiconductor film such as amorphous silicon to be a channel region of the TFT is selectively provided. Further, holes are selectively formed in the gate insulating film. After that, a metal such as Cr is again provided on the entire surface of the substrate and is selectively removed so that the data line 3 and the shunt bus line 9-
1, 9-3, the aforementioned resistance patterns 8-2, 8-4, 8-
Resistive patterns 8-1, 8-3 and the like similar to those of No. 5 are selectively provided. Further, at this time, as shown in FIG. 1B, the remaining portion 2-2 of the storage wiring is formed, and this portion is connected to the formed portion 2-2 through the opening provided in the gate insulating film. It As a result, one meandering storage wiring 2 is formed as a wiring. Of course, the intersection 13 between the scan signal line 1 and the storage wiring 2 and the intersection between the scan signal line 1 and the data line 3 in FIG. 1A are insulated by an insulating film. As is well known, scan signal line 1
Part of the data line 3 becomes the gate electrode of the TFT, and part of the data line 3 becomes the drain (source) electrode of the TFT. Further, the source (drain) electrode of the TFT is formed simultaneously with the formation of the data line 3.

After this step, by applying a probe between the desired pads and performing measurement, it is possible to detect a short circuit that may occur at the intersection of the wirings to be insulated. Also, pad 1
By applying a probe between 0-1 and 10-3 and measuring, a short circuit between two adjacent data lines 3 can be checked. If there is a short circuit, it can be repaired in some places.

After that, a transparent electrode such as ITO is selectively provided to form a pixel electrode, the entire surface of the substrate is covered with a protective insulating film, and the panel assembling process is performed.

Thus, in this embodiment, it is possible to protect the TFT from static electricity that may occur during the manufacturing process, and at the same time check for undesired short circuits between wirings due to dust or the like during the manufacturing process. Alternatively, the result can be fed back to the management and review of each process. Furthermore, an unrepairable short circuit can be detected early, and subsequent conveyance to a wasteful process can be prevented.

In the above embodiment, the storage wiring portion 2-1 formed simultaneously with the scan signal line 1 is in the floating state as described above. Therefore, it is considered that static electricity generated during the same process or during transportation to the next process is accumulated in the wiring portion 2-1 in a floating state, causing undesired discharge and destroying the wiring portion 2-1.

Therefore, as shown in FIG. 2 as a second embodiment of the present invention, it is preferable to form all the storage wirings 2 at the same time as the scan signal lines 1. In addition, in FIG.
The same components as those are denoted by the same reference numerals and the description thereof will be omitted.

In this embodiment, as shown in FIG.
Provide a metal such as Cr on the entire surface of a transparent insulating substrate such as glass,
Scan signal line 1 by etching with photoresist method
Shunt bus lines 9-2, 9-4, resistance pattern 8-
Simultaneously with the formation of 2, 8-5 and the like, the meandering storage wiring 2, the grounding resistance pattern 8-4 and the pad 12 are simultaneously formed.

With this structure, the storage wiring 2 can also be prevented from being damaged by static electricity from the time of its formation. Further, since there is no portion where the scan signal line 1 and the storage wiring 2 intersect, the possibility that a short circuit will occur between the wirings can be reduced as compared with the first embodiment. Moreover, by checking the short-circuit state between the pads 10-2 and 12 and between the pads 10-4 and 12, a short-circuit between the adjacent wirings 1-2 can be detected, and repair can be performed if any. In repairing, it is possible to scan with a laser beam to find a short-circuited portion, and increase the power to the same portion to cut it.

[0035]

As described above, according to the present invention, there is provided a shunt bus structure capable of easily performing a short circuit inspection between wirings while realizing protection from damage due to static electricity.

[Brief description of drawings]

FIG. 1 is a schematic view of a liquid crystal display panel showing a first embodiment of the present invention.

FIG. 2 is a schematic view of a liquid crystal display panel showing a second embodiment of the present invention.

FIG. 3 is a schematic view of a liquid crystal display panel showing a conventional example.

[Explanation of symbols]

1 scan signal line 2 storage wiring 3 data line 4 configuration for 1 pixel 5 shunt bus line 6 storage wiring pattern 7 ring diode 8 resistance pattern 9 shunt bus line 10 pad 11 pad 12 storage wiring pad 13 scan signal line / storage Wiring cross pattern 14 External circuit connection pad 15 Precision inspection pad

Claims (8)

[Claims] 1. A display panel portion having a plurality of scan signal lines and data lines, and a shunt bus forming portion provided around this portion, wherein the shunt bus forming portion includes first and second independent portions. A shunt bus is formed, the first shunt bus is connected to each of the scan signal lines, and the second shunt bus is connected to each of the data lines. panel. 2. The liquid crystal display panel according to claim 1, wherein the first shunt bus is grounded via a first resistor, and the second shunt bus is grounded via a second resistor. 3. A display panel portion having a plurality of scan signal lines, a plurality of data lines, and a plurality of thin film transistors connected to the corresponding scan signal lines and data lines, and a shunt bus provided around this portion. A shunt bath forming portion,
Second, third, and fourth shunt buses are formed independently of each other, the first shunt bus is connected to even-numbered scan signal lines of the plurality of scan signal lines, and the second shunt bus is formed. The bus is connected to an odd-numbered scan signal line of the plurality of scan signal lines, the third shunt bus is connected to an even-numbered data line of the plurality of data lines, and the fourth shunt bus is connected to the even-numbered data line of the plurality of data lines.
2. The liquid crystal display panel, wherein the shunt bus is connected to an odd-numbered data line of the plurality of data lines. 4. The first shunt bus is grounded via a first resistance, the second shunt bus is grounded via a second resistance, and the third shunt bus is a third resistance. The liquid crystal display panel according to claim 3, wherein the liquid crystal display panel is grounded via a resistor, and the fourth shunt bus is grounded via a fourth resistor. 5. The liquid crystal display panel according to claim 2, wherein the display panel portion further has a storage line, and the storage line is grounded via a resistor. 6. The liquid crystal display panel according to claim 5, wherein the storage wiring meanders along the scan signal line. 7. A plurality of pixels arranged in a matrix, each having a thin film transistor and a storage capacitor,
A plurality of scan signal lines respectively connecting the thin film transistors of the pixels arranged in corresponding rows to each other, and a storage wiring to which one end of each of the storage capacitors in the plurality of pixels is connected, the storage wiring, A plurality of first portions formed respectively between adjacent scan signal lines of the plurality of scan signal lines and a plurality of second portions formed in a direction orthogonal to the first portions; The second portion is a liquid crystal display panel arranged so as to connect the plurality of first portions in series with each other. 8. The liquid crystal display panel according to claim 7, wherein the plurality of first and second portions are continuously formed on the same plane.