JPH07287249A - Thin film transistor array and its inspection method - Google Patents

Abstract

PURPOSE:To provide the TFT array with a short-circuiting wire and its inspection method which enables the inspection of a short circuit between layers by simple conduction inspection after the TFT array is completed. CONSTITUTION:The thin film transistor array, which is provided with thin film transistors at respective intersection parts of plural address lines and plural data lines arranged crossing each other and has a display area having an auxiliary capacity line connected to the thin film transistors and also has a 1st short- circuiting wire arranged outside the display area through an electrostatic protection element, is equipped with a short-circuiting wire 31 for the data lines 12 which is arranged outside the 1st short-circuiting wire 30, a short-circuiting wire 31 for the address lines 11 which is arranged outside the 1st short-circuiting wire 30, and a short-circuiting wire 31 for the auxiliary capacity line 13 connected by the same metallic layer as the short-circuiting wire 31 for the address lines 11; and a discharging stylus is provided as the electrostatic protecting means 40 at the separation part between the short-circuiting wire 32 for the data lines 12, and the short-circuiting wire 31 for the address lines 11 and short- circuiting wire 31 for the auxiliary capacity line 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display device (LC
The present invention relates to a thin film transistor (TFT) array used in D), and more particularly to a short circuit wiring for facilitating inspection after the completion of the TFT array.

[0002]

2. Description of the Related Art Generally, there are the following methods for inspecting a TFT array. FIG. 4 is a diagram showing a conventional TFT array inspection method. (1) The optical inspection method is a method for visually comparing and collating repeating patterns of the TFT array.
Detect pattern abnormalities. According to this, although probing is not necessary, a short circuit between layers cannot be detected.

(2) The continuity test method is a method for detecting wiring resistance by applying a probing pin to each of the wiring terminals 500 to 2500, and it is possible to detect only line defects. According to this, the number of probing points is enormous, the number of inspection steps is increased, and the inspection efficiency is low. (3) The admittance measuring method is a method in which a resistor is inserted in a pattern circuit and a change in the admittance of the circuit is observed, and a line defect and a static pixel defect can be detected. According to this, the number of probing points is enormous, the number of inspection steps is increased, and the inspection efficiency is low.

(4) The voltage image method is a method of observing voltage images of pixels and wirings, and line defects and static pixel defects can be detected. According to this, the probing score is reduced to 3 to 5, but actual detection of a defect requires skill and its work is difficult. (5) The pulse response method is a method in which a pulse is applied to the pattern circuit and the response is observed at the other terminal, and the wiring voltage and the pixel charge can be detected. According to this, the number of probing points is enormous, the inspection man-hour increases,
Inspection efficiency is low.

By the way, conventionally, such a TFT array has been constructed as shown in FIG. That is, 1 is a TFT array region (display region), and address lines (scanning lines: gate lines) 11 and data lines (drain lines) 12 are arranged in this region so as to intersect with each other. TFTs 14 are formed at the intersections of the lines 12, and an auxiliary capacitance line 13 is provided, and an auxiliary capacitance 15 is provided between the source of the TFT 14 and the auxiliary capacitance line 13. A plurality of electrodes (not shown) connected to one of the source electrode and the drain electrode of the TFT 14 are arranged in a matrix to form a liquid crystal display (LCD).

[0006]

However, as shown in FIG. 5, when the individual electrodes are electrically independent,
The TFT characteristics may shift due to the influence of static electricity after the completion of the TFT array, or the data line 12 and the address line 1
It is known that an inter-layer short circuit occurs between the two, and as shown in FIG. 6, it has been conventionally practiced to electrically short each wiring in the TFT array pattern. The short circuit wiring 16 is separated by cutting in the LCD panel forming process.

With such a short-circuit wiring,
Only the optical inspection method (pattern inspection) is possible in the above-mentioned inspection method of the TFT array. Therefore, in order to detect defects even if the short-circuit wiring 16 exists, in the admittance measurement method, as shown in FIG. It is necessary to form 17. Since this resistance value is related to the defect detection accuracy, it is a heavy burden when designing the photomask used in the TFT process.

In addition, it is necessary to measure a minute voltage / current at the time of measurement, and in order to further determine a defect,
It is necessary to process the measurement data at high speed. On the other hand, the optical inspection method is a completely non-contact measurement, but can detect only defects accompanied by pattern abnormalities. That is, it is impossible to detect an inter-layer short circuit that is often accompanied by no pattern abnormality.

As described above, when the electrodes are electrically short-circuited by the wiring for short-circuiting as a countermeasure against static electricity, TF
There is a problem that it is not possible to determine the presence or absence of an interlayer short circuit by a simple continuity test after the T array is completed. Here, the reason why it is necessary to inspect only for the presence or absence of the interlayer short circuit is that almost all defects that occur in the TFT array are always accompanied by a pattern abnormality, and therefore can be detected by the pattern inspection, and the electrical probing is necessary. Inspection is TF
Since there is a risk of polluting or damaging the surface of the T-array substrate and it is necessary to probe hundreds to thousands of terminals, there is always concern about poor contact between the probing pins and each terminal.

However, the inter-layer short circuit is often accompanied by no pattern abnormality, and is a very serious defect. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned problems, and to provide a TFT array having a short-circuit wiring and an inspection method therefor, which can inspect an interlayer short-circuit by a simple continuity inspection after the TFT array is completed.

[0011]

[Means for Solving the Problems]

[I] In order to achieve the above object, the present invention provides a thin film transistor at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect with each other, and has an auxiliary capacitance line connected to the thin film transistors. In a thin film transistor array having a display area and having a first short-circuit wiring arranged outside the display area via an electrostatic protection element, (A) data arranged outside the first short-circuit wiring Line shorting line, address line shorting line arranged outside the first shorting line, and auxiliary capacitance line shorting line connected with the same metal layer as the address line shorting line And a static electricity protection means is provided at a portion where the data line short-circuit line and the address line short-circuit line and the auxiliary capacitance line short-circuit line are separated from each other.

(B) The short-circuit wiring of the data line arranged outside the first short-circuit wiring, the short-circuit wiring of the address line arranged outside the first short-circuit wiring, and the address A short circuit wiring for the auxiliary capacitance line connected with a different metal layer from the short circuit wiring for the line, and an electrostatic protection element provided in a separate portion between the short circuit wiring for the data line and the short circuit wiring for the address line; A static electricity protection means provided in a separation portion between the data line short-circuit wiring and the auxiliary capacitance line short-circuit wiring, and a separation portion between the address line short-circuit wiring and the auxiliary capacitance line short-circuit wiring. The static electricity protection means provided is provided.

[II] A thin film transistor is provided at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other, and a display region having an auxiliary capacitance line connected to the thin film transistor is provided, and the display region In a method of inspecting a thin film transistor array in which a first short-circuit wiring is arranged outside of the first short-circuit wiring, (A) a data line short-circuit wiring arranged outside the first short-circuit wiring A short-circuit line of the address line arranged outside the first short-circuit line, a short-circuit line of the auxiliary capacitance line connected in the same metal layer as the short-circuit line of the address line, and a short circuit line of the data line. An electrostatic protection means is provided at a separation portion between the short-circuit wiring and the short-circuit wiring of the address line and the short-circuit wiring of the auxiliary capacitance line, and the short-circuit wiring of the data line and the short-circuit of the address line and the auxiliary capacitance line are provided. A DC voltage was applied between the use wires, and the data line, in which so as to inspect the interlayer short-circuit between the address line and the auxiliary capacitance line.

(B) The short circuit wiring of the data line arranged outside the first short circuit wiring, the short circuit wiring of the address line arranged outside the first short circuit wiring, and this address A short-circuit wiring of the auxiliary capacitance line connected by a metal layer different from the short-circuit wiring of the line, an electrostatic protection element provided in a separate portion between the short-circuit wiring of the data line and the short-circuit wiring of the address line, and An electrostatic protection means is provided at a separation portion between the data line short-circuit wiring and the auxiliary capacitance line short-circuit wiring, and a static electricity protection means is provided at a separation portion between the address line short-circuit wiring and the auxiliary capacitance line short-circuit wiring. A static electricity protection means is provided, a DC voltage is applied between the short-circuit wiring of the data line and the short-circuit wiring of the address line, and an interlayer short-circuit between the data line and the address line is inspected. Wiring for short circuit and add A DC voltage is applied between the shorting lines of the data lines to inspect an interlayer short between the data line and the address line, an interlayer short between the data line and the auxiliary capacitance line is inspected, and the address line A DC voltage is applied between the short-circuit wiring and the short-circuit wiring of the auxiliary capacitance line to inspect an interlayer short-circuit between the address line and the auxiliary capacitance line.

[0015]

According to the present invention, as described above, in the separation portion where the short-circuit wiring of the address line and the short-circuit wiring of the data line and / or the short-circuit wiring of the auxiliary capacitance line of the TFT array face each other,
Since it is designed to protect against static electricity,
It is possible to prevent the FT from being damaged, and to reliably inspect the presence or absence of an interlayer short circuit by a simple continuity test using a tester or the like without using an expensive inspection device.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a thin film transistor array showing a first embodiment of the present invention. As shown in this figure, the TFT array region (display region) is the same as the conventional one, as shown in FIG. That is, 1 is a TFT array region (display region), and address lines (scanning lines) 11 and data lines 12 are arranged in this region so as to intersect with each other, and a TFT 14 is provided at an intersection of the address lines 11 and the data lines 12. Are formed respectively.

An auxiliary capacitance line 13 is provided and its T
An auxiliary capacitance 15 is provided between any one of the source electrode and the drain electrode of the FT 14 and the auxiliary capacitance line 13.
A plurality of electrodes (not shown) connected to one of the source electrode and the drain electrode of the TFT 14 are arranged in a matrix to form a liquid crystal display (LCD).

In this embodiment, the address line 11 and the auxiliary capacitance line 13 are made of the same metal layer. The address line 11, the data line 12, and the auxiliary capacitance line 13 are drawn out to the outside of the TFT array region 1 and are provided at the respective tip portions,
Connection terminals for supplying signals from the outside are formed as LCDs of the address line terminal 21, the data line terminal 22, and the auxiliary capacitance terminal 23.

Around the TFT array region 1, a first
The short-circuit wiring 30 is provided, and the first short-circuit wiring 3 is provided.
0 is connected to the address line 11 and the data line 12 via the electrostatic protection element 4. Further, on the outer circumference of each connection terminal, a short circuit wiring 31 to which all the address line terminals 21 and the auxiliary capacitance lines 13 are connected and a short circuit wiring 32 to which all the data line terminals 22 are connected are provided. Electrostatic protection means 40 is provided at the separated portion of the short circuit wiring 31 and the short circuit wiring 32.

Therefore, the short-circuit wiring 31 and the short-circuit wiring 32 are in an insulated state. FIG. 2 is an enlarged view of a separated portion of a short circuit wiring to which all address line terminals and auxiliary capacitance lines are connected and a short circuit wiring to which all data line terminals are connected. As shown in this figure, all the address line terminals 21 and the auxiliary capacitance lines 13 are connected to the short-circuit wiring 31.
And the short-circuit wiring 3 to which all the data line terminals 22 are connected
Electrostatic charging occurs in the separated part where 2 faces each other,
When a potential difference is generated between the short-circuit wiring 31 and the short-circuit wiring 32, a plurality of discharge needles 41 serving as static electricity protection means 40 for inducing discharge below the insulation film breakdown voltage between the address line 11 and the data line 12 are provided. Formed.

Here, in order to start discharge with a potential difference as low as possible when electrostatic charge is generated,
The tip of the discharge needle 41 was processed into an acute angle. In other words, the gap having the protrusion 41a having an included angle was formed. Further, the distance between the discharge needles 41 also needs to be such a distance that discharge can be started with a potential difference as low as possible and stable machining can be performed, and here, it is set to 5 μm. In addition, it is desirable to use it in 5 μm to 10 μm.

The number of discharge needles 41 may be one, two, or four or more. In this embodiment, the address line terminal 21 and the auxiliary capacitance terminal 23 are connected to the same short circuit wiring 31, and all the data line terminals 22 are connected to the short circuit wiring 32. In this way, the address line terminal 21 and the auxiliary capacitance terminal 23 are connected to the same short-circuit wiring 3
1 is connected to the address line 11 and the auxiliary capacitance line 13
Is formed by the metal of the same layer, and when the respective electrodes are formed by the metal of different layers through the insulating layer between the address line 11 and the auxiliary capacitance line 13 due to the structure, the same short circuit The wiring 31 should also be separated.

FIG. 3 is a block diagram of a thin film transistor array in the case where such an address line and an auxiliary capacitance line are formed of different layers of metal via an insulating layer. As shown in this figure, all address line terminals 21 are connected by short-circuit wiring 33, and all data terminals 22 are connected by short-circuit wiring 34. Further, the auxiliary capacitance terminal 23 is provided independently without being connected to the address line 11.

Therefore, the short-circuit wiring 33 and the short-circuit wiring 34
A discharge needle 42 having a structure similar to that of the discharge needle 41 described above is provided in the separation portion of the discharge needle 41, and a discharge needle 41 described above is provided in the separation portion of the short circuit wiring 34 and the short circuit wiring 35 of the auxiliary capacitance terminal 23. A discharge needle 43 having the same structure as the above is provided. Similarly, a discharge needle 44 having the same structure as the above-mentioned discharge needle 41 is connected to the separated portion of the short-circuit wiring 33 and the short-circuit wiring 35 of the auxiliary capacitance terminal 23.

FIG. 8 is a block diagram of a thin film transistor array showing a second embodiment of the present invention. As shown in this figure,
Most of the structure is the same as that shown in FIG. 1, but in this embodiment, all the address line terminals 21 and the auxiliary capacitance lines 13 are connected to the outer periphery of the connection terminal for shorting wiring 31. And a short-circuit wiring 32 to which all the data line terminals 22 are connected, and a static electricity protection element 45 as a static electricity protection means is provided in a separated portion between the short-circuit wiring 31 and the short-circuit wiring 32.

Further, as shown in FIG. 9, as the electrostatic protection element 45, for example, a TFT is formed. Here, FIG. 9A is a plan view of the TFT, and FIG. 9B is FIG.
It is the sectional view on the AA line of (a). In these figures,
51 is a glass substrate, on which the first
All of the second layers are formed by patterning the short circuit wirings 31 connected to all the address line terminals 21 and the auxiliary capacitance lines 13 which are layers, and forming the gate insulating film 52 between the short circuit wirings 31. Patterning the short-circuiting wiring 32 to which the data line terminal 22 of FIG. Deposit 55. In this way, the TFT is formed.

In this way, a TFT formed in the same manner as the TFT in the display area is formed as an electrostatic protection element at the separation portion where the short circuit wiring 31 and the short circuit wiring 32 face each other. Here, two TFTs are connected in parallel, and the gates 50a and 50b of each TFT are connected to the short circuit wiring 31 for the gate 50a of one TFT and to the short circuit wiring 32 for the other TFT. , Short circuit wiring 31 and short circuit wiring 32
Even if either one of them is charged by static electricity, the TFT, which is one of the electrostatic protection elements, is turned on, and the short-circuit wiring 31 and the short-circuit wiring 32 are kept at the same potential. In addition, an almost insulated state is achieved for a DC low voltage when inspecting an interlayer short circuit.

FIG. 10 is a block diagram of a thin film transistor array in the case where the address line and the auxiliary capacitance line of the thin film transistor array according to the second embodiment of the present invention are formed of different layers of metal via an insulating layer. . As shown in FIG. 10, when the auxiliary capacitance line 13 is formed of a metal layer different from the address line 11, all the address line terminals 21 are formed.
Shorting wiring 33 connected to all data line terminals 2
A short-circuit wiring 34 to which 2 is connected is provided, and an electrostatic protection element 46 made of the same TFT as that described above is provided at the separation portion between the short-circuit wiring 33 and the short-circuit wiring 34.

Further, an electrostatic protection element 47 is provided at a separation portion between the short circuit wiring 34 and the short circuit wiring 35 to which all the auxiliary capacitance lines 13 are connected. Furthermore, the wiring 33 for short circuit
The same TF as described above is provided in the separation portion between the short circuit wiring 35 and
An electrostatic protection element 48 made of T is provided. Up to this point, the embodiment in which the TFT is formed as the electrostatic protection element has been described, but the electrostatic protection element formed between the individual short-circuit wirings may be a space charge limiting current element or a resistor.

The space charge limited current element is composed of a space charge limited current (Space Charge Limited Cu).
is a two-terminal element (SCLC element) having a non-linear voltage-current characteristic whose voltage-current characteristic is defined by the current. FIG. 11 is a configuration diagram when such a space charge limited current element is used, FIG. 11A is a plan view thereof, and FIG.
11 is a sectional view taken along line BB of FIG.

As shown in the figure, a short circuit wiring 31 is patterned on a glass substrate 51, a gate insulating film 52 of a TFT is formed thereon, and a semiconductor film 53 made of amorphous silicon is formed on the gate insulating film 52. Ohmic layer 5
An electrode composed of 4 is formed, a short-circuit wiring 32 is formed on the electrode, and the electrode is covered with a protective film 55. Thus, the space charge limited current element has a structure in which the gate electrode is removed from the TFT, and can be formed at the same time as the TFT used in the display portion. Further, since it is a two-terminal element, unlike the case where the TFT is used as an electrostatic protection element, it is not necessary to form two elements in a complementary combination.

This space charge limited current element has a non-linear voltage-current characteristic as shown in FIG. 12, and has a sufficiently high element resistance at a normal driving (measurement) voltage, and when a high voltage is applied by static electricity, A large current flows and a short circuit occurs substantially. In FIG. 12, the vertical axis represents current [A] and the horizontal axis represents [V]. Next, the case where a resistor is used as the electrostatic protection element will be described.

FIG. 13 is a constitutional view when a resistor is used as an electrostatic protection element, FIG. 13 (a) is a plan view thereof, and FIG. 13 (b) is a sectional view taken along line CC of FIG. 13 (a). Is. As shown in the figure, the short-circuit wiring 3 is formed on the glass substrate 51.
1 is patterned, and the gate insulating film 5 of the TFT is formed thereon.
2 is formed, and a transparent electrode used as a pixel electrode in the TFT array region 1 is meandered on the gate insulating film 52 and processed into a thin line shape to obtain a necessary resistor 56. The short-circuit wiring 32 is formed thereon and covered with the protective film 55.

As described above, when the resistor is used as the electrostatic protection element, the voltage-current characteristic is linear unlike the TFT or the space charge limiting current element, and therefore, the thin film (amorphous silicon or metal) used for the TFT is used. It is necessary to obtain a resistance value that does not hinder driving (measurement) by patterning a thin film) into a fine line shape. Next, a method of inspecting using the thin film transistor array of the present invention configured as described above will be described.

As described above, it is possible to detect the abnormality of the pattern of the address line, the data line, and the auxiliary capacitance line visually by the optical inspection method in advance. Therefore, in particular, address lines that cannot be covered by this optical inspection method,
The detection of the pinhole short circuit between the data line and the auxiliary capacitance line is inspected by using the thin film transistor array of the present invention. Therefore, for example, in the case of FIG. 1, a DC voltage is applied between any one location of the address line terminal 21 and any one location of the data line terminal 22 or the auxiliary capacitance line terminal 23,
Check continuity. For example, the tester probe is connected to any one of the address line terminals 21 and the data line terminals 2
2 or the auxiliary capacitance line terminal 23 is applied to one place.

Then, when the address line 11 and the auxiliary capacitance line 13 in the TFT array region 1 and the data line 12 are short-circuited, the defect can be detected.
In that case, when the DC voltage for continuity inspection is applied, the static electricity protection means 40 is provided in the separation portion between the short-circuit wiring 31 and the short-circuit wiring 32. Is not conducting and is insulated.

However, when a high voltage due to static electricity is applied, the static electricity protection means 40 becomes conductive, so that a current flows through the static electricity protection element 4, and the short circuit wiring 31 and the short circuit wiring 32 are the same. It becomes an electric potential. That is, since the gate electrode and the drain or source electrode of the TFT have the same potential, it is possible to prevent the gate insulating film from being destroyed. In this way, the thin film transistor array can be inspected in three conduction steps.

Further, for example, in the case of FIG. 3, a DC voltage is applied between any one location of the address line terminal 21 and any one location of the data line terminal 22 to inspect the conduction state. To do. For example, a tester probe is applied to any one of the address line terminals 21 and one of the data line terminals 22. Then, if there is a short circuit between the address line 11 and the data line 12 in the TFT array region 1, the defect can be detected.

A DC voltage is applied between any one of the data line terminals 22 and the auxiliary capacitance line terminal 23 to inspect the conduction state. For example, a tester probe may be installed on any one of the data line terminals 22 and the auxiliary line terminals 23.
Hit Then, the data line 11 in the TFT array region 1
When there is a short circuit between the storage capacitor line 13 and the auxiliary capacitance line 13, the defect can be detected.

Further, the address line 1 in the TFT array region 1
Between any one of 1 and the auxiliary capacitance line terminal 23,
A DC voltage is applied to check the continuity. For example, a tester probe is applied to any one of the address lines 11 and the auxiliary capacitance line terminal 23. Then, if there is a short circuit between the address line 11 and the auxiliary capacitance line 13 in the TFT array region 1, the defect can be detected.

In this way, the thin film transistor array can be inspected in three conduction steps. Also,
A discharge needle, a TFT as an electrostatic protection element, an SCLC element, a resistor, or the like can be used as the electrostatic protection means. In this way, when a high voltage due to static electricity is applied by providing the protection element against static electricity. Has
A current flows through the electrostatic protection means provided on the address line, data line, and auxiliary capacitance line to prevent the breakdown of the gate insulating film, and at the voltage when measuring the interlayer short circuit, the resistance between the gate and drain becomes high. It is designed to be kept.

As described above, the visual inspection is previously performed by the optical inspection method, and the short-circuit defect between the address line, the data line and the auxiliary capacitance line is easily detected by using the thin film transistor array of the present invention. Moreover, it is possible to reliably inspect the thin film transistor array. The present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0043]

As described in detail above, according to the present invention, the short-circuit wiring of the address line of the FET array and the short-circuit wiring of the data line and / or the short-circuit wiring of the auxiliary capacitance line face each other. Since a static electricity protection means is applied to the part, it prevents the TFT from being damaged by static electricity, and without a costly inspection device, conducts a simple continuity test with a tester or the like to reliably check for the presence of an interlayer short circuit. It is possible to

[Brief description of drawings]

FIG. 1 is a configuration diagram of a thin film transistor array showing a first embodiment of the present invention.

FIG. 2 is a separation portion of a short circuit wiring to which all address line terminals and auxiliary capacitance lines are connected and a short circuit wiring to which all data line terminals are connected of the thin film transistor array showing the first embodiment of the present invention. FIG.

FIG. 3 is a configuration diagram of a thin film transistor array in the case where the address line and the auxiliary capacitance line of the thin film transistor array according to the first embodiment of the present invention are respectively formed of different layers of metal via an insulating layer.

FIG. 4 is a diagram showing a conventional inspection method for a TFT array.

FIG. 5 is a configuration diagram of a conventional TFT array.

FIG. 6 is a configuration diagram of a conventional TFT array in which a short circuit wiring is formed.

FIG. 7 is a configuration diagram of a conventional TFT array in which a resistor is formed between a short-circuit wiring and a TFT array.

FIG. 8 is a configuration diagram of a thin film transistor array showing a second embodiment of the present invention.

FIG. 9 is a configuration diagram of a TFT as an electrostatic protection element of a thin film transistor array showing a second embodiment of the present invention.

FIG. 10 is a configuration diagram of a thin film transistor array in which an address line and an auxiliary capacitance line of a thin film transistor array showing a second embodiment of the present invention are respectively formed of different layers of metal via an insulating layer.

FIG. 11 is a configuration diagram of a space charge limited current element as an electrostatic protection element of a thin film transistor array showing a second embodiment of the present invention.

FIG. 12 is a diagram showing voltage-current characteristics of a space charge limited current element as an electrostatic protection element of a thin film transistor array showing a second embodiment of the present invention.

FIG. 13 is a diagram showing a resistor as an electrostatic protection element of a thin film transistor array showing a second embodiment of the present invention.

[Explanation of symbols]

 1 TFT array area (display area) 4, 45, 46, 47, 48 Electrostatic protection element 11 Address line (scanning line) 12 Data line 14 TFT 13 Auxiliary capacitance line 15 Auxiliary capacitance 21 Address line terminal 22 Data line terminal 23 Auxiliary capacitance Terminal 30 First short-circuit wiring 31, 32, 33, 34, 35 Short-circuit wiring 40 Electrostatic protection means 41, 42, 43, 44 Discharge needle 41a Inclined projections 50a, 50b TFT gate 51 Glass substrate 52 Gate insulation Film 53 Semiconductor film (amorphous silicon) 54 Ohmic layer 55 Protective film 56 Resistor

Claims (8)

[Claims] 1. A thin film transistor is provided at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other, and a display region having an auxiliary capacitance line connected to the thin film transistor is provided, In a thin film transistor array in which a first short-circuit wiring is arranged outside via an electrostatic protection element, (a) a data-circuit short-circuit wiring arranged outside the first short-circuit wiring, and (b) A short circuit wiring of an address line arranged outside the first short circuit wiring; and (c) a short circuit wiring of an auxiliary capacitance line connected with the same metal layer as the short circuit wiring of the address line,
(D) A thin film transistor array, characterized in that static electricity protection means is provided at a portion where the data line short-circuit line and the address line short-circuit line and the auxiliary capacitance line short-circuit line are separated from each other. 2. A thin film transistor is provided at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other, and a display region having an auxiliary capacitance line connected to the thin film transistor is provided, In a thin film transistor array in which a first short-circuit wiring is arranged outside via an electrostatic protection element, (a) a data-circuit short-circuit wiring arranged outside the first short-circuit wiring, and (b) A short circuit wiring of an address line arranged outside the first short circuit wiring; and (c) a short circuit wiring of an auxiliary capacitance line connected to a metal layer different from the short circuit wiring of the address line,
(D) an electrostatic protection element provided at a separation portion between the data line short-circuiting line and the address line short-circuiting line,
Provided in a separate portion between the short-circuit wiring of the data line and the short-circuit wiring of the auxiliary capacitance line, and an electrostatic protection means, and in a separate portion of the short-circuit wiring of the address line and the short-circuit wiring of the auxiliary capacitance line. A thin-film transistor array, comprising: 3. The thin film transistor array according to claim 1, wherein the electrostatic protection means is a discharge needle. 4. The thin film transistor array according to claim 1, wherein the static electricity protection means is a TFT. 5. The thin film transistor array according to claim 1, wherein the electrostatic protection means is a space charge limited current element whose voltage-current characteristic is defined by a space charge limited current. 6. The thin film transistor array according to claim 1, wherein the static electricity protection means is a resistor. 7. A thin film transistor is provided at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other, and a display region having an auxiliary capacitance line connected to the thin film transistor is provided, In a method of inspecting a thin film transistor array in which a first short-circuit wiring is arranged outside via an electrostatic protection element, (a) a short-circuit wiring of a data line arranged outside the first short-circuit wiring,
An address line short-circuit line arranged outside the first short-circuit line, an auxiliary capacitance line short-circuit line connected to the same metal layer as the address line short-circuit line, and the data line short-circuit A static electricity protection means is provided at a separation portion between the wiring for data and the wiring for short-circuiting the address line and the wiring for short-circuiting the auxiliary capacitance line, and (b) the wiring for short-circuiting the data line and the address line and the auxiliary capacitance line. Apply a DC voltage between the shorting wires,
A method of inspecting a thin film transistor array for inspecting an interlayer short circuit between the data line and an address line and an auxiliary capacitance line. 8. A thin film transistor is provided at each intersection of a plurality of address lines and a plurality of data lines arranged to intersect each other, and a display region having an auxiliary capacitance line connected to the thin film transistor is provided, In a method of inspecting a thin film transistor array in which a first short-circuit wiring is arranged outside via an electrostatic protection element, (a) a short-circuit wiring of a data line arranged outside the first short-circuit wiring,
An address line shorting line arranged outside the first shorting line, an auxiliary capacitance line shorting line connected to a metal layer different from the address line shorting line, and the data line shorting A static electricity protection element provided in a separated portion between the data wiring and the short circuit wiring of the address line, and an electrostatic protection means provided in a separated portion between the short circuit wiring of the data line and the short circuit wiring of the auxiliary capacitance line, An electrostatic protection means is provided at a separate portion between the short-circuit wiring of the address line and the short-circuit wiring of the auxiliary capacitance line, and (b) between the short-circuit wiring of the data line and the short-circuit wiring of the address line. A DC voltage is applied to inspect for an interlayer short circuit between the data line and the address line, and a DC voltage is applied between the data line short-circuiting line and the address line short-circuiting line to form the data line and the data line. , Layer with address line To check the inter-layer short circuit between the data line and the auxiliary capacitance line, and apply a DC voltage between the shorting line of the address line and the shorting line of the auxiliary capacitance line to obtain the address line. And a method of inspecting a thin film transistor array for inspecting an interlayer short circuit between the storage capacitor line and the storage capacitor line.