JPH1195253A - Matrix array wiring substrate and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to omit an additional etching stage of lower layer wiring after the formation of upper layer wiring by disposing the gate electrodes of first and second thin-film transistors(TFTs) opposite to each other apart a spacing of several μm. SOLUTION: The gate electrode 3 consisting of lower layer metallic films is connected to the terminal part 1 side of the lower layer wiring. The first TFT 12 is formed of an amorphous Si film 6, the first upper layer wiring 10 and second upper layer wiring 11. The gate electrode 4 consisting of a lower layer metallic film is connected to an outer peripheral wiring 2 side for shorting the lower layer. The second TFT 13 is formed of an amorphous Si film 7, the first upper layer wiring 10 and the second upper layer wiring 11. Both of the first gate electrode 3 and the second gate electrode 4 have a projecting shape in their opposite facing parts 5 and are separated by maintaining a spacing of, for example, 3 to 6 μm. The opposite facing parts 5 are formed simultaneously with lower layer matrix array wiring in a patterning stage for the lower layer metallic film before a stage for depositing the upper layer metallic film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix array wiring substrate and a method of manufacturing the same, and more particularly, to a matrix array wiring substrate for a liquid crystal display device which has a countermeasure against static electricity during manufacturing and a method of manufacturing the same.

[0002]

2. Description of the Related Art As shown in FIG. 2, a prior art liquid crystal display device has a terminal portion 21 of a matrix array wiring formed by a plurality of address lines and data lines and a peripheral wiring 22 for short circuit.
To secure a resistance of about 100KΩ or more,
The meandering wiring 23 has been laid to lengthen the wiring.

[0003] When static electricity is generated in a matrix array wiring substrate during a manufacturing process, a thin film transistor (TFT) 24, which is a switching element arranged near each intersection of each matrix array wiring, is damaged by the static electricity. In order to prevent this, the array wirings need to have the same potential, and therefore, the terminal portion 21 of the matrix array wiring and the outer peripheral wiring 22 for short-circuit are electrically connected. At the completion of the manufacture of the matrix array wiring board,
Inspection of array wiring (disconnection, short circuit) and T
The function test of the FT 24 or the display pixel unit 25 connected to the FT 24 is electrically performed by setting a probe on the terminal unit 21. At this time, the current flowing from the outer peripheral wiring 22 for short-circuit to the terminal portion 21 lowers the S / N ratio of the measurement, so that the wiring resistance between the terminal portion 21 and the outer peripheral wiring 22 for short-circuiting is reduced in order to suppress this. This is because it is necessary to increase the wiring resistance of the array wiring part by at least about three times or more.

The problem of the prior art is that the meandering wiring 2 is located between the terminal 21 of the matrix array wiring and the outer peripheral wiring 22 for short-circuit.
That is, it is not possible to secure enough space for laying No.3.

[0005] The reason is that as the display portion of the liquid crystal display device becomes larger, the matrix array portion 27 becomes larger and the distance between the terminal portions 21 in a matrix array wiring board of the same size. Is a narrow pitch, and the distance between the terminal portion 21 and the outer peripheral wiring 22 for short-circuiting is becoming narrower.

Techniques for improving the above-mentioned disadvantages are disclosed in Japanese Patent Application Laid-Open Nos. 5-27263 and 63-106788.

In Japanese Patent Application Laid-Open No. Hei 5-27263, as shown in FIG. 3, a first electrode in which a gate electrode is connected to a terminal portion 31 between a terminal portion 31 and a short-circuit outer peripheral wiring 32 via a capacitor 35a and a resistor 36a. TFT 33 and a second TFT 34 whose gate electrode is connected to the short-circuit outer peripheral wiring 32 via a capacitor 35b and a resistor 36b are arranged in parallel, and are required for inspection of a discharge circuit for static electricity and a matrix array wiring board in a small space. High resistance (in this case, TFT
Use of the on-resistance).

In Japanese Patent Application Laid-Open No. 63-106788, matrix array wirings are connected to each other by non-linear elements in order to achieve both static electricity countermeasures during the manufacturing process and testability (easiness of inspection). After performing a cutting operation, a surface treatment operation, a joining operation with another component, or the like, the connection of the matrix array wirings by the non-linear elements is cut off by etching.

[0009]

Problems to be Solved by the Invention Japanese Patent Laid-Open No. 5-27263
The problem is that the gate wiring of the first TFT 33 and the terminal 3
1 and between the gate wiring of the second TFT 34 and the outer peripheral wiring 32 for short-circuiting.
5b and the resistors 36a and 36b are arranged. In this structure, if static electricity is generated on the matrix array wiring board during a manufacturing process before the first and second TFTs function as a discharge circuit, the capacitors 35a and 35b and resistors 36a and 36b are the first TFT 33 and the second TFT 34
However, there is a problem that it does not protect TFTs arranged as switching elements of the matrix array section 37 formed in the same manufacturing process.

Further, Japanese Patent Application Laid-Open Nos. Hei 5-27263 and Sho 63
When -106788 is combined, the terminal section 41 and the lower-layer short-circuit outer peripheral wiring 42 are connected by lower-layer metal wiring during the manufacturing process of the matrix array wiring board as shown in FIG.
A structure and a manufacturing method in which the lower metal wiring is cut at the position of the opening 49 by etching immediately before the inspection process of the matrix array wiring board can be easily conceived, and this is also disclosed in Japanese Patent Application Laid-Open No. 63-106788. As in the case of the problem, it is necessary to add an etching step in order to achieve both the countermeasures against static electricity during the manufacturing process and testability (easiness of inspection).

An object of the present invention is to prevent a display pixel portion including a TFT arranged in a matrix array portion from being damaged by static electricity during a manufacturing process of a matrix array wiring substrate, and to carry out the process when the manufacture of a matrix array wiring substrate is completed. In order to secure the S / N ratio necessary for the electrical function test, a discharge circuit having a resistance several times or more larger than that of the matrix array wiring provided between the terminal portion of the matrix array wiring and the outer peripheral wiring for short-circuit is provided in a smaller space. And the discharge circuit has the function of discharging static electricity even during the manufacturing process before the upper wiring film is deposited, but the additional etching step of the lower wiring after the formation of the upper wiring, which was required in the prior art, is omitted. It is an object of the present invention to provide a structure and a manufacturing method of a matrix array wiring substrate that can be performed.

[0012]

According to the present invention, there is provided a matrix array wiring board comprising: pixel electrodes arranged in a matrix array; switching elements provided for each pixel electrode; a plurality of address lines for controlling the switching elements; A plurality of data lines that are orthogonal to the plurality of data lines, and a short-circuit outer peripheral wiring provided outside the display area, connected to the address lines and the data lines via thin film transistors connected in parallel; Thin film transistor connected in parallel between the line and the data line and the short-circuit outer peripheral wiring,
A first thin film transistor in which a gate electrode made of a lower metal film is connected to the address line and data line terminal portion side made of the lower metal film; and a gate electrode made of the lower metal film is connected to the short-circuit outer peripheral wiring side made of the lower metal film. Second connected to
And the gate electrode of the first thin-film transistor and the gate electrode of the second thin-film transistor are opposed to each other with a gap of several μm. The gate electrode of the thin film transistor described above is also formed in a projection shape.

Further, the method of manufacturing a matrix array wiring substrate according to the present invention is directed to a method of manufacturing a first thin film transistor connected in parallel between an address line and a data line formed of a lower metal film and a short-circuit outer peripheral wiring formed of the lower metal film. Gate electrode and second
The thin film transistor is opposed to the gate electrode of the thin film transistor with a gap of several μm, and is formed in a step of patterning an address line and a data line.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention, in which a discharge circuit is laid between a terminal portion 1 made of a lower metal film, which is a part of a matrix array wiring substrate, and an outer peripheral wiring 2 for a lower layer short circuit. Part is shown.

The gate electrode 3 made of a lower metal film is connected to the terminal 1 of the lower wiring, and the first upper wiring 10 and the second upper wiring 11 are connected to each other by the amorphous Si film 6 and the first upper wiring 10.
TFT 12 is formed. Further, the gate electrode 4 made of the lower metal film is connected to the lower layer outer peripheral wiring 2 for short-circuit, and the second TFT 13 is formed by the amorphous Si film 7, the first upper wiring 10, and the second upper wiring 11. Have been.

The first TFT 12 and the second TFT
Reference numeral 13 denotes an aspect ratio (L / L) to make the on-resistance approximately 1 MΩ.
W) is set to 20 to 30.

The upper wiring 10 is connected to the terminal 1 of the lower wiring at the opening 8 of the interlayer insulating film, and the upper wiring 11 is connected to the lower short-circuiting outer wiring 2 at the opening 9 of the interlayer insulating film. I have.

In the discharge circuit having the above-described structure and function, the first gate electrode 3 and the second gate electrode 4 have a protruding shape at their opposing portions 5 so as to have 3 to 6 μm.
They are separated at an interval of m. The opposing portion 5 is formed simultaneously with the lower matrix array wiring in the patterning step of the lower metal film before the step of depositing the upper metal film, and the lower limit of the interval between the two depends on the resolution of the exposure apparatus used for patterning the lower metal film. Decided.

Next, the operation of the embodiment of the present invention will be described in detail with reference to FIG. The first part of the discharge circuit
In the manufacturing process before the TFT 12 and the second TFT 13 are functionally completed, if the lower matrix array wiring is charged to several hundred V or more, the first gate electrode 3 and the second gate
In the opposing portion 5 in which both the gate electrodes 4 have a protruding shape, a sharp discharge is generated between the terminal portion 1 and the outer peripheral wiring 2 for lower layer short-circuit, and the potential of the matrix array wiring is made uniform.

Since the facing portion 5 has a protruding shape that easily induces a sharp discharge even at an interval of 3 to 6 μm,
If a voltage of several hundred volts or more is generated between the terminal portion 1 and the lower-layer short-circuit outer peripheral wiring 2, a sharp discharge occurs, so that the terminal portion 1 is connected to the terminal portion 1 in a manufacturing process until the upper metal film is deposited. Of the TFTs arranged in the matrix array wiring portion and the functional destruction of the display pixels can be prevented.

The first TFT 12 and the second TF
In the manufacturing process after the formation of T13, if the terminal portion 1 is positively charged with respect to the lower-layer short-circuit outer peripheral wiring 2, the first
When the TFT 12 is turned on and discharged, and the terminal portion 1 is negatively charged with respect to the lower-layer short-circuit outer peripheral wiring 2, the second
TFT 13 is turned on and discharged.

In the electrical inspection at the stage of completion of the matrix array wiring board, the resistance between the terminal portion 1 of the lower layer matrix array wiring and the outer peripheral wiring 2 for the lower layer short circuit is determined by the resistance of the matrix array wiring in order to secure the S / N ratio. (20 ~
30 KΩ) or more, but the opposing portion 5 is separated at the time of patterning the lower metal film, so that the first TFT 12 and the second TFT 13 of the discharge circuit of the discharge circuit are not subjected to additional etching. ON resistance (~ 1M
Ω), the above-described necessary resistance can be obtained.

[0023]

The effect of the present invention is that the terminal portion 41 composed of the lower metal film and the lower peripheral wiring 4 for short-circuiting shown in FIG.
This is because the step of etching and cutting the connection 2 in the region of the opening 49 after forming the upper wiring can be omitted.

The reason for this is that, as shown in FIG. 1, the gate electrode 3 of the first TFT connected to the terminal portion 1 of the lower wiring and the lower peripheral wiring 2 for short-circuiting are connected in the lower metal film patterning step as shown in FIG. This is because the opposing portion 5 of the gate electrode 4 of the second TFT 13 is formed in the patterning step of the lower metal film performed before the patterning of the upper metal film. The discharge during the manufacturing process until a discharge circuit is formed
Is performed by the point discharge at

[Brief description of the drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a conventional technique.

FIG. 3 is another schematic circuit diagram of the prior art.

FIG. 4 is a plan view of a main part of FIG. 3;

[Explanation of symbols]

 1,21,31,41 Terminal part 2,42 Lower layer peripheral wiring for short circuit 3,4 Gate electrode 5 Opposing part 6,7 Amorphous Si film 8,9,45,46,49 Opening 10,11,47,48 Upper layer Wiring 12, 33, 43 First TFT 13, 34, 44 Second TFT 22, 32 Outer peripheral wiring for short circuit 23 Meandering wiring 24 TFT (matrix array section) 25 Display pixel section 27, 37 Matrix array section 35a, 35b Capacitor 36a, 36b resistance

Claims (4)

[Claims] 1. A pixel electrode arranged in a matrix array, a switching element provided for each pixel electrode, a plurality of address lines for controlling the switching element and a plurality of data lines orthogonal to the plurality of address lines are connected in parallel. And a short-circuit outer peripheral wiring provided outside the display area connected to the address line and the data line via the formed thin film transistor, wherein the address line and the data line are connected to the short-circuit outer peripheral wiring. The thin film transistor connected in parallel between the first thin film transistor in which a gate electrode made of a lower metal film is connected to the terminal portion side of the address line and the data line made of the lower metal film, and a gate electrode made of the lower metal film as a lower layer A second thin film transistor connected to the short-circuit outer peripheral wiring side made of a metal film; A gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor are opposed to each other with a gap therebetween. 2. The matrix array wiring substrate according to claim 1, wherein said gate electrodes facing each other with said gap are formed in a projecting shape. 3. The gap between the opposed gate electrodes is 3
2. The matrix array wiring board according to claim 1, which has a thickness of about 6 [mu] m. 4. A parallel connection of pixel electrodes arranged in a matrix array, switching elements provided for each pixel electrode, a plurality of address lines for controlling the switching elements and a plurality of data lines orthogonal thereto. A method of manufacturing a matrix array wiring board having a short-circuit outer peripheral wiring provided outside the display area connected to the address line and the data line via the thin film transistor,
The gate electrode of the thin film transistor connected in parallel,
A method of manufacturing a matrix array wiring substrate, comprising: forming an address line and a data line so as to face each other with a gap in a patterning step.