JP2001345452A - Thin-film transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of increased number of processes to form a contact hole in an insulation film simply by using a PR process, in order to form a thin-film shunt transistor, and although, as the method of connecting its gate wiring and its source/drain wiring with each other without using any PR process, the method of the short-circuiting of the two wirings by a laser is considered, there is generated a faultiness wherein the gate wiring of the portion irradiated by the laser is also removed therefrom to bring a disconnection. SOLUTION: In a manufacturing method of a thin-film transistor, there is used the structure that a transparent metallic film 2 and a low-resistance metallic film 3 are necessarily laminated in one wiring of the two wirings present in a laser-welded place, and the one wiring is made to overlap with the other wiring provided oppositely to it via an insulation film 5. As a result, no disconnection is generated even in the case of any laser welding and by scanning a laser beam 9 a plurality of welded places can be welded with the laser scanning of only one time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (hereinafter sometimes abbreviated as TFT), and more particularly to a process of manufacturing an electrostatic protection circuit (hereinafter referred to as a shunt transistor) around a TFT pattern. Things.

[0002]

2. Description of the Related Art In recent years, liquid crystal panels have been increasing in size and thinning, and at the same time, have the problem of electrostatic destruction which must always be solved. For this purpose, the gate terminal of the liquid crystal panel is usually connected with the gate wiring 104 naked from the gate terminal to the internal TFT array region as shown in an equivalent circuit diagram near the gate terminal in FIG. Instead, a configuration is adopted in which a shunt transistor and TFTs 121 and 123 are arranged between the common wiring 120 which is a ground potential and connected to internal elements. The same configuration is adopted for the drain terminal.

Further, a shunt transistor is formed by using the same thin film transistor as the thin film transistor used therein and short-circuiting the gate electrode of the thin film transistor and the source / drain wiring 108.

[0004]

However, in the manufacturing process of the thin film transistor, in order to form the shunt transistor, as shown in FIGS. 8A and 8B, the insulating film 105 is simply formed by using the PR process. A contact hole 115 is formed in the gate wiring 104 and the source / drain wiring 108 via the contact hole 115.
Is increased, the number of steps is increased.

Here, as a method of connecting the gate wiring 104 and the source / drain wiring 108 without using the PR process, for example, a method of short-circuiting two wirings by using a laser can be considered. As shown in FIG. 2, for example, when a laser is irradiated on the gate wiring 104 made of metal such as Cr from the transparent substrate 101 side, the insulating film 105 at the irradiated portion is removed, and the gate wiring 104 and the source / drain wiring are formed along the side wall. 108 and short circuit, but at the same time,
The gate wiring 104 of the laser irradiation part 116 is also removed,
The problem of disconnection occurs.

An object of the present invention is to provide a method of manufacturing a thin film transistor which can be formed stably and with good reproducibility when forming an electrostatic protection circuit around a TFT pattern using a laser in the method of manufacturing a thin film transistor. .

[0007]

According to a first aspect of the present invention, there is provided a thin film transistor, comprising: a substrate; a lower wiring formed on the substrate; an interlayer insulating film covering a surface of the substrate including the lower wiring; An upper wiring having an overlapping region formed on the interlayer insulating film and overlapping the lower wiring via the interlayer insulating film, wherein the lower wiring is a transparent metal material in a lower layer at least in the overlapping region. Wherein the overlapping region forms a rectangle having a width of at least 20 μm and a length of at least 20 μm.

[0008] A second thin film transistor of the present invention comprises a substrate, a lower wiring formed on the substrate, an interlayer insulating film covering the surface of the substrate including the lower wiring, and a thin film transistor on the interlayer insulating film. A thin film transistor including an upper wiring having an overlapping region formed and overlapping the lower wiring, wherein the upper wiring has an underlying semiconductor film made of a semiconductor film in a lower layer at least in the overlapping region. A semiconductor film is provided inside the overlap region, and the semiconductor film forms a channel portion and an ohmic contact portion of the thin film transistor;
That is.

In the first and second thin film transistors according to the present invention, the lower layer wiring forms a gate electrode of the thin film transistor, the interlayer insulating film forms a gate insulating film of the thin film transistor, and the upper layer wiring forms a source / drain wiring of the thin film transistor. The overlap region is an overlap region between the gate electrode of the thin film transistor constituting the electrostatic protection circuit and the source / drain wiring.

According to a first method of manufacturing a thin film transistor of the present invention, a substrate, a lower wiring formed on the substrate,
An interlayer insulating film covering the surface of the substrate including the lower wiring, and an upper wiring having an overlapping region formed on the interlayer insulating film and overlapping the lower wiring, the lower wiring in at least the overlapping region. Preparing a thin film transistor having an underlying metal made of a transparent metal material in a lower layer, irradiating a laser to the lower layer wiring in the overlapping region from the substrate side, thereby short-circuiting the lower layer wiring and the upper layer wiring. The overlap region is a rectangle having a width of 20 μm or more and a length of 20 μm or more;
That is.

According to a second method of manufacturing a thin film transistor of the present invention, a substrate, a lower wiring formed on the substrate,
An interlayer insulating film covering the surface of the substrate including the lower layer wiring, and an upper layer wiring having an overlapping region formed on the interlayer insulating film and overlapping the lower layer wiring, wherein the upper layer wiring is formed in at least the overlapping region. By preparing a thin film transistor having an underlying semiconductor film made of a semiconductor film in a lower layer, irradiating a laser to the upper layer wiring over a region including the overlapping region from the side opposite to the substrate to the upper layer wiring, thereby forming the lower layer wiring And the upper wiring is short-circuited, wherein the underlying semiconductor film is provided inside the overlapping region, and the upper wiring extends from the side opposite to the substrate to the upper wiring over a region including the overlapping region. By irradiating a laser to the upper wiring, the interlayer insulating film is removed in a region excluding the underlying semiconductor film from the overlapping region. That Shorting and the lower wiring and the upper wiring simultaneously, is that.

In the first and second methods of manufacturing a thin film transistor according to the present invention, the lower wiring is a gate electrode of the thin film transistor, the interlayer insulating film is a gate insulating film of the thin film transistor, and the upper wiring is a source / drain wiring of the thin film transistor. The overlap region is an overlap region of the gate electrode and the source / drain wiring of the thin film transistor constituting the electrostatic protection circuit,
The electrostatic protection circuit is regularly arranged repeatedly corresponding to external terminals regularly arranged around the substrate on which the thin film transistor is mounted, and is scanned in a single scan by scanning the laser in the repetition direction. A portion obtained by short-circuiting the gate electrode and the source / drain wiring of the thin film transistor constituting the plurality of electrostatic protection circuits with respect to the plurality of electrostatic protection circuits, and short-circuiting the gate electrode and the source / drain wiring of the thin film transistor. Even in a region where the laser scanning the other region intersects with the source / drain wiring, an overlapping region of the dummy gate wiring and the source / drain wiring formed simultaneously with the gate electrode is arranged, and as one application form ,
Under the source / drain wiring in the overlap region, an underlying semiconductor film made of a semiconductor film is laid.

[0013]

Next, a first embodiment of the present invention will be described with reference to FIGS. Here, components corresponding to the same components as those in FIGS. 7 and 8 used in the description of the conventional shunt transistor are denoted by the numbers obtained by subtracting 100 from the numbers in FIGS. FIG.
FIG. 2 is a schematic plan view mainly showing wiring and electrodes of a thin film transistor on a gate terminal side around a substrate according to the first embodiment. FIG. 2 is a sectional view taken along line AA ′ in FIG.
FIG. 3 is a schematic cross-sectional view taken along a cutting line BB ′ in FIG.

First, a transparent metal film 2 such as ITO (indium tin oxide) is formed as a wiring material on a transparent substrate 1 such as glass using a magnetron sputtering method or the like. The thickness is not particularly limited, but the transmittance is not reduced by 0.05 μm.
A degree is desirable.

Next, cleaning is performed to form the low-resistance wiring metal film 3.
Is formed using a magnetron sputtering method or the like. The metal material is not particularly limited, but it is preferable to use a material such as Cr. The wiring film thickness is preferably 0.2 μm or more in the case of Cr in order to short-circuit with the upper wiring by irradiating a laser or the like in a later step.

Next, a resist pattern is formed using a photolithography method. Next, using the resist pattern as a mask, first, the low-resistance wiring metal film 3 is etched by wet etching or dry etching.
The transparent metal film 2 is etched by wet etching or dry etching. Finally, the resist pattern is stripped to complete the gate wiring 4.

Next, after the insulating film 5 and the phosphorus-doped n-type semiconductor layer are formed, the n-type semiconductor layer and the semiconductor layer are patterned into islands by photolithography to form an island-like semiconductor film 12. To form

Next, the source / drain wiring 8 serving as a signal line is patterned. The configuration of the wiring material may be the same as that of the low resistance metal film 3 forming the gate wiring 4. Also,
Different materials may be used.

In the intersection area between the gate wiring 4 and the source / drain wiring 8, the shape of the overlapping area of the gate wiring 4 and the source / drain wiring 8 to be irradiated with laser in a later step is as follows:
It is preferable that the shape be 20 μm × 20 μm or more.

Next, the n-type semiconductor layer between the source / drain wiring 8 and a part of the semiconductor layer are etched (not shown).

Next, as shown in FIG. 2A, laser light 9 is irradiated from the back side of the transparent substrate 1 to dissolve the low resistance metal film 3 of the laser welding portion 10 of the gate wiring 4, and furthermore, Then, the low resistance metal film 3 is short-circuited with the source / drain wiring 8 as shown in FIG. At this time, as shown in the schematic plan view of FIG. 1, the laser light 9 scans the laser light 9 in a repetition direction in which the thin film transistors 21 and 22 are repeatedly arranged at equal intervals, as shown by a laser scanning line 16 in FIG. In this figure, TF
The gate wiring 4 and the source / drain wiring 8 of each of T21 and T22 are short-circuited.

Similarly, the thin film transistors 21, 22
The laser light 9 is also scanned in the same repetition direction as the laser scanning line 17 in FIG. 1 for each of the TFTs 23 and 24 arranged in pairs, so that the source and drain wirings 8 of the TFTs 23 and 24 are shared. Wiring 20 and FIG.
Short-circuit as shown in (a) and (b). here,
The common wiring 20 is formed simultaneously in the same step as the gate wiring 4.

Next, a passivation film 14 such as a nitride film
To form a shunt transistor for static electricity protection composed of TFTs 21 and 23 and TFTs 22 and 24,
The shunt transistors are formed corresponding to the respective gate terminals.

Thus, for example, the shunt transistor becomes a bidirectional transistor as shown in FIG. 7, and even if a high voltage is applied to the gate terminal, the shunt transistor absorbs the high voltage, thereby preventing the destruction of the internal element. It is possible to do.

Here, FIG. 1B shows that the direction of taking out the source / drain electrodes of the TFTs 21, 22, 23 and 24 shown in FIG. 1A is changed from the horizontal direction (to the paper surface) to the vertical direction. 1A is a schematic plan view showing a state of a thin film transistor when wiring and electrodes are main, and is shown as a modified example of FIG. 1A, and the laser scanning lines 16 and 17 are similar to the case of FIG. Shunt transistor is formed by irradiating the laser along the line.

Next, the manner of change in the vicinity of the shunt transistor for electrostatic protection before and after the irradiation of the laser beam 9 in the first embodiment will be described with reference to FIGS.

As shown in FIG. 2A, the area where the upper and lower wirings are short-circuited by the irradiation of the laser beam 9 always has a laminated structure of the gate wiring 4, the insulating film 5, and the drain wiring 8. The wiring layout does not have a configuration in which there is no drain wiring 8 above or no gate wiring 4 below the drain wiring 8.

As shown in FIG. 1A, the source / drain wiring 8 located at the laser scanning line 16 intersects with the laser scanning line 16 in a region other than the short-circuited portion. A gate wiring region 25 for preventing disconnection is also provided below.

After the above-mentioned laminated structure is formed, thermal welding of the gate wiring 4 and the drain wiring 8 is performed with the laser light 9.
FIG. 2B shows a schematic cross-sectional view after laser welding.

The laser light used in this embodiment is 10 μm
Although it is a line of × 10 mm, the laser irradiation device is not particularly limited. Laser irradiation is performed on gate wiring 4 or drain wiring 8
Irradiation may be performed from either of them.

FIGS. 3A and 3B show TFTs 23 and 24, respectively.
2 is a schematic cross-sectional view before and after laser irradiation when the source / drain wiring 8 and the common wiring 20 are short-circuited by irradiating a laser beam 9 along a laser scanning line 17 shown in FIG.

In the case of the conventional structure shown in FIG. 8C, when the linear laser irradiation as in the present invention is performed, the gate wiring 104 in the irradiated portion evaporates, and the gate wiring 104 is disconnected. In the present invention, by disposing the transparent metal film 2 below the low-resistance metal film 3 constituting the gate wiring 4, the transparent metal film 2 transmits laser light 9 and is not damaged when laser irradiation is performed. It was confirmed that only the low-resistance metal film 3 and the insulating film 5 sandwiched between the low-resistance metal film 3 and the source / drain wiring 8 were selectively dissolved.

As a result, as shown in FIG. 2 (b), the portion irradiated with the laser beam 9 connects the metal forming the upper source / drain wiring 8 to the lower low resistance metal film 3, and By using the transparent metal film 2 as an underlying metal film, a structure in which the wiring of the gate wiring 4 is secured is obtained.

It is preferable to carry out cleaning after completion of welding.
After the cleaning, a passivation film 14 made of a SiNx film or the like should be formed on the upper layer to prevent moisture and the like at the time of manufacturing the liquid crystal panel from adhering to the welded portions of the wires so that the wires do not disappear.

As an effect of the first embodiment of the present invention, the conventional shunt transistor usually has a contact hole 115 formed as shown in FIG. 8B to form a gate wiring 104 and a source / drain wiring 108. Was connected.

In FIG. 8B showing a conventional example, SiNx
Film or SiNx / SiO ₂ laminated film (the lower layer is SiO ₂
Or an insulating film 10 made of a SiO ₂ film.
5 is etched by dry etching or wet etching in a PR process, a contact hole 115 is formed in the insulating film 105, and then the source / drain wiring 108 is patterned and the source / drain wiring 108 is formed through the contact hole 115. Gate wiring 104
And was connected.

According to the present invention, it is possible to reduce the number of 1PR steps required for forming a contact hole in the conventional manufacturing method. Further, in the present invention, one of the wirings to be laser-welded always has a structure in which a transparent metal film and a low-resistance metal film are laminated, and one of the wirings overlaps with the other wiring disposed via an insulating film. As a result, even when laser welding is performed, disconnection does not occur, and a plurality of welding locations can be welded by one laser scan by scanning with a laser beam.

In FIG. 8A showing a conventional example, the shape of the intersection region between the gate wiring 104 and the source / drain wiring 108 is 10 μm × 10 μm or less. The volume of the metal wiring at the time of laser welding can be secured by making the shape of the intersection region with the drain wiring 8 20 μm × 20 μm or more and increasing the thickness of the insulating film 5, and the gate wiring 4 and the source can be surely formed. Connection with the drain wiring 8 became possible.

In the conventional method, there is a repair method in which the gate wiring and the source / drain wiring are spot-welded. However, as in the present invention, a laser scan is performed to collectively weld the welded portions. In addition, the welding time can be reduced.

FIG. 4 is a schematic plan view showing the state of the thin film transistor on the drain terminal side in the periphery of the panel according to the first embodiment, mainly showing wiring and electrodes.
FIG. 4A is a schematic plan view showing the case where the source / drain electrodes of the thin film transistor are taken out in the vertical direction (toward the paper surface), and FIG. Also on this drain terminal side,
In the same manner as the gate terminal side, the laser scanning line 18,
By irradiating a laser along 19, a shunt transistor is formed.

Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. Here, parts corresponding to the same parts as those in FIGS. 7 and 8 used in the description of the conventional shunt transistor are denoted by the numbers obtained by subtracting 50 from the numbers in FIGS. FIG. 5 is a schematic plan view mainly showing wiring and electrodes of a thin film transistor on the gate terminal side around the panel according to the second embodiment, and FIG. 6 is a schematic cross section taken along a cutting line CC ′ in FIG. FIG.

As in the first embodiment, the gate wiring 54
(Or, the common wiring 70), an insulating film 55, and a region where the source / drain wiring 58 are sequentially stacked are provided, and laser welding is performed along the laser scanning lines 66 and 67.

FIG. 6 shows a structure in which a semiconductor film and an island-shaped semiconductor film 62 made of an n-type semiconductor film are arranged below the source / drain wiring 58. The island-shaped semiconductor film 62 has a gate wiring 54
And the source / drain wiring 58 are arranged in a region where they intersect, and the shape of the island-shaped semiconductor film 62 is always smaller than the shape of the intersection region and is patterned so as to be inside.

Since the island-shaped semiconductor film 62 absorbs the laser beam 59 from above the transparent substrate 51, even if the island-shaped semiconductor film 62 is irradiated with the laser beam 59, the laser-welded portion on the island-shaped semiconductor film 62 is formed. The source / drain wirings 60 of the welding region remain without being melted, and the source / drain wirings 58 in the welding region are welded and connected to the gate wirings 54 along the side walls of the island-shaped semiconductor film 62.

As described above, in the present embodiment, one of the wirings to be laser-welded has a structure in which the metal wiring is formed so as to cover the island-shaped semiconductor film smaller than the laser-welded region, and And the other wiring arranged via the insulating film are overlapped with each other, so that a connection portion formed by laser welding is formed along the side wall of the island-shaped semiconductor film, which is more effective than the welding according to the first embodiment. Reliable connection is possible. Further, there is no disconnection due to laser irradiation, and it is possible to weld a plurality of welding points by one laser scanning by scanning with a laser beam.

[0046]

As described above, according to the thin film transistor and the method of manufacturing the same of the present invention, one of the wirings to be laser-welded must be formed by laminating a transparent metal film and a low-resistance metal film. By adopting a structure in which the other wiring arranged via the insulating film is superimposed, no break occurs even when laser welding is performed, and multiple laser spots are welded by one laser scan by scanning with laser light. It became possible to do.

According to another thin film transistor and a method of manufacturing the same of the present invention, one of the wirings to be laser-welded has a structure in which a metal wiring is formed so as to cover a semiconductor film smaller than the laser-welded region; By adopting a structure in which one wiring and the other wiring arranged via the insulating film are overlapped with each other, no disconnection occurs even when laser welding is performed. It has become possible to weld the welding points.

[Brief description of the drawings]

FIG. 1 is a schematic plan view on the gate terminal side of a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view taken along a cutting line in FIG.

FIG. 3 is a schematic sectional view taken along another cutting line of FIG. 1;

FIG. 4 is a schematic plan view on the drain terminal side of the thin film transistor according to the first embodiment of the present invention.

FIG. 5 is a schematic plan view on the gate terminal side of a thin film transistor according to a second embodiment of the present invention.

FIG. 6 is a schematic sectional view taken along a cutting line in FIG. 5;

FIG. 7 is an equivalent circuit diagram showing a shunt transistor used in a liquid crystal panel.

FIG. 8 is a schematic plan view and a schematic sectional view near a shunt transistor used in a conventional liquid crystal panel.

[Explanation of symbols]

1, 51, 101 Transparent substrate 2 Transparent metal film 3 Low-resistance wiring metal film 4, 54, 104 Gate wiring 5, 55, 105 Insulating film 8, 58, 108 Source / drain wiring 9, 59 Laser beam 10, 60 Laser welding Portions 12, 62 Island-like semiconductor films 16, 17, 18, 19, 66, 67 Laser scanning lines 20, 70, 120 Common wiring 21, 22, 23, 24, 71, 72, 73, 74, 1
21, 122, 123, 124 TFT 25, 75 Disconnection preventing gate wiring region 115 Contact hole 116 Laser irradiated portion

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) // G02F 1/1368 G02F 1/136 500 F term (reference) 2H092 JA24 JA37 JA41 JA47 MA05 MA13 MA17 MA30 NA14 5F033 GG04 HH17 JJ17 KK17 KK38 MM05 NN12 PP15 QQ07 QQ08 QQ09 QQ10 QQ11 QQ19 QQ53 QQ75 QQ83 RR04 RR06 VV06 VV11 VV15 XX33 XX36 5F038 AV03 BH07 BH13 CA02 EZ06 EZ20 EE20 A04 EE07 A04 AE07

Claims (17)

[Claims] A substrate, a lower wiring formed on the substrate, an interlayer insulating film covering a surface of the substrate including the lower wiring, and an interlayer insulating film formed on the interlayer insulating film. A thin film transistor comprising: an upper wiring having an overlapping region overlapping with the lower wiring through the lower wiring, wherein the lower wiring has an underlying metal made of a transparent metal material in a lower layer in at least the overlapping region. 2. A substrate, a lower wiring formed on the substrate, an interlayer insulating film covering the surface of the substrate including the lower wiring, and an overlap with the lower wiring formed on the interlayer insulating film. A thin film transistor comprising: an upper wiring having an overlapping region, wherein the upper wiring has an underlying semiconductor film made of a semiconductor film in a lower layer at least in the overlapping region. 3. The thin film transistor according to claim 2, wherein the underlying semiconductor film is provided inside the overlapping region. 4. The thin film transistor according to claim 3, wherein the semiconductor film forms a channel portion and an ohmic contact portion of the thin film transistor. 5. The lower wiring is a gate electrode of the thin film transistor, the interlayer insulating film is a gate insulating film of the thin film transistor, and the upper wiring is a source electrode of the thin film transistor.
5. The thin film transistor according to claim 1, wherein each of the drain wirings constitutes a drain wiring. 6. The thin film transistor according to claim 1, wherein the overlap region is an overlap region between a gate electrode and a source / drain wiring of a thin film transistor constituting an electrostatic protection circuit. 7. The thin film transistor according to claim 1, wherein the overlapping region has a rectangular shape with a width of 20 μm or more and a length of 20 μm or more. 8. A substrate, a lower wiring formed on the substrate, an interlayer insulating film covering the surface of the substrate including the lower wiring, and an overlap with the lower wiring formed on the interlayer insulating film. An upper layer wiring having an overlapping region to be provided, at least in the overlapping region, the lower layer wiring prepares a thin film transistor having an underlying metal made of a transparent metal material in a lower layer, and a laser is applied from the substrate side to the lower layer wiring in the overlapping region. A method of manufacturing a thin film transistor, wherein the lower wiring and the upper wiring are short-circuited by irradiation. 9. A substrate, a lower wiring formed on the substrate, an interlayer insulating film covering the surface of the substrate including the lower wiring, and an overlap with the lower wiring formed on the interlayer insulating film. A thin film transistor having an underlying semiconductor film composed of a semiconductor film in a lower layer at least in the overlapping region, and forming the overlapping region from the side opposite to the substrate in the upper wiring. A method of manufacturing a thin film transistor, wherein the lower wiring and the upper wiring are short-circuited by irradiating the upper wiring with a laser over a region to be included. 10. The method according to claim 9, wherein the underlying semiconductor film is provided inside the overlapping region. 11. irradiating a laser to the upper layer wiring over a region including the overlapping region from a side opposite to the substrate on the upper layer wiring, so that the upper layer wiring excludes the underlying semiconductor film from the overlapping region. 11. The method of manufacturing a thin film transistor according to claim 10, wherein the lower wiring and the upper wiring are short-circuited simultaneously with the removal of the interlayer insulating film. 12. The thin film transistor according to claim 8, wherein the lower wiring forms a gate electrode of the thin film transistor, the interlayer insulating film forms a gate insulating film of the thin film transistor, and the upper wiring forms a source / drain wiring of the thin film transistor.
Or the method for manufacturing a thin film transistor according to item 11. 13. The overlap region according to claim 8, wherein said overlap region is an overlap region between a gate electrode of a thin film transistor constituting a static electricity protection circuit and a source / drain wiring.
13. The method for manufacturing a thin film transistor according to 1 or 12. 14. The static electricity protection circuit is regularly arranged repeatedly corresponding to external terminals regularly arranged around a substrate on which a thin film transistor is mounted, and is scanned by a laser in the repetition direction. The gate electrode and the source electrode of the thin film transistor that constitutes the plurality of electrostatic protection circuits for the plurality of electrostatic protection circuits in one scan.
14. The method for manufacturing a thin film transistor according to claim 13, wherein a short circuit is formed between the drain wiring and the drain wiring. 15. A dummy formed simultaneously with the gate electrode in a region where the laser scanning a region other than a portion where the gate electrode and the source / drain wiring of the thin film transistor are short-circuited with the source / drain wiring. The method of manufacturing a thin film transistor according to claim 14, wherein an overlapping region of a gate wiring and the source / drain wiring is arranged. 16. The method according to claim 15, wherein an underlying semiconductor film made of a semiconductor film is laid under the source / drain wiring in the overlapping region. 17. The overlapping region has a width of 20 μm or more,
9. The method for manufacturing a thin film transistor according to claim 8, wherein the thin film has a rectangular shape having a length of 20 μm or more.