KR19990041068A - HSS capacitor formation method to prevent bridge of capacitor lower electrode - Google Patents
HSS capacitor formation method to prevent bridge of capacitor lower electrode Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 53
- 230000015572 biosynthetic process Effects 0.000 title claims 9
- 238000001312 dry etching Methods 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000009616 inductively coupled plasma Methods 0.000 claims description 17
- 238000004140 cleaning Methods 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 230000007547 defect Effects 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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Abstract
HSG 형상의 커패시터 하부전극 패턴이 형성된 반도체 기판에서 하부전극 패턴 외에 절연막 표면에 형성된 원치 않는 HSG를 제거하는 방법에 대해 개시한다. 본 발명은 절연막 표면에 형성된 원치 않는 HSG를 제거하기 위하여 커패시터 패턴을 구성하는 폴리실리콘과 절연막을 구성하는 산화막과 식각선택비가 10∼50:1의 조건이 되는 플라즈마를 이용한 건식식각을 이용하여 HSG 형상의 하부전극 패턴의 표면을 100∼500Å 정도로 에치백 함으로써 절연막 표면에 형성된 HSG를 제거한다.A method of removing unwanted HSG formed on an insulating film surface in addition to a lower electrode pattern in a semiconductor substrate on which an HSG-shaped capacitor lower electrode pattern is formed is disclosed. The present invention provides an HSG shape using dry etching using polysilicon constituting a capacitor pattern, an oxide film constituting the insulating film, and plasma having an etching selectivity of 10 to 50: 1 to remove unwanted HSG formed on the insulating film surface. The HSG formed on the surface of the insulating film is removed by etching back the surface of the lower electrode pattern at about 100 to 500 mW.
Description
본 발명은 반도체 소자의 커패시터 형성방법에 관한 것으로, 더욱 상세하게는 HSG(Hemi Spherical Grain, 이하 'HSG'라 칭함) 형상의 하부전극을 갖는 반도체 소자의 커패시터 형성방법에 관한 것이다.The present invention relates to a method of forming a capacitor of a semiconductor device, and more particularly, to a method of forming a capacitor of a semiconductor device having a HSG (Hemi Spherical Grain, hereinafter referred to as "HSG") shaped lower electrode.
반도체 소자에 대한 제조기술의 발달과 응용 분야의 확장에 따라 대용량 메모리 소자의 개발이 진척되고 있으며, 회로의 고집적화에 따라 단위 메모리 셀(cell)의 면적은 감소하고 셀 커패시턴스(cell capacitance)도 감소하고 있다. 특히, 정보의 저장 수단으로 커패시터를 사용하고, 이에 연결된 제어 가능한 신호전달 수단인 스위칭 트랜지스터(switching transistor)로 구성된 DRAM(Dynamic Random Access Memory, 이하 'DRAM'이라 칭함) 소자에 있어서, 단위 메모리 셀의 면적 감소에 따른 셀 커패시턴스의 감소는 메모리 셀의 독출 능력을 저하시키고, 소프트 에러율(soft error rate)을 증가시키므로 반도체 메모리 소자의 고집적화를 위해서는 반드시 해결되어야 할 문제이다.With the development of manufacturing technology for semiconductor devices and the expansion of their application fields, the development of high-capacity memory devices is progressing. As the integration of circuits increases, the area of unit memory cells decreases and cell capacitance decreases. have. Particularly, in a DRAM (Dynamic Random Access Memory) device, which uses a capacitor as a means for storing information and is connected to a switching transistor which is a controllable signal transmission means connected thereto, The decrease in cell capacitance due to the area decreases the readability of the memory cell and increases the soft error rate, which is a problem that must be solved for high integration of semiconductor memory devices.
메모리 셀에서의 커패시터(capacitor)의 기본 구조는 하부 전극인 스토리지 전극(storage electrode)과 유전체막 그리고 상부전극인 플레이트 전극(plate electrode)으로 구성되며, 작은 면적 내에서 보다 큰 커패시턴스를 얻기 위한 방법으로 다음과 같은 3가지 관점에서의 연구가 이루어지고 있다.The basic structure of a capacitor in a memory cell is composed of a storage electrode, which is a lower electrode, a dielectric film, and a plate electrode, which is an upper electrode, and is a method for obtaining a larger capacitance in a small area. Research from three perspectives is under way.
첫째는 유전체막의 두께 감소, 둘째는 커패시터의 유효면적 증가, 셋째는 유전상수가 큰 물질의 사용이라는 측면에서의 연구가 그것이다.The first is the reduction of the thickness of the dielectric film, the second is the increase in the effective area of the capacitor, and the third is the use of a material having a high dielectric constant.
첫째, 유전체막의 두께는 유전체의 성질과 밀접한 관계가 있으며, 두께를 제한하는 주요인은 유전체의 누설전류와 파괴전압으로, 주어진 유전체막의 두께에서 누설전류가 적어지면 적어질수록 파괴전압이 커지면 커질수록 좋은 유전체가 된다.First, the thickness of the dielectric film is closely related to the properties of the dielectric. The main factors limiting the thickness are the leakage current and breakdown voltage of the dielectric. The smaller the leakage current at a given thickness of the dielectric film, the larger the breakdown voltage is. It becomes a dielectric.
둘째, 커패시터의 유효면적을 증가시키기 위해서 플래너(planar), 트랜치(trench), 스택(stack). 실린더(cylinder)형과 이들의 복합형 등 다양한 종류의 커패시터가 형성되고 있다.Second, planar, trench, and stack to increase the effective area of the capacitor. Various kinds of capacitors are formed, such as cylinder type and combination type thereof.
셋째, 누설전류가 적고, 파괴전압이 크며, 큰 유전상수를 지니는 고유전체일수록 물리적 두께에 비하여 유전체막의 두께를 얇게 할 수 있으며, 메모리 셀의 크기를 작게 하고 커패시턴스를 증가시킬 수 있다.Third, the higher dielectric materials with less leakage current, large breakdown voltage, and large dielectric constant can make the thickness of the dielectric film thinner than the physical thickness, and can reduce the size of the memory cell and increase the capacitance.
상술한 커패시터의 유효면적을 늘리기 위한 여러 가지 방법중에서, 현재 상용화되고 있는 16 메가(Mega)에서 256 메가급의 DRAM소자에는 주로 하부전극(storage node) 표면에 반구형 그레인(HSG)을 성장시킴으로서 커패시터 표면적을 증가시켜서 커패시턴스를 증가시키는 방법이, 나머지 커패시터의 구조를 트랜치(trench)형, 실린더(cylinder)형 등과 같은 3차원 구조로 형성함으로써 커패시터 표면적을 증가시키는 방법보다 많이 응용되고 있다. 상기의 하부전극의 표면에 HSG를 성장시킴으로 커패시턴스를 증가시키는 방법은 비정질 실리콘이 다결정 실리콘으로 상 변화하는 과정에서 발생하는 특이한 물리적 현상을 이용한 것으로서, 기판에 비정질 실리콘을 증착한 후 열을 가하면 비정질 실리콘은 미세한 반구 모양의 그레인(grain)들을 형성하여 울퉁불퉁한 표면을 갖는 다결정 실리콘으로 변화하게 된다. 이러한 과정을 통하여 형성된 HSG 다결정실리콘 커패시터 하부전극(storage node)의 울퉁불퉁한 표면은 기존의 평평한 표면보다 2∼3배의 표면적이 증가된다.Among the various methods for increasing the effective area of the above-mentioned capacitor, the capacitor surface area is mainly grown by growing hemispherical grain (HSG) on the storage node surface of the DRAM device of 16 mega to 256 mega scale, which is currently commercialized. The method of increasing the capacitance by increasing is more applied than the method of increasing the capacitor surface area by forming the structure of the remaining capacitor into a three-dimensional structure such as a trench type or a cylinder type. The method of increasing the capacitance by growing the HSG on the surface of the lower electrode utilizes a unique physical phenomenon that occurs in the process of the phase change of amorphous silicon into polycrystalline silicon, and when the silicon is deposited on a substrate and then heat is applied to the amorphous silicon Is formed into fine hemispherical grains that turn into polycrystalline silicon with an uneven surface. The uneven surface of the HSG polysilicon capacitor storage node formed through this process increases the surface area by two to three times that of the conventional flat surface.
그러나 상기 HSG를 이용하여 커패시턴스를 높이는 방법에서, HSG가 성장하는 동안 HSG는 하부전극의 표면에만 성장되어야 하지만, 하부전극 외에 절연막의 표면에도 동시에 소량이 성장하는 문제점이 발생한다. 이러한 절연막 표면에 형성된 HSG는 일반적으로 습식식각(wet etch)을 통하여 제거하는데, 이에 대한 선행연구가 미합중국 특허 제 5,662,889호(title: High Capacitance capacitor manufacturing method, Date: 1997 Apr. 22)로 등록되어 있다.However, in the method of increasing the capacitance using the HSG, while the HSG is growing, the HSG should be grown only on the surface of the lower electrode, but a small amount of growth occurs simultaneously on the surface of the insulating film in addition to the lower electrode. The HSG formed on the surface of the insulating film is generally removed by wet etch, and a prior research is registered in US Patent No. 5,662,889 (title: High Capacitance capacitor manufacturing method, Date: 1997 Apr. 22). .
상술한 종래기술은 반도체 소자의 집적도가 향상되고 미세 패턴의 선폭이 급속도로 작아짐에 따라, 습식식각을 통하여 제거된 절연막 표면의 HSG 찌꺼기가 완전히 제거되지 않고 잔류함으로써, 하부전극과 하부전극 사이에서 브릿지(bridge)를 형성하여 인접하는 두 개의 비트라인 사이에 단락결함을 야기할 수 있다.In the above-described prior art, as the degree of integration of the semiconductor device is improved and the line width of the fine pattern is rapidly reduced, HSG residue on the surface of the insulating film removed through wet etching is not completely removed, thereby remaining a bridge between the lower electrode and the lower electrode. A bridge may be formed to cause a short circuit defect between two adjacent bit lines.
본 발명이 이루고자 하는 기술적 과제는 플라즈마를 이용한 건식식각으로 절연막과 식각선택비가 수십 대 일 정도로 HSG 및 절연막의 표면을 에치백하여 절연막 표면에 형성된 HSG를 제거함으로써 인접하는 두 개의 비트라인 위에 형성된 커패시터 하부전극 패턴 간의 단락결함을 억제할 수 있는 HSG 커패시터 형성방법을 제공하는데 있다.The technical problem to be achieved by the present invention is a dry etching using plasma to remove the HSG formed on the surface of the insulating film by etching back the surface of the HSG and the insulating film and the etch selectivity of several dozens of capacitors formed on the two adjacent bit lines The present invention provides a method of forming an HSG capacitor capable of suppressing short circuit defects between electrode patterns.
도 1 내지 도 3은 본 발명의 바람직한 실시예에 의한 커패시터 하부전극의 브릿지를 예방하는 HSG 커패시터 형성방법을 설명하기 위하여 도시한 단면도들이다.1 to 3 are cross-sectional views illustrating a HSG capacitor forming method for preventing a bridge of a capacitor lower electrode according to a preferred embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100: 반도체 기판, 102: 절연막,100: semiconductor substrate, 102: insulating film,
104: 비트라인 콘택홀, 106: 커패시터 하부전극 패턴,104: bit line contact hole, 106: capacitor lower electrode pattern,
108: HSG 형상의 하부전극 패턴, 110: 절연막 표면의 HSG,108: HSG-shaped lower electrode pattern, 110: HSG on the insulating film surface,
112: 건식식각이 진행된 HSG 형상의 하부전극 패턴.112: HSG-shaped lower electrode pattern subjected to dry etching.
상기 기술적 과제를 달성하기 위해 본 발명 따른 커패시터 하부전극의 브릿지를 예방하는 HSG 커패시터 형성방법은, 절연막이 형성된 반도체 기판에 HSG 형상의 하부전극 패턴을 형성한다. 그리고, 상기 HSG 형상의 하부전극 패턴이 형성된 결과물 상에 플라즈마를 이용한 건식식각을 진행하여 HSG 형상의 하부전극 패턴 외에 절연막의 표면에 형성된 HSG를 제거하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above technical problem, the HSG capacitor forming method for preventing the bridge of the capacitor lower electrode according to the present invention forms an HSG shape lower electrode pattern on the semiconductor substrate on which the insulating film is formed. And, by performing a dry etching using a plasma on the resultant formed HSG-shaped lower electrode pattern characterized in that it comprises the step of removing the HSG formed on the surface of the insulating film in addition to the HSG-shaped lower electrode pattern.
본 발명의 바람직한 실시예에 의하면, 상기 절연막은 산화막 또는 산화막을 포함하는 복합막을 사용하여 형성하고, 상기 HSG 형상의 하부전극 패턴은 비트라인(Bit Line) 위에 형성된 COB(Capacitor Over Bit Line) 구조로 형성된 것이 적합하고, 상기 하부전극 패턴은 스택형(stack type) 구조로 형성하는 것이 적합하다.According to a preferred embodiment of the present invention, the insulating film is formed using an oxide film or a composite film including an oxide film, and the HSG-shaped lower electrode pattern has a COB (Capacitor Over Bit Line) structure formed on a bit line. It is suitable that the formed, and the lower electrode pattern is preferably formed in a stack type (stack type) structure.
바람직하게는, 상기 플라즈마를 이용한 건식식각을 진행한 후에 연속해서 세정공정을 더 실시하는 것이 적합하고, 연속해서 유전체막과 상부전극을 형성하는 것이 적합하다.Preferably, after the dry etching using the plasma is carried out, it is suitable to further carry out the cleaning step, and to form the dielectric film and the upper electrode in succession.
상기 플라즈마를 이용한 건식식각은 상기 HSG형상의 하부전극 패턴과 절연막과의 식각비가 10∼50 대 1이 되도록 진행하는 것이 바람직하다.The dry etching using the plasma may be performed such that an etching ratio between the HSG-shaped lower electrode pattern and the insulating layer is 10 to 50 to 1.
바람직하게는, 상기 플라즈마를 이용한 건식식각은 TCP(Transformer Coupled Plasma) 장치를 이용하여 진행하는 것이 적합하다. 이때 공정 진행 조건은 챔버 압력을 1∼10 mTorr, 파워(power)조건으로 TCP 전극에는 250∼350 watt를 인가하고 바이어스 전극에는 100∼200 watt의 전력을 인가하는 것이 바람직하다. 또한, 식각가스로 Cl2/O2또는 Cl2/HBr를 사용하는 것이 적합하고, 챔버의 월(wall) 온도는 50∼70℃로, 바이어스 전극의 온도는 30∼50℃ 사이에서 진행하는 것이 적합하다.Preferably, the dry etching using the plasma is preferably performed using a TCP (Transformer Coupled Plasma) device. At this time, it is preferable that the process progress condition is performed by applying a chamber pressure of 1 to 10 mTorr and power to 250 to 350 watts to the TCP electrode and 100 to 200 watts to the bias electrode. In addition, it is suitable to use Cl 2 / O 2 or Cl 2 / HBr as an etching gas, the wall temperature of the chamber is 50 to 70 ℃, the temperature of the bias electrode is to proceed between 30 to 50 ℃ Suitable.
상기 플라즈마를 이용한 건식식각은 HSG 형상의 하부전극 패턴을 100∼500Å 정도로 에치백(etchback)되게 식각을 진행하는 것이 바람직하다.In the dry etching using the plasma, the etching may be performed to etch back the HSG-shaped lower electrode pattern to about 100 to 500 mW.
본 발명에 따르면, HSG 형상의 커패시터 하부전극 패턴을 형성한 후에, 절연막 표면에 형성된 원치 않은 HSG 찌거지를 높은 식각선택비를 갖는 플라즈마를 이용한 건식식각 방식으로 제거함으로써 커패시터 하부전극의 브릿지(bridge)를 예방하여 인접하는 두 개의 비트라인 사이의 단락결함을 줄일 수 있다.According to the present invention, after forming the HSG-shaped capacitor lower electrode pattern, the unwanted HSG debris formed on the surface of the insulating film is removed by dry etching using a plasma having a high etching selectivity. This prevents short-circuit defects between two adjacent bit lines.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
당 명세서에서 말하는 플라즈마를 이용한 건식식각 방식은 가장 넓은 의미로 사용하고 있으며 TCP(Transformer Coupled Plasma)와 같은 한 개의 특정 플라즈마를 이용한 건식식각 방식을 한정하는 것이 아니다. 본 발명은 그 정신 및 필수의 특징사항으로부터 이탈하지 않고 다른 방식으로 실시할 수 있다. 예를 들면, 상기 바람직한 실시예에서는 플라즈마를 이용한 건식식각을 TCP 플라즈마 장치를 이용하는 것을 일 예로 들었지만, HSG 형상의 커패시터 하부전극 패턴과 절연막과의 식각선택비가 10∼50 대 1의 선택적 식각을 할 수 있는 플라즈마를 이용한 건식식각이면 반응성 이온 식각(RIE: Reactive Ion Etching)장치, 전자 사이크로트톤 공명(ECR: Electron Cyclotron Resonance)장치, 유도 결합 플라즈마(ICP: Inductive Coupled Plasma)장치 및 표면파형 플라즈마(SWP: Surface Wave Plasma)장치 등의 장치를 이용해도 무방하다. 따라서, 아래의 바람직한 실시예에서 기재한 내용은 예시적인 것이며 한정하는 의미가 아니다.The dry etching method using plasma in the present specification is used in the widest sense and does not limit the dry etching method using one specific plasma such as TCP (Transformer Coupled Plasma). The present invention can be implemented in other ways without departing from its spirit and essential features. For example, in the above preferred embodiment, a dry etching using plasma is used as an example using a TCP plasma apparatus, but the etching selectivity between the HSG-shaped capacitor lower electrode pattern and the insulating film may be selectively etched in a range of 10 to 50 to 1. Dry etch using plasma with reactive plasma : Device such as Surface Wave Plasma device may be used. Therefore, the content described in the following preferred embodiments is exemplary and not intended to be limiting.
도 1 내지 도 3은 본 발명의 바람직한 실시예에 의한 커패시터 하부전극의 브릿지를 예방하는 HSG 커패시터 형성방법을 설명하기 위하여 도시한 단면도들이다.1 to 3 are cross-sectional views illustrating a HSG capacitor forming method for preventing a bridge of a capacitor lower electrode according to a preferred embodiment of the present invention.
도 1은 비트라인 콘택홀(104)을 갖는 절연막(102)에 커패시터 하부전극 패턴(106)을 형성하였을 때의 단면도이다.1 is a cross-sectional view when the capacitor lower electrode pattern 106 is formed in the insulating film 102 having the bit line contact hole 104.
도 1을 참조하면, 하부구조, 예컨대 트랜지스터(미도시)와 비트라인 패턴(미도시) 등이 형성된 반도체 기판(100)에 산화막 또는 산화막을 포함하는 복합막과 같은 절연막(102)을 형성한다. 이어서, 상기 절연막(102)의 표면에 포토레지스트를 도포하고 사진 및 식각공정을 진행하여 비트라인을 노출시키는 비트라인 콘택홀(Bit line contact hole, 104)을 형성한다. 상기 비트라인 콘택홀(102)이 형성된 반도체 기판에 비정질 실리콘(amorphous silicon)을 적층하고 패터닝(patterning)을 실시하여 커패시터 하부전극 패턴(106)을 형성한다. 이때, 커패시터 하부전극 패턴(104)은 표면적을 늘리기 위한 여러 가지 3차원의 구조중에서 스택형(stack type)으로 형성하는 것이 적합하다. 또한 커패시터 하부전극 패턴(104)은 비트라인 상부에 콘택홀을 뚫고 커패시터를 형성하는 COB(Capacitor over bit line) 구조를 갖는 것이 바람직하다.Referring to FIG. 1, an insulating film 102 such as an oxide film or a composite film including an oxide film is formed on a semiconductor substrate 100 on which a lower structure, for example, a transistor (not shown), a bit line pattern (not shown), or the like is formed. Subsequently, a photoresist is applied to the surface of the insulating layer 102, and a bit line contact hole 104 is formed to expose the bit line by performing a photo and etching process. Amorphous silicon is deposited on the semiconductor substrate on which the bit line contact hole 102 is formed and patterned to form a capacitor lower electrode pattern 106. In this case, the capacitor lower electrode pattern 104 may be formed in a stack type among various three-dimensional structures for increasing the surface area. In addition, the capacitor lower electrode pattern 104 preferably has a capacitor over bit line (COB) structure in which a contact hole is formed on the bit line to form a capacitor.
도 2는 상기 커패시터 하부전극 패턴(106)이 형성된 결과물에 열처리( annealing)를 수행하여 HSG 형상의 하부전극 패턴(108)을 형성하였을 때의 단면도이다.FIG. 2 is a cross-sectional view when an HSG-shaped lower electrode pattern 108 is formed by performing annealing on the resultant product in which the capacitor lower electrode pattern 106 is formed.
도 2를 참조하면, 상기 커패시터 하부전극 패턴이 형성된 결과물에 비정질 실리콘(Amorphous silicon)이 다결정 폴리실리콘(poly silicon)으로 상 변화하는 온도인 500℃ 이상에서 열처리(annealing)를 일정시간 동안 수행하여 HSG 형상의 하부전극 패턴(108)을 형성한다. 이외에도, HSG 형상의 하부전극 패턴을 형성하는 방법은 SiH4와 같은 기체소스를 이용한 저압 화학기상증착(Low Pressure Chemical Vapor Deposition) 진행하거나 또는 SiH4를 분자의 형태로 비정질의 하부전극 패턴의 표면에 조사하여 HSG 형상의 하부전극 패턴(108)을 형성할 수도 있다. 따라서, 커패시터 하부전극 패턴은 HSG 형상으로 변함에 따라 커패시터 하부전극의 표면적이 스택형의 구조일 때보다 커지게 된다.Referring to FIG. 2, HSG is performed by performing annealing at a temperature of 500 ° C. or higher for a predetermined time in which amorphous silicon is phase-changed into polycrystalline polysilicon on the resultant capacitor lower electrode pattern. A lower electrode pattern 108 having a shape is formed. In addition, the method of forming the lower electrode pattern of the HSG-shaped low-pressure chemical vapor deposition using a gas source (Low Pressure Chemical Vapor Deposition) in progress, or SiH 4, such as SiH 4 on the surface of the lower electrode pattern of the amorphous form of the molecule Irradiation may form the HSG-shaped lower electrode pattern 108. Therefore, as the capacitor lower electrode pattern is changed into an HSG shape, the surface area of the capacitor lower electrode becomes larger than when the stack type structure is used.
그러나, HSG는 비정질의 커패시터 하부전극 패턴(106) 표면에만 형성되지 않고 절연막(102) 표면에 형성된 HSG(110)가 존재하게 된다. 종래 기술에 있어서는 이러한 절연막 표면에 형성된 HSG(110)가 습식식각을 통하여 제거하는 과정에서 잔류하여 HSG 형상의 하부전극 패턴(108) 간의 브릿지를 유발함으로써 인접하는 두 개의 비트라인이 단락되는 결함이 유발되었다. 그러나 본 발명에서는 이러한 문제를 HSG 형상의 하부전극 패턴(108)을 구성하는 폴리실리콘과 절연막(102)을 구성하는 산화막과의 식각선택비가 수십대 일, 예컨대 10∼50:1의 조건이 되는 플라즈마를 이용한 건식식각 방식으로 제거함으로써 절연막(102)의 표면에 형성된 HSG(110)을 완전히 제거할 수 있다.However, the HSG is not formed only on the surface of the amorphous capacitor lower electrode pattern 106, but the HSG 110 formed on the surface of the insulating film 102 exists. In the related art, the HSG 110 formed on the surface of the insulating layer remains in the process of removing through wet etching, causing a bridge between the HSG-shaped lower electrode patterns 108 to cause a defect in which two adjacent bit lines are short-circuited. It became. However, in the present invention, this problem is solved by a plasma in which the etching selectivity between the polysilicon constituting the HSG-shaped lower electrode pattern 108 and the oxide film constituting the insulating film 102 is several tens of days, for example, 10 to 50: 1. The HSG 110 formed on the surface of the insulating layer 102 may be completely removed by using a dry etching method.
도 3은 상기 열처리(annealing)가 완료된 반도체 기판에 플라즈마를 이용한 건식식각을 진행하여 절연막(102) 표면에 형성된 HSG를 완전히 제거하였을 때의 단면도이다. 상세히 설명하면, 상기 플라즈마를 이용한 건식식각은, HSG 형상의 하부전극 패턴(108)을 구성하는 폴리실리콘과, 절연막(102)을 구성하는 산화막과의 식각선택비가 10∼50:1이 되도록 조정된 여러 가지 방식의 플라즈마를 이용한 건식식각은 진행하여 HSG 형상의 하부전극(108) 패턴 표면을 100∼500Å의 두께로 에치백(etchback)함으로써 본 발명에서 추구하는 목적을 달성할 수 있다. 그러나, 본 실시예에서는 TCP(Transformer Coupled Plasma) 장치를 플라즈마를 이용한 건식식각 장치로 사용하는 것을 일 예로 설명한다.FIG. 3 is a cross-sectional view when the HSG formed on the surface of the insulating film 102 is completely removed by performing dry etching using a plasma on the annealing completed semiconductor substrate. In detail, the dry etching using the plasma is adjusted such that the etching selectivity of the polysilicon forming the HSG-shaped lower electrode pattern 108 and the oxide film forming the insulating film 102 is 10 to 50: 1. Dry etching using various types of plasma may be performed to etch back the surface of the HSG-shaped lower electrode 108 pattern to a thickness of 100 to 500 Å to achieve the object pursued by the present invention. However, in the present exemplary embodiment, a TCP (Transformer Coupled Plasma) apparatus is used as a dry etching apparatus using plasma as an example.
먼저 TCP 장치를 이용한 공정조건을 챔버(chamber)의 압력을 1∼10 mTorr, 파워를 TCP 전극에는 250∼350watt, 바이어스 전극에는 100∼200 watt 범위로 인가한다. 그리고 챔버 내부에 흘리는 식각가스로는 Cl2/O2또는 Cl2/HBr 가스를 사용하고, 챔버 월(wall)의 온도를 50∼70℃ 범위로 조정하고, 바이어스 전극의 온도를 30∼50℃의 범위로 조정하여 일정시간 동안 건식식각을 진행함으로써 HSG 형상의 하부전극 패턴(108) 표면이 100∼500Å 정도 에치백(etchback) 된 건식식각이 진행된 HSG 형상의 하부전극 패턴(112)을 형성한다. 이때, HSG 형상의 하부전극 패턴(108)을 구성하는 폴리실리콘과 절연막(102)을 구성하는 산화막과의 식각선택비가 수십대:1이 되는 건식식각 조건으로 인해서 얇은 두께로 절연막 표면에 형성된 HSG(도 2의 참조부호 110)는 완전히 제거된다. 이어서, 세정공정을 진행하여 식각잔류물을 제거하고 유전체막 및 상부전극을 형성하여 본 발명에 의한 커패시터 하부전극의 브릿지를 예방하는 HSG 커패시터 형성 공정을 완료한다.First, the process conditions using the TCP apparatus are applied in the range of 1 to 10 mTorr pressure in the chamber, 250 to 350 watts to the TCP electrode, and 100 to 200 watts to the bias electrode. As an etching gas flowing into the chamber, Cl 2 / O 2 or Cl 2 / HBr gas is used, the temperature of the chamber wall is adjusted to a range of 50 to 70 ° C., and the temperature of the bias electrode is set to 30 to 50 ° C. By adjusting the range to dry etching for a predetermined time to form the HSG-shaped lower electrode pattern 112, the dry etching is carried out by the surface of the HSG-shaped lower electrode pattern 108 is etched back (about 100 ~ 500Å). At this time, the HSG formed on the surface of the insulating film with a thin thickness due to the dry etching condition in which the etching selectivity between the polysilicon constituting the HSG-shaped lower electrode pattern 108 and the oxide film constituting the insulating film 102 is severalteen: 1. Reference numeral 110 in FIG. 2 is completely removed. Subsequently, the cleaning process is performed to remove the etch residue and to form the dielectric film and the upper electrode to complete the HSG capacitor forming process to prevent the bridge of the capacitor lower electrode according to the present invention.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.
따라서, 상술한 본 발명에 따르면, HSG 형상의 커패시터 하부전극 패턴을 형성한 후에, 절연막 표면에 형성된 원치 않은 HSG 찌거지를 높은 식각선택비를 갖는 플라즈마를 이용한 건식식각 방식으로 제거함으로써 커패시터 하부전극의 브릿지(bridge)를 예방하여 인접하는 두 개의 비트라인 사이의 단락결함을 줄일 수 있다.Therefore, according to the present invention described above, after forming the HSG-shaped capacitor lower electrode pattern, by removing the unwanted HSG residue formed on the surface of the insulating film by a dry etching method using a plasma having a high etching selectivity of the capacitor lower electrode By preventing bridges, short-circuit defects between two adjacent bit lines can be reduced.
Claims (13)
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|---|---|---|---|
| KR1019970061600A KR19990041068A (en) | 1997-11-20 | 1997-11-20 | HSS capacitor formation method to prevent bridge of capacitor lower electrode |
| JP10133769A JPH11177031A (en) | 1997-11-20 | 1998-05-15 | Hsg capacitor formation method for preventing bridge on capacitor lower electrode |
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| KR1019970061600A KR19990041068A (en) | 1997-11-20 | 1997-11-20 | HSS capacitor formation method to prevent bridge of capacitor lower electrode |
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