KR19990040042A - Capacitor Formation Method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor, comprising: forming an interlayer insulating layer having contact holes exposing the impurity regions in a semiconductor substrate on which a transistor including an impurity region is formed; And a step of forming an electrode, a step of forming a dielectric film on the lower electrode, and a step of forming a diffusion barrier layer on the dielectric film and forming an upper electrode on the diffusion barrier layer.

Therefore, in the present invention, by forming a diffusion barrier layer on the dielectric film, the oxygen-containing dielectric film is decomposed due to the subsequent high temperature heat treatment process, thereby preventing the oxygen or the oxygen in the atomic state from being diffused to the upper layer, thereby metalizing the dielectric film. To prevent that. Therefore, in the present invention, the Ta ₂ O ₅ layer, which is a dielectric material, is prevented from being metallized, thereby preventing the occurrence of leakage current.

Description

Capacitor Formation Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a capacitor, and more particularly, to a method of forming a capacitor having a dielectric film made of a high dielectric material in order to increase capacitance in a highly integrated semiconductor device.

Many studies have been conducted to increase the storage density so that the capacitor has a constant storage capacity even if the cell area is reduced due to the high integration of the semiconductor device. In order to increase the capacitance, the capacitor was formed into a stacked or trenched three-dimensional structure to increase the surface area of the dielectric. However, stacked capacitors or trench capacitors are limited in increasing the surface area of the dielectric due to the complicated manufacturing process. Therefore, the capacitance of the capacitor is formed by using a high dielectric material such as tantalum oxide (Ta ₂ O ₅ ) or PZT (Pb (Zr Ti) O ₃ ) or BST ((Ba Sr) TiO ₃ ) to form a dielectric. A technique for increasing the has been proposed in the past.

1A to 1C are capacitor manufacturing process diagrams according to the prior art.

Although not shown in the drawing, after forming a field oxide layer defining an active region and a field region of a device on a semiconductor substrate, a gate electrode is formed on the device region of the semiconductor substrate by interposing a gate oxide layer, and the gate electrodes are formed on both sides of the gate electrode. Transistors are formed by forming an impurity diffusion region used as a source / drain region in the active region.

Referring to FIG. 1A, the silicon oxide layer 104 to be used as an interlayer insulating layer is formed on the entire surface of the semiconductor substrate 100 on which the above-described transistor is formed by chemical vapor deposition (hereinafter, referred to as CVD). Thereafter, the silicon oxide layer 104 is formed with a contact hole H1 exposing an impurity region (not shown).

Next, a polysilicon layer is formed thick by CVD to fill the contact hole H1 on the silicon oxide layer 104 so as to come into contact with the impurity region, and then a tantalum oxide layer to be used as a dielectric through the subsequent process ( Ta ₂ O ₅ ) 106 are sequentially stacked. This polysilicon layer 104 is used as a lower electrode through the following process.

The stacked tantalum oxide layer 106 is formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method or a low pressure chemical vapor deposition (LPCVD) method. ₂ H ₅ ) ₅ and O ₂ gas are used, and the reaction formula is as follows.

Ta (OC ₂ H ₅ ) ₅ + O _{2 →} Ta ₂ O _{5. … … …} (Ⅰ)

Inside the process chamber (not shown) where the tantalum oxide layer 106 is formed, a carbon component in the form of an atom or a radical remains, and the oxygen component of the tantalum oxide and the carbon component undergo a substitution reaction. Metallize the metal. In this case, the metallization of the tantalum oxide layer 106 to be used as the dielectric material has a conductive property, which may cause leakage current to flow therethrough.

Therefore, in order to prevent this, the rapid thermal oxidation treatment is performed on the tantalum oxide layer 106 in a temperature range of about 500 to 550 ° C. Therefore, the carbon component in the state of atoms or radicals remaining on the surface of the tantalum oxide layer 106 in which the deposition process is performed is made to fly in the form of CO ₂ .

Referring to FIG. 1B, a TiN layer 108 to be used as an upper electrode is formed on the thermally oxidized tantalum oxide layer 106.

Referring to FIG. 1C, the TiN layer 108, the tantalum oxide layer 106, and the polycrystalline silicon layer 104 are patterned so as to remain on the mythical silicon layer 102 and the connection hole H1 to form the lower electrode 104-1. And a dielectric layer 106-1 and an upper electrode 108-1.

However, in the conventional technology upon to laminate the TiN layer to _five-layer Ta ₂ O, Ta ₂ O oxygen component was the interface of _{the fifth} floor is to react with the TiN Ti component challenge the Ta ₂ O ₅ layer is metallized Have a temper. Therefore, there is a problem that leakage current is generated through the Ta ₂ O ₅ layer when a voltage is applied.

Accordingly, the present invention to solve the above problems is to provide a method for forming a capacitor that can prevent the dielectric is metallized by a high temperature heat treatment.

In the present invention, by interposing a diffusion barrier layer between the dielectric film and the upper electrode, the dielectric containing oxygen component is decomposed due to a subsequent high temperature heat treatment process, thereby preventing diffusion of atomic or radical oxygen into the upper layer to metallize the dielectric film. To prevent that.

The capacitor forming method of the present invention comprises the steps of forming an interlayer insulating layer having a contact hole exposing the impurity region in a semiconductor substrate on which a transistor including an impurity region is formed, and forming a lower electrode covering the contact hole on the interlayer insulating layer. And a step of forming a dielectric film on the lower electrode, and a step of forming a diffusion barrier layer on the dielectric film and forming an upper electrode on the diffusion barrier layer.

1a to 1c is a manufacturing process diagram for forming a capacitor according to the prior art.

2A to 2C are manufacturing process diagrams for forming a capacitor according to the present invention.

Explanation of symbols on the main parts of the drawings

102, 202. Silicon oxide layer 104, 204. Polycrystalline silicon layer

106, 206. Tantalum oxide layers H1, H2. Contact

108,208.TiN layer 207.SiN layer

104-1, 204-1. Lower electrodes 106-1 and 206-1. Dielectric film

108-1, 208-1. Upper electrode 207-1. Diffusion barrier

100, 200. Semiconductor Substrate with Transistors

Hereinafter, the present invention will be described with reference to the accompanying drawings.

2a to 2c is a capacitor manufacturing process according to the present invention.

2A, a silicon oxide layer 202 to be used as an interlayer insulating layer is formed on a semiconductor substrate 200 on which a transistor is formed by the method described above in the prior art, and a substrate (preferably impurity region) is formed on the silicon oxide layer. Form a contact hole (H2) that exposes. Then, on the silicon oxide layer 202, an impurity doped polysilicon layer 204 is formed sufficiently thick to fill the contact hole H2, and on the upper portion thereof, a tantalum oxide layer 206 to be used as a dielectric through a subsequent process. Laminated sequentially. The polysilicon layer 204 described above is used as a lower electrode through the following process.

At this time, as described above, the tantalum oxide layer 206 reacts with the source Ta (OC ₂ H ₅ ) ₅ and O ₂ gas to each other in a temperature range of about 400 to 450 ° C. using a PECVD method or an LPCVD method. Is formed.

When the tantalum oxide layer 206 is formed, rapid thermal oxidation at a temperature of about 500 to 550 ° C. is performed on the tantalum oxide layer 206 in order to remove carbon atoms in the form of atoms or radicals remaining in the process chamber where the CVD process is performed. Perform the process. Therefore, the carbon component remaining on the surface of the tantalum oxide layer 206 flies in the form of CO ₂ .

Referring to FIG. 2B, before forming the upper electrode on the tantalum oxide layer 206, which is a dielectric, the tantalum oxide layer 206 and the upper electrode to prevent diffusion of the tantalum oxide layer 206 into the upper layer and metallization. A diffusion barrier layer is formed in between.

SiN is used as the diffusion barrier layer and is interposed between the Ta ₂ O ₅ layer 206 and the TiN 208 layer to block the oxygen component of the Ta ₂ O ₅ layer from reacting with the Ti component of the TiN layer. The SiN layer 207 is formed to have a thickness in the range of about 300 to 500 kPa by PECVD.

After that, a TIN layer 208 to be used as an upper electrode is deposited on the SiN layer 207.

At this time, since the reaction may proceed between the Ta ₂ O ₅ layer and the SiN layer at a high temperature of 800 ° C. or higher, SiO ₂ may be formed, and the SiN layer 207 is formed at a temperature in the range of about 350 to 450 ° C.

Referring to FIG. 2C, the TiN layer 208, the SiN layer 207, the tantalum oxide layer 206, and the polycrystalline silicon layer 204 are patterned so as to remain on the siliconized silicon layer 202 and the connector H2. The electrode 208-1, the diffusion barrier layer 207-1, the dielectric layer 206-1, and the lower electrode 204-1 are formed.

In the present invention, in order to prevent the dielectric film containing the oxygen component from diffusing to the upper layer due to the high temperature heat treatment process, the diffusion film is interposed between the dielectric film and the upper electrode to prevent diffusion.

As described above, the present invention has an advantage of preventing the metallization of the dielectric film to prevent leakage current from occurring.

Claims (4)

Forming an interlayer insulating layer having a contact hole exposing the impurity region in a semiconductor substrate on which a transistor including an impurity region is formed; Forming a lower electrode covering the contact hole on the interlayer insulating layer; Forming a dielectric film on the lower electrode; Forming a diffusion barrier layer on the dielectric layer and forming an upper electrode on the diffusion barrier layer. The method according to claim 1, And the diffusion barrier layer is formed of SiN. The method according to claim 2, The SiN is a capacitor forming method characterized in that formed in the temperature range of 350 ~ 450 ℃. The method according to claim 2 or 3, Said SiN is a capacitor formation method characterized in that it has a thickness range of 300 ~ 500Å.