KR19990039436A - Implementation method of communication device of SB and MP860 of measurable processor architecture - Google Patents

Abstract

The present invention relates to a method of implementing a communication device between the SBus and the MPC860 of the Measurable Processor Architecture (SPARC) series using a dual port RAM (DPRAM), and is a high speed, dual port RAM capable of sending and receiving messages with minimal data loss. A method of using was embodied.

In practice, the use of DPRAM is not effective in the case of long or large messages, i.e. downloading, etc. Otherwise, there is no need to go through the transmission medium or protocol, which results in much better performance in terms of price and data loss prevention. Has an effect.

Description

Implementation method of communication device of SB and MP860 of measurable processor architecture

The present invention relates to a method of implementing a communication device of a SBus and an MPC860 of a scalable processor architecture (SPARC) series using dual port RAM (hereinafter referred to as DPRAM).

The communication between two different boards used in the related art can be implemented using Ethernet, high level data link control (HDLC), and US electronic industrialization (EIA-232). If the length is short and the quantity is small, there is a problem in that it is not very efficient in terms of transmission medium price, protocol management, and data loss.

In order to solve the above problems, an object of the present invention is to provide a method for communicating data between two different boards by providing a method through DPRAM, which is relatively high speed and minimizes data loss.

1 is a structural diagram of a communication apparatus of the SBus and MPC860 according to the present invention;

2 is a detailed structural diagram of a communication device according to the present invention;

3 is a structure diagram of a DPRAM to which the present invention is applied.

<Description of Symbols for Main Parts of Drawings>

100: SPARC board 110: SPARC

120: SBus 200: MPC860 Board

210: logic around DPRAM 211: DPRAM

211a: TX area 211b: RX area

211c: RX_Header area 211d: Interrupt area

212: DPRAM arbiter 213: DPRAM decoder

214: SRAM controller 215: buffer controller

216 MPC860 interrupt generator 217 TA / ACK generator

220: MPC860 230: SRAM

240: vector register

In order to achieve the above object, the present invention is characterized by consisting of a process of transmitting a message from the SBus to the MPC860, and a process of transmitting a message from the MPC860 to the SBus.

The present invention matches SBus and Motorola's Power Personal Computer (hereinafter referred to as PowerPC) used in the Scalable Processor Architecture (SPARC) series by communicating through DPRAM. It's about logic.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a structural diagram of a communication apparatus of the SBus and the MPC860 according to the present invention, which can be broadly divided into a SPARC board having an SBus 120 and an MPC860 board 200 having an MPC860 220.

Inside the MPC860 board, the logic 210 around the DPRAM is located as a communication window with the SBus 120 of the SPARC board, and the DPRAM 211 is located within the logic board.

In the logic 210 around the DPRAM, the SBus 120 and the MPC860 220 process data to be transmitted to each other.

In addition, when accessing the SBus 120 and the DPRAM 211 at the same time, a DPRAM arbiter 212 is implemented to prevent a collision, and to inform the DPRAM 211 that there is a message to be received by the other party. Interrupt handling logic is also implemented.

The MPC860 220 has eight device selection signals CS [7: 0] ^* , and the registers in the MPC860 220 may be programmed to select a device with a predetermined address map.

In the present invention, the DPRAM 211 access uses CS4 ^* and the vector register 240 access uses CS6 ^* .

The MPC860 220 ends the transmission with TA ^*, and may be driven at a predetermined time by external logic or generated inside the MPC860220.

At this time, the access time of the device should be considered. In the present invention, the DPRAM generates TA ^* in the TA / ACK generator 217 20 ns after the DPRAM arbiter 212 completes the arbitration, so that the MPC860 220 performs transmission. In this case, the vector register 240 is terminated with TA ^* generated therein.

In general, a commercial DPRAM has a built-in arbiter 212, which is convenient to use, but since the capacity is not large, a commercial static RAM (hereinafter referred to as SRAM) having an access time of 20 ns is used in the present invention (230). DPRAM 211 is implemented directly.

There may be various methods of arbitration, but in the present invention, a method of first serving the first accessor is used.

That is, the SEL ^* of the SBus 120 and the CS4 ^* of the MPC860 220 are arbitrated based on a signal driven first to serve.

The DPRAM 220 consists of an SRAM 230 having a 32-bit Long-Word port of 512 kilobytes of capacity.

Before describing the present invention in detail, the characteristics of the SBus 120 and the MPC860 220 are as follows. The basic characteristics of the SBus 120 include 32 bits of data and 28 bits of physical address bus per slot. It can transfer 1, 2, 4, 8, 16, 32, 64 bytes, has seven shared interrupt lines, and has a big-endian format.

In contrast, the MPC860 220 has a 32-bit address and data bus, can transfer 1, 2, and 4 bytes, has eight interrupt lines, eight internally programmable device select signals, and helps with external logic. The transfer can be terminated without it, and in small-endian form.

Table 1 shows the SBus 120 signal of the SPARC board in detail, and Table 2 shows the MPC860 220 signal.

SBus Signals on SPARC Boards Signal name Justice Direction (based on SBus) Remarks SA [0:27] Physical address bus Print SA27: MSB SD [0:31] Data bus I / O SD31: MSB SEL ^* Slave selection Print 1 per slave AS ^* Address valid Print Rd Transmission direction Print SIZ [2: 0] Size of data to send Print ACK [2: 0] ^* Notify transmission result input SIRQ [7: 1] ^* Interrupt request input Open drain

MPC860 signal Signal name Justice Direction (based on MPC860) Remarks MA [31: 0] Address bus Print MA0: MSB MD [31: 0] Data bus I / O MD0: MSB CS [7: 0] ^* Select device Print WE [3: 0] ^* Write transfer Print 1 byte selectable OE ^* Read transfer Print TA ^* Notify transmission result I / O Internal TA ^* Available MIRQ [7: 0] ^* Interrupt request input

2 is a detailed structural diagram of the MPC860 communication apparatus according to the present invention, which is a detailed block diagram of a communication apparatus between the SBus 120 and the MPC860 220 of the SPARC series.

2 illustrates the SRAM 230 and the DPRAM peripheral logic 210. The DPRAM peripheral logic 210 includes the DPRAM arbiter 212, the DPRAM decoder 213, the SRAM controller 214, and the buffer controller 215. MPC860 interrupt generator 216 and TA / ACK generator 217.

First, the case in which the DPRAM 211 is accessed by the SBus 120 is described in order.

SBus 120 is SEL ^* , AS ^* , Rd, SIZ [2: 0]. Drives SA [0:27] (address) and SD [0:31] (data).

At this time, if Rd is "0", a write transfer is performed, SD [0:31] is an output of the SBus 120, if Rd is "1", a read transfer is performed, and SD [0:31] is an SBus ( 120).

The DPRAM arbiter 212 senses SEL ^* and AS ^* , allowing the SBus 120 to access the DPRAM 211.

The DPRAM decoder 213 decodes SA [0:27], SIZ [2: 0], and Rd of the SBus 120.

SRAM controller 214 when the transfer write yen, a chip enable a DPCE of SRAM (230): a is [3: 0] ^*, the enable write SRAM DPWE ^* the SRAM drives, yen when the read transfer, SRAM Drive DPCE [3: 0] ^* , the chip enable of, and DPOE ^* , the read enable of SRAM.

In addition, the buffer controller 215 drives the buffer enable (SWIN), the buffer direction selection (SDIR) at the time of the write transfer or read transfer so that the SBus 120 can transfer.

If it is determined that the SBus 120 accesses the interrupt area of the DPRAM 211 by the DPRAM decoder 213, the MPC860 interrupt generator 216 drives MIRQ4 ^* to the MPC860 220 to request an interrupt.

The TA / ACK generator 217 drives ACK [2: 0] ^* to the SBus 120 after the access time of the SRAM 230 ends the transmission.

On the contrary, the case in which the DPRAM 211 is accessed in the MPC860 220 will be described sequentially.

The MPC860 220 drives CS4 ^* , WE [3: 0] ^* , OE ^* , MA [31: 0] (address), MD [31: 0] (data).

At this time, if WE [3: 0] ^* is driven, write transfer is performed, MD [31: 0] is output of MPC860, and if OE ^* is driven, read transfer is performed, and MD [31: 0] is MPC860 ( 220).

The DPRAM arbiter 212 also senses CS4 ^* and allows the MPC860 220 to access the DPRAM 211.

The DPRAM decoder 213 decodes MA [31: 0], WE [3: 0] ^* , OE ^* of the MPC860 220.

In the case of a write transfer, the SRAM controller 214 drives DPCE [3: 0] ^* , which is the chip enable of the SRAM 230, and DPWE ^* , which is the write enable of the SRAM 230, to the SRAM 230. In the case of transmission, the chip enable DPCE [3: 0] ^* and the read enable DPOE ^* of the SRAM 230 are driven to the SRAM 230.

The buffer controller 215 drives a buffer enable (MWIN), a buffer direction selection (MDIR) at the time of a write transfer or a read transfer so that the MPC860 220 can transfer.

The TA / ACK generator 217 drives TA ^* to the MPC860 220 after a predetermined time, which is an access time of the SRAM 230, to terminate transmission.

3 is a diagram illustrating a structure of a DPRAM to which the present invention is applied. The DPRAM 211 is largely comprised of a TX area 211a, an RX area 211b, an RX_Header area 211c, and an interrupt area 211d.

The TX area 211a is an area in which the SBus 120 writes a message. The TX area 211a is divided into several equally sized parts to store several messages, and each part has a flag.

The SBus 120 may write only a portion where the flag is "0", write a message in one portion of the TX area 211a, and set the corresponding flag to "1".

If all the flags of the TX area 211a are "1", if the interrupt corresponding to TX_FULL is set to the MPC860 220 in the interrupt area 211d, the MPC860 220 may set the flag of the TX area 211a. Poll

If there is a part whose flag is "1", the message is read and the flag is cleared to "0".

The RX area 211b is an area in which the MPC860 220 writes a message. The RX area 211b is divided into several equally sized parts to store several messages.

Each part has a flag, and the MPC860 220 can write only the part whose flag is "0", and writes a message in one part of the RX area 211b and sets the corresponding flag to "1". .

If the flags of the RX area 211b are all "1", the interrupt corresponding to RX_FULL is set in the vector register 240.

If the MPC860 220 has more messages to write within a certain time, it can continue to write messages.

After a certain time, the MPC860 220 writes the start address and offset of the RX area 211b in which the SBus 120 has a message to be read in the RX_Header area 211c. Check it.

The MPC860 220 sets an interrupt corresponding to RX_EN in the vector register 240 and requests an interrupt to the SBus 120.

The SBus 120 reads the RX_Header area 211c as an interrupt service to obtain the start address and offset of the RX area 211b in which the message to be read is located.

Further, after reading the message from the start address of the RX area 211b to the address plus the offset, the SBus 120 clears the corresponding flag to "0" and clears the offset of the RX_Header area 211c to "0". .

The RX_Header area 211c is composed of an address and an offset, and the MPC860 220 writes messages to the RX area 211b and, after a predetermined time, notifies the SBus 120 of its start address and offset.

The interrupt area 211d is used when the SBus 120 sets TX_FULL.

When the vector value is set from the SBus 120 in the interrupt area 211d, an interrupt MIRQ4 ^* is automatically generated in the MPC860 220, and the MPC860 220 performs an interrupt service.

The vector register 240 is in the MPC860 board, and is set when the MPC860 220 sets RX_EN or RX_FULL according to a predetermined period, and an interrupt SIRQ4 ^* is automatically generated to the SBus 120.

It should be noted in FIG. 3 that the SBus 120 processes the message in an interrupt manner, and the MPC860 220 processes the polling scheme, and the MPC860 220 sets RX_EN according to a predetermined period.

This is because the embodiment of the present invention is that SPARC is the main processor and MPC860 220 is the local processor.

In other words, since the main task is not communication with the MPC860 (220), the SPARC is treated as an interrupt instead of a burdensome polling scheme.

In addition, because each message cannot be interrupted each time, the messages collected for a certain time are processed at once.

The present invention will be described in detail with reference to FIGS. 2 and 3 as follows.

First, when the message is transmitted from the SBus 120 to the MPC860 220, the SBus 120 checks a flag of the TX area 211a of the DPRAM 211.

If there is a part with flag "0" after inspection, prepare to write a message normally.

The SBus 120 drives SEL ^* , AS *, Rd, SIZ [0:27] (address) and SD [0:31] (data).

At this time, Rd becomes "0" and write transfer is performed, and SD [0:31] becomes an output of the SBus 120.

DPRAM arbiter 212 senses the SEL ^* and AS ^* and allows SBus 120 to access DPRAM 211.

The DPRAM decoder 213 decodes SA [0:27], SIZ [2: 0], and Rd of the SBus 120.

SRAM controller 214 drives DPCE [3: 0] ^* , the chip enable of SRAM 230, and DPWE ^* , the write enable of SRAM 230, to SRAM 230.

The buffer controller 215 drives the buffer enable SWIN and the buffer direction selection SDIR so that the SBus 120 can perform a write transfer.

Meanwhile, the TA / ACK generator 217 drives ACK [2: 0] ^* to the SBus 120 after the access time of the SRAM 230 and terminates the transmission.

The SBus 120 sets the corresponding flag of the TX area 211a of the DPRAM 211 to "1".

The MPC860 220 polls a flag in the TX area 211a of the DPRAM 211 and prepares to read the message if there is a part whose flag is "1".

The MPC860 220 drives CS4 ^* , OE ^* , MA [31: 0] (address), MD [31; 0] (data).

The OE ^* is driven for read transmission, and MD [31: 0] is input to the MPC860 220.

The DPRAM arbiter 212 senses CS4 ^* and allows MPC860 220 to access DPRAM 211.

The DPRAM decoder 213 decodes MA [31: 0], OE ^* of the MPC860 220.

SRAM controller 214 drives DPCE [3: 0] ^* , the chip enable of SRAM 230, and DPOE ^* , the read enable of SRAM 230, to SRAM 230.

The buffer controller 215 drives the buffer enable MWIN and the buffer direction selector MDIR so that the MPC860 220 can perform a read transfer.

The TA / ACK generator 217 drives TA ^* to the MPC860 220 after the access time of the SRAM 230 and terminates the transmission.

The MPC860 220 clears the corresponding flag of the TX area 211a of the DPRAM 211 to "0".

If the SBus 120 does not have a portion where the flag is "0" in the flag check of the TX area 211a of the DPRAM 211, the SBus 120 accesses the interrupt area 211d of the DPRAM 211 to access the MPC860. At 220, prepare to request a TX_FULL interrupt.

In addition, the SBus 120 drives SEL ^* , AS *, Rd, SIZ [0:27] (address), SD [0:31] (data), and at this time, Rd becomes " 0 " SD [0:31] is the output of the SBus 120, so that the TA / ACK generator 217 drives ACK [2: 0] ^* to the SBus 120 after the access time of the SRAM 230. Repeat the process until the transmission ends.

At this time, the data written to the interrupt area 211d of the DPRAM 211 by the SBus 120 is not a message but a vector of TX_FULL interrupts.

The MPC860 interrupt generator 216 drives MIRQ4 ^* to request an interrupt to the MPC860 220.

MPC860 220 accepts an interrupt and prepares to begin an interrupt service routine.

The MPC860 220 drives CS4 ^* , OE ^* , MA [31: 0] (address), MD [31; 0] (data), and the OE ^* is driven for read transfer, and MD [31: 0] is repeated from the input of the MPC860 220 to the TA / ACK generator 217 to drive the TA ^* to the MPC860 220 after the access time of the SRAM 230 to terminate transmission The MPC860 220 reads the interrupt vector from the interrupt region 211d of the DPRAM 211 and performs a message read quickly to clear the corresponding flag of the TX region 211a of the DPRAM 211 to "0" and then again. The SBus 120 returns to the flag check of the TX area 211a of the DPRAM 211.

Next, when the message is transmitted from the MPC860 220 to the SBus 120, the MPC860 220 checks a flag of the RX region 211b of the DPRAM 211.

After checking the flag, if there is "0" part, prepare to write the message normally.

The MPC860 220 drives CS4 ^* , WE [3: 0] ^* , MA [31: 0] (address), MD [31: 0] (data), and WE [3: 0] ^* Driven to write transfer, MD [31: 0] is the output of the MPC860 (220).

DPRAM arbiter 211a senses CS4 ^* and allows MPC860 220 to access DPRAM 211.

The DPRAM decoder 213 decodes MA [31: 0], WE [3: 0] ^* of the MPC860 220, and the SRAM controller 214 enables the chip enable (DPCE [3: 0] of the SRAM 230. ^* ), The write enable DPWE ^* of the SRAM 230 is driven to the SRAM 230.

The buffer controller 215 drives the buffer enable MWIN and the buffer direction selector MDIR so that the MPC860 220 can perform a write transfer.

The TA / ACK generator 217 drives TA ^* to the MPC860 220 after the access time of the SRAM 230, that is, 20 ns, ends the transmission.

The MPC860 220 sets the corresponding flag of the RX area 211b of the DPRAM 211 to "1".

If there are more messages to be written by the MPC860 220 for a certain period of time, the MPC860 220 checks the flag of the RX area 211b of the DPRAM 211 and then the MPC860 220 corresponds to the RX area 211b of the DPRAM 211. Repeat until the flag is set to "1".

After a certain time, the MPC860 220 prepares to write the start address and offset of the RX region to be read by the SBus 120 in the RX_Header region 211c.

MPC860 (220) is the MPC860 the ^{CS4 *, WE [3: 0} ] *, MA [31: 0] ( the address), MD [31: 0] when the drive (data), the WE [3: 0] ^* Is driven to perform a write transfer, and MD [31: 0] becomes the output of the MPC860 220, so that the TA / ACK generator 217 has a predetermined time of access time of the SRAM 230, that is, 20 ns. The RX_Header area 211c is accessed by repeatedly driving TA ^* to the MPC860 220 to terminate the transmission.

The MPC860 220 prepares to request an RX_EN interrupt to the SBus 120, and sends CS6 ^* , WE [3: 0] ^* , MA [31: 0] (address), MD [31: 0] (data). The RX_EN interrupt vector, which means that there is a message to be read and read in the RX area 211b, is written to the vector register 240.

The WE [3: 0] ^* is driven to write transfer, and the MD [31: 0] is the output of the MPC860 220.

Vector register 240 drives SIRQ4 ^* to SBus 120 to request an interrupt for RX_EN.

SBus 120 accepts an interrupt and prepares to begin interrupt service routine 1, which is an operation that reads the interrupt vector of interrupt vector register 240.

The SBus 120 also drives SEL *, AS *, SIZ [2: 0], SA [0:27] (address) and SD [0:31] (data).

At this time, Rd becomes "1" and read transmission is performed, and SD [0:31] is input to the SBus 120.

The DPRAM arbiter 211a senses SEL ^* and AS ^* and allows the SBus 120 to access the DPRAM 211.

The DPRAM decoder 213 decodes SA [0:27], SIZ [2: 0], and Rd of the SBus 120.

The SRAM controller 214 drives DPCE [3: 0] ^* , which is the chip enable of the SRAM 230, and DPOE ^* , which is the read enable of the SRAM 230, to the DPRAM 211.

The buffer controller 215 drives the buffer enable (SWIN) and the buffer direction selection (SDIR) so that the SBus 120 can perform a read transfer.

The TA / ACK generator 216 drives ACK [2: 0] ^* to the SBus 120 after the access time of the SRAM 230, that is, 20 ns, and terminates the transmission.

The SBus 120 clears the vector register 240 to end the interrupt service routine 1.

SBus 120 drives SEL *, AS *, SIZ [2: 0], SA [0:27] (address), SD [0:31] (data), where Rd is " 1 " Is a read transfer, and SD [0:31] is the source of the interrupt vector read from the input of the SBus to the termination of the interrupt service routine 1 by the SBus clearing the vector register 240. Confirms that is RX_EN, and prepares to start interrupt service routine 2, which is an operation of reading the start address and offset of the RX_Header area 211c.

SBus 120 drives SEL *, AS *, SIZ [2: 0], SA [0:27] (address), SD [0:31] (data), where Rd is " 1 "&Quot; read transfer, and SD [0:31] is inputted to the SBus 120, so that the TA / ACK generator 217 receives the SBus after a predetermined time, which is the access time of the SRAM 230, that is, 20 ns. Interrupt service routine 2 is completed by repeatedly driving ACK [2: 0] ^* to terminate transmission at 120.

As a result, the SBus 120 obtains the start address and offset of the RX area 211b in which the message to be read is located.

The SBus 120 is configured such that the SBus 120 receives SEL *, AS *, SIZ [2: 0], SA [0:27] (address), SD from the given start address of the RX area 211b to the address plus the offset. Drive [0:31] (data), at which time Rd becomes " 1 " for read transmission, and SD [0:31] is the input of SBus 120 from TA / ACK generator 217. Reads the message repeatedly by driving ACK [2: 0] ^* to the SBus 120 after the access time of the SRAM 230, that is, 20 ns, to terminate the transmission, and sets the corresponding flag to "0". Cleared with

If the MPC860 220 does not have a portion where the flag is "0" in the flag check of the RX area 211b of the DPRAM 211, the MPC860 220 accesses the vector register 240 to RB_FULL to the SBus 120. Prepare to request an interrupt.

The MPC860 220 drives CS6 ^* , WE [3: 0] ^* , MA [31: 0] (address) and MD [31: 0] (data) to write an RX_FULL interrupt to the vector register 240.

At this time, the WE [3: 0] ^* is driven to write transfer, and the MD [31: 0] is the output of the MPC860 220.

Vector register 240 drives SIRQ4 ^* with SBus 120 to request an interrupt for RX_FULL.

The SBus 120 receives the interrupt and prepares to start the interrupt service routine 1 which is an operation of reading the interrupt vector of the vector register 240.

The SBus 120 drives SEL *, AS *, SIZ [2: 0], SA [0:27] (address), SD [0:31] (data), where Rd is " 1 " SD [0:31] is read from the input of the SBus 120 to the SBus 120 clearing the vector register 240 to terminate the interrupt service routine 1. After confirming that the source of the interrupt vector is RX_FULL, the message is read quickly to clear the corresponding flag in the RX area 211b of the DPRAM 211 to " 0 ".

The MPC860 220 then returns to the flag check of the RX region 211b of the DPRAM 211.

As described above, the present invention is not effective in using a DPRAM when downloading a message when the message is actually large, but otherwise, since it does not go through a transmission medium or a protocol, in terms of price and data loss prevention It has the effect of showing much better performance.

Claims (3)

There is a commercial logic and dual port RAM arbiter, dual port RAM decoder, commercial static RAM controller, buffer controller, dual port RAM (DPRAM) peripheral logic with TA ACK generator. In the method of implementing a communication device of the SBus and MPC860 of the measurable processor architecture (SPARC) series including TX, RX, RX_Header, and interrupt area in the DPRAM, A first step of transmitting a message from the SBus to an MPC860; And a second process of transmitting a message from the MPC860 to the SBus. The method of claim 1, wherein the first process is A first step of preparing to write a message normally when the SBus checks a flag of the DPRAM and there is a portion where the flag is "0"; The SBus drives SEL ^* , AS *, Rd, SIZ [2: 0], address SA [0:27], and data SD [0:31], where Rd is set to " 0 &quot;. A second step in which write transfer is performed, and SD [0:31] is an output of SBus; A DPRAM arbiter detects the SEL ^* and AS ^* and permits the SBus to access the DPRAM; A DPRAM decoder comprises: a fourth step of decoding SA [0:27], SIZ [2: 0], Rd of the SBus; After decoding, the SRAM controller may further include driving a chip enable (DPCE [3: 0] ^* ) and write enable (DPWE ^* ) of the SRAM into the SRAM; A buffer controller is configured to drive a buffer enable (SWIN) and a butter direction selection (SDIR) to allow the SBus to perform a write transfer; The TA / ACK generator drives a ACK [2: 0] ^* to the SBus after the access time of the SRAM to terminate transmission; An eighth step of, after the SBus sets a corresponding flag of the TX area of the DPRAM, the MPC860 polls the flag of the TX area of the DPRAM to prepare to read the message if there is a portion of which the flag is "1"; The MPC860 drives CS4 ^* , OE ^* , address MA [31: 0], and data MD [31: 0] for read transmission, and MD [31: 0] is an input of MPC860. Steps; A DPRAM arbiter detects the CS4 ^* and allows the MPC860 to access the DPRAM; The DPRAM decoder decodes MA [31: 0] and OE ^* of the MPC860, and then the SRAM controller drives DPCE [3: 0] ^* , the chip enable of SRAM, and the read enable DPOE ^* of SRAM into SRAM. 11 steps; The buffer controller includes a twelfth step of driving a buffer enable (MWIN) and a buffer direction selector (MDIR) to allow the MPC860 to perform a read transfer; The TA / ACK generator driving a TA ^* to the MPC860 after the access time of the SRAM to terminate transmission; A fourteenth step of, by the MPC860, clearing the corresponding flag of the TX area of the DPRAM to "0"; A 15th step in which the SBus prepares to request a TX_FULL interrupt to the MPC860 by accessing the interrupt area of the DPRAM if the SBus does not have a portion of the flag "0" after checking the flag of the TX area of the DPRAM; The SBus drives SEL ^* , AS *, Rd, address SIZ [0:27], data SD [0:31], write transfers with Rd set to " 0 &quot;, and SD [0]. Step 16: repeating the output from the SBus to the output of the SBus from the TA / ACK generator to driving the ACK [2: 0] ^* to the SBus after the SRAM access time; The MPC860 interrupt generator drives MIRQ4 ^* to request an interrupt to the MPC860, receives an interrupt, and prepares to start an interrupt service routine; An eighteenth step in which the MPC860 drives CS4 ^* , OE ^* , address MA [31: 0], data MD [31: 0]; The OE ^* is driven and read-transferd, and MD [31: 0] is inputted to the MPC860 until the TA / ACK generator drives TA ^* to the MPC860 after the access time of the SRAM to terminate transmission. Repeating the nineteenth step; After the repetition, the MPC860 reads the interrupt vector in the interrupt area of the DPRAM and reads the message to clear the corresponding flag in the TX area of the DPRAM to "0", and then the SBus returns to the flag check of the TX area of the DPRAM. A method of implementing a communication device of an ES BUS and an MP860 of a measurable processor structure series, comprising the steps of: The method of claim 1, wherein the second process A first step in which the MPC860 checks the flag of the RX area of the DPRAM and then prepares to write a message normally if there is a portion of "0"; The MPC860 drives CS4 ^* , WE [3: 0] ^* , address MA [31: 0] and data MD [31: 0] to perform write transfer, and MD [31: 0] is MPC860. A second step of outputting a; A DPRAM arbiter detects the CS4 ^* and permits the MPC860 to access the DPRAM; The DPRAM decoder decodes MA [31: 0] and WE [3: 0] ^* of the MPC860, and the SRAM controller enables chip enable (DPCE [3: 0] ^* ) of the SRAM and write enable (DPWE ^* ) of the SRAM. 4) driving the SRAM into the SRAM; A buffer controller is configured to drive a buffer enable (MWIN) and a buffer direction selector (MDIR) to allow the MPC860 to perform a write transfer; The TA / ACK generator is configured to drive TA ^* to MPC860 after the access time of the SRAM to terminate transmission; After the MPC860 sets the corresponding flag in the RX area of the DPRAM to "1", if there are more messages to be written by the MPC860 for a certain period of time, the MPC860 checks the flag in the RX area of the DPRAM and the MPC860 sets the corresponding flag in the RX area of the DPRAM. A seventh step of repeating the setting to "1"; After a certain time, the MPC860 prepares to write the start address and offset of the RX area to be read by the SBus in the RX_Header area, and then the MPC860 reads CS4 ^* , WE [3: 0] ^* , address (MA [31: 0])) An eighth step of driving data MD [31: 0] and performing write transfer; The MD [31: 0] outputs the MPC860, and the TA / ACK generator repeatedly accesses the RX_Header region from the time of terminating the transmission by driving TA ^* to the MPC860 after the access time of the SRAM. A ninth step; The MPC860 prepares to request the RX_EN interrupt to the SBus and then drives CS6 ^* , WE [3: 0] ^* , MA [31: 0], MD [31: 0] to indicate that the SBus has a message to be read in the RX area. A tenth step of writing an RX_EN interrupt vector to a vector register; An eleventh step in which the WE [3: 0] ^* is driven to perform a write transfer, and the MD [31: 0] is an output of the MPC860; The vector register drives SIRQ4 ^* with SBus, requests an interrupt for RX_EN, receives an interrupt, and prepares to start interrupt service routine 1, which is an operation of reading an interrupt vector of the vector register; After SBus drives SEL *, AS *, SIZ [2: 0], address (SA [0:27]) and data (SD [0:31]), Rd becomes "1" and read transfer is performed. SD [0:31] is a thirteenth step of inputting an SBus; The DPRAM arbiter detects SEL ^* and AS ^* and allows the SBus to access the DPRAM, and the DPRAM decoder includes a fourteenth step of decoding SA [0:27], SIZ [2: 0], and Rd of the SBus; The SRAM controller is configured to drive DPCE [3: 0] ^* , the chip enable of SRAM, and DPOE ^* , the read enable of SRAM, to SRAM; A buffer controller (16) for driving a buffer enable (SWIN) and a buffer direction selection (SDIR) so that the SBus can perform a read transfer; The TA / ACK generator drives an ACK [2: 0] ^* to the SBus after the access time of the SRAM to terminate transmission; An eighteenth step of terminating interrupt service routine 1 by the SBus clearing a vector register; The SBus drives reads when the SBus drives SEL *, AS *, SIZ [2: 0], address (SA [0:27]) and data (SD [0:31]), and Rd becomes "1". SD [0:31] confirms that the source of the interrupt vector read is RX_EN in the process from inputting the SBus to the SBus clearing the vector register and ending the interrupt service routine 1. A nineteenth step of preparing to start an interrupt service routine 2 which is an operation of reading a starting address and an offset of the first; The SBus drives reads when the SBus drives SEL *, AS *, SIZ [2: 0], address (SA [0:27]) and data (SD [0:31]), and Rd becomes "1". SD [0:31] is the input of the SBus, and the TA / ACK generator repeatedly drives the ACK [2: 0] ^* to the SBus after the access time of the SRAM to terminate the transmission. A twentieth step of completing interrupt service routine 2; As a result of the above process, SBus may include: a twenty-first step of obtaining a start address and an offset of an RX area in which a message to be read is located; SBus stores the SEL *, AS *, SIZ [2: 0], address (SA [0:27]), and data (SD {0:31]) from the given start address of the RX area to the address plus the offset. Drive, Rd becomes " 1 " for read transmission, and SD [0:31] becomes SBus input, so the TA / ACK generator sends ACK [2: 0] ^{* to the} SBus after the access time of the SRAM. A twenty-second step of repeatedly reading the message and clearing the corresponding flag to " 0 " Step 23, if the MPC860 does not have a portion where the flag is "0" in the flag check of the RX region of DPRAM, the MPC860 accesses the vector register and prepares to request an RX_FULL interrupt to the SBus; The MPC860 drives CS6 ^* , WE [3: 0] ^* , MA [31: 0] (address), MD [31: 0] (data) to write an RX_FULL interrupt to the vector register, and then sends the WE [3: 0 A twenty-fourth step of driving] ^* as write transfer, and MD [31: 0] as the output of the MPC860; The vector register drives SIRQ4 ^* with SBus, requests an interrupt for RX_FULL, receives an interrupt, and prepares to start an interrupt service routine 1 for reading an interrupt vector of the vector register; The SBus drives SEL *, AS *, SIZ [2: 0], address SA [0:27], data SD [0:31], and Rd becomes "1" for read transfer. SD [0:31] is a twenty-sixth step of confirming that the source of the interrupt vector read from the input of the SBus to the end of the interrupt service routine 1 by the SBus clearing the vector register is RX_FULL; After confirming that the source of the interrupt vector is RX_FULL, the message is read quickly to clear the corresponding flag in the RX area of DPRAM to "0", and then the MPC860 returns to the flag check of the RX area of the DPRAM. A method of realizing a communication device of an ES 860 and an MC 860 of a measurable processor structure series.