JPH05300198A - Communication data counting device - Google Patents

Abstract

PURPOSE:To provide a device for counting the number of the appearances at respective communication data at a high speed. CONSTITUTION:The device is provided with a RAM 11, communication LSI 12, communication data transfer circuit 13 for setting the communication data to the address of the RAM 11 by the data read requesting signal s1 of the communication LSI 12 and increment circuit 14 for reading the contents of the RAM 11 by the data read requesting signal s1 to make them incremental, and writing the incremented value to the read address. At every communication data reception, the communication data are made to be the address of the RAM 11, the increment circuit 14 is operated, and the number of the appearances is counted by received respective communication data classifications.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication data counting device used in a data terminal device or a data monitor device that requires statistics of communication data.

[0002]

2. Description of the Related Art In recent years, it has been desired to count the number of appearances of communication data at high speed by utilizing a microcomputer for various communication devices.

A conventional communication data counting device will be described below with reference to the drawings.

As shown in FIG. 4, the conventional communication data counting device includes a communication LSI 33 for interfacing the communication line 18 with the device, and a ROM 3 for storing a program.
2 and RA as a communication data buffer and work area
M35 and CPU3 that counts the number of appearances of communication data
It is composed of 1. In order to support high-speed communication, a direct memory access controller (hereinafter abbreviated as DMAC) 34 that transfers communication data from the communication LSI 33 to the RAM 35 is provided and realized.

The operation of the communication data counting device configured as described above will be described below. First, R
The processing is started when the communication data is loaded into the AM 35, and first, the communication data loaded into the RAM 35 is stored in the address register of the CPU 31. Next, the content indicated by the value stored in the address register is incremented by the addition instruction using the indirect addressing mode. Every time the communication data is taken into the RAM 35, the above process is repeated and the number of appearances of the communication data is counted by the CPU 31.

[0006]

However, in the above-mentioned conventional configuration, C required for counting communication data is required.
The PU processing time has a problem of decreasing the communication speed of countable communication data.

The present invention solves the above-mentioned conventional problems, and provides a communication data counting device capable of increasing the communication speed of communication data by counting the number of appearances of communication data at a high speed. With the goal.

[0008]

In order to achieve the above object, a communication data counting device of the present invention sets a communication data to a RAM address by a RAM, a communication LSI, and a data read request signal of the communication LSI. It comprises a communication data transfer circuit and an increment circuit for reading the contents of the RAM in response to the data read request signal, incrementing it, and writing the incremented value in the read address.

[0009]

According to the present invention, in the above structure, each time communication data is received, the communication data is set to the address of the RAM and the increment circuit is operated to increment the content of the RAM. By repeating the above operation each time communication data is received, the number of appearances of each received communication data is counted at a high speed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the communication data counting device 10 of the present embodiment uses a RAM 11, a communication line 18, a communication LSI 12 for interfacing with this device, and a data read request signal s1 from the communication LSI. RAM
A communication data transfer circuit 13 for setting communication data to the address 11, and a RAM by the data read request signal s1
It is composed of an increment circuit 14 which reads out and increments the contents of 11, and writes the incremented value into the read address.

The operation of the communication data counting device 10 configured as described above will be described below with reference to FIGS. 1 and 2. First, a data read request signal s1 notifying that communication data has been received from the communication LSI 12
When is turned on, the data transfer circuit 13 causes the communication LSI 1 to operate in the same manner as the direct memory access controller transfers communication data from the communication LSI 12 to the memory.
By turning on the data reading signal s2 of No. 2, the communication data is taken out from the communication LSI 12, and the communication data is set to the address a of the RAM 11. Further, when the data read request signal s1 is turned on, the increment circuit 14 also starts operating. RAM control circuit 17
When the chip select signal s3 and the output enable signal s4 of the RAM 11 are turned on, the value of the communication data is set as the address a of the RAM 11 as described above. Be issued. The number of appearances is passed through the addition circuit 15 of +1 to be n + 1, and the data is temporarily stored in the latch unit 16. Then, the RAM control circuit 17
When the chip select signal s3 and the write enable signal s5 of M11 are turned on, the number of appearances n + 1 captured in the latch section 16 is written in the RAM 11. Thus, the counting of one communication data is completed.

Next, as shown in FIG. 3, the system of one embodiment using the communication data counting device 10 of the present invention is a CPU 21 for controlling the entire system and an I / O for inputting / outputting signals to / from the outside. / O25, a ROM 26 for storing a program, a RAM 27 as a work area, and a connection and disconnection between the communication data counting device 10 and the CPU bus to allow the CPU 21 to read and write data in the RAM 11. It is composed of tri-state buffers 22, 23 and 24. Before starting the counting, the CPU 21 initializes all the RAM 11 in the communication data counting device 10 to zero.
After that, by turning on the signal s6 that starts counting the communication data, the data read request signal s1
Are enabled and the communication data counting device 10 starts counting. The count is ended by turning off the count enable signal s6.
Then, for example, when knowing the number of appearances of the communication data 0100, the CPU 21 can do this by reading the data at the address 0100 of the RAM 11.

[0014]

As is apparent from the above embodiments, according to the communication data counting apparatus of the present invention, the time required to count one communication data is the communication data read time of the communication LSI + RAM access time. 2 times (sum of read cycle and write cycle) + gate delay time, and communication data can be counted at high speed.
Therefore, it is possible to realize an excellent communication data counting device that improves the communication speed of countable communication data.

[Brief description of drawings]

FIG. 1 is a block diagram of a communication data counting device according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the device.

FIG. 3 is a block diagram of a system using the communication data counting device of the same embodiment.

FIG. 4 is a block diagram of a conventional communication data counting device.

[Explanation of symbols]

 10 communication data / counting device 11 RAM 12 communication LSI 13 communication data transfer circuit 14 increment circuit

Claims (1)

[Claims] 1. A RAM, a communication LSI, a communication data transfer circuit for setting communication data to an address of the RAM by a data read request signal of the LSI, and a content of the RAM read by the data read request signal. An increment circuit is provided for incrementing and writing the incremented value to the read address. Whenever communication data is received, the communication data is set to the address of the RAM and the increment circuit is operated to increase the number of appearances for each received communication data at high speed. Communication data counting device arranged to count in.