JPS62226359A - Peripheral module access system - Google Patents

Abstract

PURPOSE:To simultaneously output command signals to plural peripheral modules by one access of a CPU module by output command signals to peripheral modules when a common access signal is inputted from the CPU module. CONSTITUTION:A specific output gate is opened based on the output of a select setting section 31, and command signals are outputted from a command output section 35 to its own peripheral modules. Command signals can be outputted simultaneously to plural peripheral modules 31, 32... by one access of a CPU module 2. Thus, the command signals can be outputted to the peripheral modules by the CPU module without giving influences on a substantial processing even if the number of peripheral modules is large.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a peripheral module access method suitable for use in computer systems, etc. This invention relates to an improvement in a peripheral module access method when a module accesses multiple peripheral modules.

(Prior Art) Generally, a computer system can be represented by a schematic configuration as shown in FIG. In this computer system, in addition to a CPU module 2, a plurality of types of peripheral modules 31, 32, . . . are connected to a motherboard 1, and these CPU module 2 and each peripheral module 3s, 3
2, .

By the way, conventionally, as a means for the CPU module 2 to select a specific peripheral module and send a command signal,
A command output circuit 10 as shown in FIG. 3 is added to each peripheral module 3r, 32, . . . to create a module selection signal and thereby send the command signal to the selected peripheral module. It becomes. That is, the command output circuit 10 sets in advance select values 11111, 11QN, 110°' for specifying its own peripheral module 31, for example, by the select setting unit 11, and uses the select values and the address lines 121 to 121 of the motherboard 1 in advance. 123, and when the address value matches the select value, it outputs a signal 13 indicating that its own peripheral module 31 has been accessed. Note that 14 is an access signal line.

Further, the gate circuit 16 is connected to a data transmission line, for example 156, which transmits the command signal of its own peripheral module 31 among the data output lines 150 to 157 which transmit the command signal from the CPU 2 to the peripheral module, and the gate circuit 16 is connected to 13 is at the "high" level, the gate circuit 16 is opened and the command signal transmitted through the data transmission line 156 is output to its own peripheral module 31.

In this way, conventionally, when the CPU module 2 sends a command signal to each peripheral module 3, 32, . . . , each peripheral module 31, 32...

. . . Give an address signal for each and compare it with the select value, and select signal 1 generated by the match of the comparison result.
3, each peripheral module 31,
Since the configuration is such that command signals are sent to 32, . . . , each peripheral module 31, 32, .
...It takes time to give an address signal for each, and when the number of peripheral modules increases, the CPU
When module 2 performs its original processing, it is restricted, making it unsuitable for high-speed data processing.

(Problems to be Solved by the Invention) The present invention has been made based on the above-mentioned circumstances, and provides a peripheral that allows a CPU module to send command signals to multiple peripheral modules with just one access. The purpose is to provide a module access method.

[Structure of the invention] (Means for solving the problems) In order to solve the above problems and achieve the purpose, the present invention has the following features:
In a calculation system in which a CPU module and multiple peripheral modules exchange data through the motherboard, each peripheral module uses the preset select value of the select setting section and the peripheral module selection output from the CPU module. Compare with the address signal,
When this peripheral module selection address signal matches the select value, it is determined that its own peripheral module has been accessed, and upon receiving the common address signal output from the CPU module, it corresponds to the select value of the select setting section. The output gate is opened to send a command signal for the self-peripheral module to the self-peripheral module, and the command signal is simultaneously sent to the plurality of peripheral modules through common access by the CPU module.

(Function) By taking such measures, when a common access signal is input from the CPU module, the gates provided on the plurality of data lines can be selectively set based on the output of the select setting section that differs for each peripheral module. The command signal is output to the relevant peripheral module, so
A single access from the CPU module allows command signals to be output to multiple peripheral modules simultaneously.

(Example) An embodiment of the present invention will be described below.

As the computer system, for example, one having the configuration shown in FIG. 2 or one having a conventional general configuration is used. Therefore, here, 1 of the computer system
The explanation of the structure will be omitted, and the command output circuit shown in FIG. 1 using the method of the present invention will be explained. 1st
In the figure, the left side in the figure is connected to the motherboard 1. The lines connected to this motherboard 1 include peripheral module selection address lines 211 to 213.
, a common address line 22, a write signal line 23, and data transmission lines 240 to 247 for transmitting command signals from the CPU module 2.

On the other hand, the command output circuit includes each peripheral module 3r,
A select setting section 31 sets different select values for each of the lines 211 to 213. self-module access determining means 32 for determining whether or not it is a common access; and a common determining circuit 33 for determining whether or not it is a common access. An operation control section 34 such as a decoder which turns on the gate upon receiving a signal indicating common access, reads and outputs the output of the select setting section 31, and a tri-state buffer 7 corresponding to the output line of this operation control section 34. A gate (output gate) is provided, and a specific output gate is opened based on the output of the select setting section 31, and a command output 135 is configured to output a command signal to its own peripheral module. .

Next, the operation of the computer system configured as above will be explained.

First, when accessing each peripheral module 31, 32, . . . individually to read and write data, an address signal for peripheral module selection is sent from the CPU module 2 side to the address lines 211 to 213 of the motherboard 1. At the same time, an individual determination signal of, for example, low level 0'0' is sent to the common address line 22 for individual access. Here, select setting section 3
The output of 1 and the address signals of address lines 211 to 213 are compared line by line, and when they match, a low level signal is output. Further, the common address line 22 is a low level signal, and as a result, a select signal is output from the logic circuit 321 to indicate that its own peripheral module has been accessed.Thus, each peripheral module 3s, 32, ..., data is read or written in response to this select signal.

Next, the CPU module 2 connects multiple peripheral modules to /[/
31, 32, . . . to send a command signal, a high level signal 111.11 is set on the common address line 22. Then, the common judgment circuit 33 judges that it is a common access from the level of the address line 22, and turns on the gate of the operation $1 sin section 34. As a result, the operation control section 34 takes in and decodes the selection value set by the selection setting section 31, opens the output gate corresponding to the selection value, and passes the command through the output gate in the open state. A signal is transmitted. Here, each peripheral device module 31
, 32,... have different select values set, so the select 11! ! The corresponding output)] gate is opened and the command signal is output to each peripheral module 31, 32 through a respective different data transmission line 24[1-247. Note that this computer system is shown as an example in which eight peripheral modules are provided.

In this way, according to this embodiment, a plurality of peripheral modules 31, 3 can be accessed by one access of the CPU module 2.
2, . . . at the same time. Therefore, even if there are a large number of peripheral modules, the CP (J module) can output command signals to each peripheral module without affecting the original processing.

Note that the present invention is not limited to the above embodiments.

For example, in the embodiment described above, an 8-bit CPU has been described, but the present invention can be similarly applied to a 16-bit or 32-bit CPU. It goes without saying that various other modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a peripheral module access method in which a CPU module can send command signals to a plurality of peripheral modules with just one access.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a command output circuit according to the gist of the method of the present invention, FIG. 2 is a schematic diagram of a computer system, and FIG. 3 is a block diagram of a command output circuit to which the conventional method is applied. 1...Motherboard, 2...CPU module, 3
1.32 ,... peripheral module, 31...
- Select setting unit, 32...Self module access judgment means, 33...Common judgment circuit, 34...Operation control unit, 35...Command output unit. Applicant's agent Patent attorney Takehikomasa Suzue 2 Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a computer system in which a CPU module and a plurality of peripheral modules exchange data through a motherboard, each of the peripheral modules receives a preset selection value from a select setting section and a peripheral module selection address signal output from the CPU module. Compare with
self-module access determination means that determines that its own peripheral module has been accessed when the peripheral module selection address signal matches the select value; and a selection setting section that receives a common address signal output from the CPU module. a common access means for opening an output gate corresponding to a select value and sending a command signal for the self-peripheral module to the self-peripheral module; the common access means for sending the command signal to the plurality of peripheral modules simultaneously by the common access by the CPU module; A peripheral module access method characterized by transmitting.