JPH05197654A - Communication control system - Google Patents

Abstract

PURPOSE:To improve efficiency for processing data by directly transferring the plural kinds of data to respective buffers by providing means to discriminate the kind of received data and to start a direct memory access(DMA) controller. CONSTITUTION:An information processor 6 is composed of a CPU 1, main storage device (MS) 2, DMA controller 3, communication control part 4 and bus 5 to connect these parts. The communication control part 4 is provided with a received data discrimination part 8. The received data discrimination part 8 discriminates the kind of data received from a line 7 and starts the DMA controller 3 through a DMA request signal line 9. The DMA controller 3 requests a bus right to the CPU 1 and when the bus right is dispatched from the CPU 1, DMA is permitted to the communication control part 4. The communication control part 4 directly transfers the received data to a buffer 10 or 11, which is set by the CPU 1 beforehand, in the MS 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control system in an information processing apparatus for transferring received data using a DMA controller.

[0002]

2. Description of the Related Art As an example of a conventional DMA system, "Direct Memory Memory" disclosed in Japanese Patent Laid-Open No. 3-75859 is disclosed.
"Access control device".

In this DMA system, in order to surely execute the highest priority DMA processing in a short time, the DMA controller has a plurality of memory control circuits for outputting DMA requests and a priority order for the DMA requests. A DMA controller that performs setting and performs DMA, and when the highest priority DMA request signal is periodically generated, when the highest priority DMA request signal is activated, the DMA request signal of the other DMA request signal is transmitted from a predetermined time before the activation. It is composed of a DMA arbiter circuit that prohibits input to the DMA controller. When it is known in advance that the highest priority DMA request signal is periodically generated, the DMA controller sends all DMA request signals sent from the plurality of memory control circuits to the DMA controller to the DMA arbiter circuit. Enter and usually the highest priority D
The DMA request signals other than the MA request signal pass through the DMA arbiter circuit and are input to the DMA controller, where the DMA processing is performed as in the conventional case. However, the highest priority DM
At a fixed time before the A request signal is generated, another D
The MA request signal is prohibited from being input to the DMA controller by the DMA arbiter circuit.
The A request signal is accepted.

[0004]

In the above-mentioned prior art, as shown in FIG. 2, in the information processing device 6 including the CPU 1, the MS 2, the DMA controller 3, the communication control unit 4 and the bus 5 connecting these, from the line 7 The procedure for storing the received data in the buffer (10 or 11) for each data type is as follows. Communication control unit 4
When it receives data from the line 7, it stores the data in the internal buffer 12 and notifies the CPU 1 that the data has been received. The CPU 1 determines the data in the internal buffer 12 and activates the corresponding DMA controller 3. here,
In the DMA controller 3, it is assumed that the CPU 1 presets the buffer address for each received data type. Therefore, the DMA controller 3 uses the internal buffer 1
The received data is transferred from 2 to the corresponding buffer.

Since it takes time to store the received data in the internal buffer 12 and to determine the received data by the CPU 1, the transfer of the received data to the corresponding buffer is delayed, and the reception processing efficiency is lowered. That is,
There is a problem that the amount of data that can be received within a fixed time is small (throughput is low).

An object of the present invention is to provide a communication control system that solves the above problems.

[0007]

In order to achieve the above object, the present invention provides a CPU 1, an MS 2 and a DM as shown in FIG.
An information processing device 6 including an A controller 3, a communication control unit 4 and a bus 5 connecting them is provided with a reception data discriminating unit 8 for discriminating data received from a line 7.

[0008]

The operation of the present invention will be described with reference to FIG. In the above means, the received data discriminating unit 8 discriminates the type of data received from the line 7, and the D data is transmitted via the DMA request signal line 9.
The MA controller 3 is activated. DMA controller 3
Directly transfers the received data from the communication control unit 4 to the buffer preset by the CPU 1 according to the DMA request signal line 9.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a configuration diagram of this embodiment. The information processing device 6 includes a CPU 1, an MS 2, a DMA controller 3, a communication control unit 4, and a bus 5 connecting these.
When the CPU 1 receives the bus right request signal (BRQ 21) from the DMA controller 3, the CPU 1 transfers the bus right in BACK 22. Also, an interrupt signal (INT0
Upon receiving (19) or INT1 (20), the corresponding process is performed. The MS2 is provided with two buffers 10 and 11. The DMA controller 3 is provided with an address register 0 (13) and an address register 1 (14) that hold the DMA destination address. Addresses can be set in the two address registers 13 and 14 from the CPU 1 via the bus 5. When the DMA controller 3 receives the DMA request signal (DRQ0 (16) or DRQ1 (17)) from the communication control unit 4, it sends a BRQ to the CPU 1.
Request bus right at 21. Then, from the CPU 1, the BAC
When the bus right is transferred at K22, DACK is sent to the communication control unit 4.
DMA is allowed at 18. The communication control unit 4 includes a reception data discriminating unit 8 for discriminating the data received from the line 7 and a byte count register 1 for indicating the number of bytes of the received data.
5 is provided. The reception data discrimination unit 8 discriminates the data received from the line 7 and sends the DM to the DMA controller 3.
A request signal (DRQ0 (16) or DRQ1 (1
7)) is generated. And from the DMA controller 3 to D
When receiving the MA permission signal (DACK 18), the received data is sent out on the bus 5. Further, when the DMA of all the received data is completed, the received data length is set in the byte count register 15 and INT1 (19) or INT is set in the CPU1.
Interrupt at 1 (20). Byte count register 15
Can be read from the CPU 1 via the bus 5.

Here, it is assumed that the information processing device 6 is connected to FDDI which is one of standard local area networks. In FDDI, a frame for transmitting normal user data and an SMT for performing station management.
Handles two types of frames. These two types of frames are treated as MAC frames on the Media Access Control layer. In Figure 4, M
The format of an AC frame is shown. MAC frame 2
3 is an FC for indicating the type of frame in the first byte
It has a field 24. FIG. 5 shows the FC of the SMT frame.
The format of the field. The SMT frame is
Bit 25 of the sixth power is "1".

In addition, a normal user data frame and SMT
Since the processing contents of the frame are different, it is necessary to divide the receiving buffer. Therefore, the two buffers 10 and 11 are assigned to the user data frame buffer and the SMT frame buffer, respectively. FIG. 6 shows a memory map of MS2. The user data frame buffer 10 is 10,000
From the address 000H, the SMT frame buffer 11 is 20
Assign from address 000000H.

In the information processing device 6 as described above, S
The processing procedure when an MT frame is received will be described below. The CPU 1 sends the start address 10000000H of the user data frame buffer 10 and the start address 20000 of the SMT frame buffer 11 via the bus 5.
Address 000H is set in the address register 0 (13) and the address register 1 (14) of the DMA controller 3, respectively. The CPU 1 activates reception of the communication control unit 4 via the bus 5. The communication control unit 4 receives the SMT from the line 7.
When the frame is received, the first byte of the received data is passed to the received data discriminating unit 8. The received data discrimination unit 8 recognizes that the sixth bit of the data is “1”, and DM
DRQ1 (17) is generated for the A controller 3 (hereinafter, the communication control unit 4 generates DRQ1 when there is received data). DMA controller 3 is CP
Generates BRQ1 (21) for U1. CPU1
Returns a BACK 22 to the DMA controller 3 after the access cycle ends. DMA controller 3
Responds DACK 18 to the communication control unit 4. The communication control unit 4 sends out the received data on the bus 5.
The DMA controller 3 takes in the data on the bus 5 and releases the DACK 18. The communication control unit 4 stops sending data to the bus 5. DMA controller 3
Indicates the address (2000 indicated by the address register 1 (14).
The previously fetched data is written to the address (0000H).
Then, the DMA controller 3 increments the content of the address register 1. If DRQ1 has occurred, the above process is repeated. If not, the DMA controller 3 releases the BRQ1 (21) for the CPU1. On the other hand, when the communication control unit 4 completes the reception of the SMT frame, the SM received by the byte count register 15 is received.
Set the number of bytes in the T frame. And received SM
When all T frames are transferred, INT1 is sent to CPU1.
(20) is generated. CPU 1 DMs via bus 5
The contents of the address register 1 (14) of the A controller 3 and the byte count register 15 of the communication control unit 4 are read, and the transferred data is confirmed and processed. The SMT frame reception process is performed as described above. In the reception processing of the user frame data, the received data discriminating unit 8 generates the DRQ request signal to the DMA controller 3 and outputs the DRQ.
0 (16), the DMA controller 3 uses the address register 0 (13) as a transfer destination, and uses INT0 (19) as an interrupt signal from the communication control unit 4 to the CPU 1 in the same manner as in the SMT frame reception processing. is there.

[0013]

According to the present invention, a plurality of types of data can be directly transferred to the respective buffers, so that there is an effect that the data processing capability is enhanced.

[Brief description of drawings]

FIG. 1 is a schematic diagram of the present invention.

FIG. 2 is a configuration diagram of a conventional technique.

FIG. 3 is a configuration diagram of an embodiment of the present invention.

FIG. 4 is a format diagram of a MAC frame.

FIG. 5 is a FC field format diagram of an SMT frame.

FIG. 6 is a memory map diagram of the embodiment of the present invention.

[Explanation of symbols]

1 ... CPU, 2 ... MS, 3 ... DMA controller, 4 ...
Communication controller, 5 ... Bus, 6 ... Information processing device, 7 ... Line,
8 ... Received data discrimination section, 9 ... DMA request signal, 10, 1
1 ... Buffer, 13 ... Address register 0, 14 ... Address register 1, 15 ... Byte count register, 16
... DRQ0, 17 ... DRQ1, 18 ... DACK, 19 ...
INT0, 20 ... INT1, 21 ... BRQ, 22 ... BA
CK, 23 ... MAC frame format, 24 ... FC
field

Claims (6)

[Claims] 1. A central processing unit (hereinafter, referred to as a CPU), a main storage device (hereinafter, referred to as an MS), a direct processing unit.
A communication control method in an information processing apparatus including a memory access (hereinafter referred to as DMA) controller, a communication control unit, and a bus connecting these, and means for determining the type of received data and activating a DMA controller is provided. A communication control method characterized in that 2. An information processing apparatus comprising a CPU, an MS, a DMA controller, a communication control section and a bus connecting them, wherein a received data discriminating section for discriminating the type of received data and activating the DMA controller is provided. Information processing device. 3. A received data discriminating unit for discriminating the kind of received data and activating the DMA controller, which is a communication control controller in an information processing apparatus comprising a CPU, an MS, a DMA controller, a communication control unit and a bus connecting these. A communication control controller characterized by being provided. 4. The communication control system according to claim 1, wherein a station management frame (hereinafter referred to as an SMT frame) in FDDI is discriminated. 5. The received data discriminating unit according to claim 2,
An information processing device characterized by discriminating an SMT frame in DDI. 6. The received data discriminating unit according to claim 3,
A communication control controller characterized by discriminating an SMT frame in DDI.