KR19990037687A - Tuning control method - Google Patents

Abstract

The tuning mechanism includes a frequency control circuit 2 including a tuning circuit 1, a synchronous rectification circuit 3 and a pulse conversion circuit 5, a polarity determination circuit 6, and a voltage synthesis circuit 7 formed by cascading two or more abnormal circuits and non-inverting circuits I have. The synchronous rectifying circuit 3 synchronously rectifies the input signal in synchronism with the output of the inquiry circuit 1, and the pulse converting circuit 5 generates a synchronous rectifying output signal corresponding to the shift (phase difference) between the frequency of the input signal and the tuning frequency And outputs a signal having a pulse width. The polarity discrimination circuit 6 discriminates the polarity of the phase difference and the voltage synthesizing circuit 7 synthesizes the voltage corresponding to the pulse outputted from the pulse conversion circuit 5 to a predetermined voltage in accordance with the polarity of the discriminated phase difference, And generates a control voltage for application. Further, the inquiry route 1 adds the tuning frequency to the frequency of the input signal of the inquiry route 1 based on the control voltage from the frequency control circuit 2.

Description

Tuning control method

A filter and a tuning circuit having various configurations using LC resonance or the like are known. For example, an intermediate frequency amplifier circuit of a superheterodyne receiver includes a function as a filter, and a conventional intermediate frequency amplifier circuit generally realizes a desired frequency characteristic by using a plurality of intermediate frequency transformers (IFT) and capacitors have. For example, in the case of an AM receiver, a center frequency of 455 kHz is set and a predetermined amount is attenuated when 9 kHz is detuned from the center frequency. An AM receiver that realizes a desired frequency characteristic by using one ceramic filter instead of plural sets of intermediate frequency transformers is also known.

However, in the conventional technique using the superheterodyne method described above, since the intermediate frequency wave amplifier circuit, which is a filter for tuning, includes an intermediate frequency wave transformer or a ceramic filter, the entirety including them is integrated on the semiconductor substrate It was difficult.

A local oscillation circuit combined with the intermediate frequency amplifier circuit is realized by an LC oscillator using a local oscillation transformer, and a PLL structure using crystal oscillation is realized when the oscillation circuit has a high accuracy. Particularly, when the local oscillation circuit has a PLL configuration, since it includes a voltage-controlled oscillator (VCO) that performs sinusoidal oscillation, integration is difficult and a part of the hybrid IC is used.

In this way, it is difficult to integrate not only the intermediate frequency amplifier circuit operating as a filter but also the local oscillation circuit constituting the tuning mechanism in combination with them, and a tuning control system capable of integrating the entire tuning mechanism is preferable. In addition, even if the entirety of a conventional filter or a circuit including this filter is integrated, a large variation occurs in the circuit constant, so that different characteristics are produced for each manufactured chip. Furthermore, since the center frequency may considerably vary depending on the temperature or the like, it is possible to surely achieve the desired frequency characteristics even when the center frequency is integrated

The present invention does not have a tuning control scheme conventionally.

And a tuning control method of passing only a predetermined frequency signal.

1 is a configuration diagram of a tuning mechanism which is an embodiment to which the tuning control method of the present invention is applied;

2 is a circuit diagram showing a detailed configuration of a tuning circuit;

Fig. 3 is a circuit diagram showing the configuration of the abnormal circuit of the preceding stage shown in Fig. 2; Fig.

4 is a vector diagram showing a relationship between an input / output voltage of the abnormal circuit shown in FIG. 3 and a voltage appearing in a capacitor or the like.

Fig. 5 is a circuit diagram showing the configuration of the abnormal circuit at the subsequent stage shown in Fig. 2; Fig.

6 is a vector diagram showing a relationship between an input / output voltage of the ideal circuit shown in FIG. 5 and a voltage appearing in a capacitor or the like.

Fig. 7 is a circuit diagram in which the entirety of two abnormal circuits and the voltage divider circuit shown in Fig. 2 are replaced with a circuit having a transfer function K1; Fig.

Fig. 8 is a circuit diagram of the circuit shown in Fig. 7 converted by the Miller's theorem. Fig.

Fig. 9 is a diagram showing tuning characteristics of the tuning circuit shown in Fig. 2; Fig.

10 is a diagram showing a phase relationship between signals input to and output from two or more circuits;

Fig. 11 is a diagram showing the phase relationship between input / output signals of the respective anomalous circuits when the tuned frequency is higher than the frequency of the signal input to the anomaly circuit at the previous stage. Fig.

Fig. 12 is a diagram showing the phase relationship between input / output signals of the respective anomalous circuits when the tuned frequency is lower than the signal frequency inputted to the anomaly circuit at the previous stage. Fig.

13 is a circuit diagram showing a detailed configuration of a frequency control circuit;

14 is a timing chart when the tuning frequency of the tuning circuit is higher than the frequency of the signal input to the tuning circuit.

15 is a timing chart when the tuning frequency of the tuning circuit is lower than the frequency of the signal input to the tuning circuit.

16 is a diagram showing a configuration of a tuning mechanism that also serves as AM detection.

Fig. 17 is a circuit diagram showing the detailed configuration of the frequency control circuit shown in Fig. 16. Fig.

Fig. 18 is a diagram showing the configuration of an AM receiver using the tuning mechanism shown in Fig. 16. Fig.

19 is a diagram showing a configuration of a tuning mechanism that also serves as an FM detection.

20 is a circuit diagram showing a detailed configuration of the frequency control circuit shown in Fig. 19;

21 is a circuit diagram showing another configuration example of the frequency control circuit;

22 is a timing chart when the tuning frequency of the tuning circuit is higher than the frequency of the signal input to the tuning circuit shown in Fig.

23 is a timing chart when the tuning frequency of the tuning circuit is lower than the frequency of the signal input to the tuning circuit shown in Fig.

24 is a circuit diagram showing another configuration example of the frequency control circuit;

25 is a timing chart when the tuning frequency of the tuning circuit is higher than the frequency of the signal input to the tuning circuit shown in Fig.

26 is a timing chart when the tuning frequency of the tuning circuit is lower than the frequency of the signal input to the tuning circuit shown in Fig.

27 is a circuit diagram showing another configuration example of the frequency control circuit;

Fig. 28 is a timing chart when the tuning frequency of the tuning circuit is higher than the frequency of the signal input to the tuning circuit shown in Fig. 27; Fig.

Fig. 29 is a timing chart when the tuning frequency of the tuning circuit is lower than the frequency of the signal input to the tuning circuit shown in Fig. 27; Fig.

30 is a circuit diagram showing a configuration of an abnormal circuit including an LR circuit;

31 is a vector diagram showing a relationship between an input / output voltage of the abnormal circuit shown in Fig. 30 and a voltage appearing on a capacitor or the like. Fig.

32 is a circuit diagram showing another configuration of an ideal circuit including an LR circuit;

33 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 32 and the voltage appearing on the capacitor or the like.

34 is a circuit diagram showing a second modification of the tuning circuit;

35 is a circuit diagram showing a configuration of an ideal circuit including an LR circuit;

36 is a circuit diagram showing another configuration of an ideal circuit including an LR circuit;

37 is a circuit diagram showing a fourth modification of the tuning circuit;

38 is a circuit diagram showing a fifth modification of the tuning circuit;

39 is a circuit diagram showing a sixth modification of the tuning circuit;

40 is a circuit diagram showing a seventh modification of the tuning circuit;

41 is a circuit diagram showing a eighth modification of the tuning circuit;

Fig. 42 is a circuit diagram showing the configuration of the preceding stage anomaly circuit shown in Fig. 41. Fig.

Fig. 43 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 42 and the voltage appearing on the capacitor or the like.

Fig. 44 is a circuit diagram showing the configuration of the abnormal circuit at the rear end shown in Fig.

45 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in FIG. 44 and the voltage appearing on the capacitor or the like.

46 is a circuit diagram showing a configuration of an abnormal circuit including an LR circuit;

47 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 46 and the voltage appearing on the capacitor or the like. Fig.

48 is a circuit diagram showing another configuration of the ideal circuit including the LR circuit;

Fig. 49 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 48 and the voltage appearing on the capacitor or the like. Fig.

50 is a circuit diagram showing a tenth modification of the tuning circuit;

51 is a circuit diagram showing a modification 11 of the tuning circuit;

52 is a circuit diagram showing a twelfth modification of the tuning circuit;

Fig. 53 is a circuit diagram showing the configuration of the preceding stage anomaly circuit shown in Fig.

FIG. 54 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in FIG. 53 and the voltage appearing on the capacitor or the like;

Fig. 55 is a circuit diagram showing the configuration of the preceding stage anomaly circuit shown in Fig.

FIG. 56 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in FIG. 55 and the voltage appearing in the capacitor or the like.

57 is a circuit diagram showing another configuration of an ideal circuit including an LR circuit;

Fig. 58 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 57 and the voltage appearing in an inductor or the like. Fig.

59 is a circuit diagram showing another configuration of an ideal circuit including an LR circuit;

Fig. 60 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit shown in Fig. 59 and the voltage appearing in the inductor or the like. Fig.

61 is a circuit diagram showing a fourteenth modification of the tuning circuit;

62 is a circuit diagram showing a fifteenth modification of the tuning circuit;

Fig. 63 is a circuit diagram of a tuning circuit in which variable resistors in the abnormal circuit shown in Fig. 3 are formed by MOS type FETs; Fig.

64 is a circuit diagram showing an example in which elements other than FETs are used as variable resistors in the abnormal circuit;

Fig. 65 is a circuit diagram showing a portion necessary for operation of the abnormal circuit during the construction of the operational amplifier. Fig.

DISCLOSURE OF INVENTION

SUMMARY OF THE INVENTION The present invention is designed to solve such a problem, and its object is to provide a new tuning control method suitable for integration.

The tuning control method of the present invention is a tuning control method in which two or more crossover-connected all-pass circuits of the crossover type and an output of the abnormal circuit at the rear end are fed back to the input side of the abnormal circuit at the previous stage, A tuning circuit for passing only a signal in the vicinity of a predetermined frequency,

Wherein the tuning circuit has a frequency that matches the tuning frequency of the tuning circuit with the frequency of the input signal of the tuning circuit based on the phase difference between the input and output signals of the tuning circuit when a signal having a frequency near the predetermined frequency is input to the tuning circuit And a control circuit.

By performing control so that the phase difference between the input and output signals of the tuning circuit is eliminated, it is possible to make the tuning frequency always follow the frequency of the input signal.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, one embodiment of the tuning control method of the present invention will be described in detail with reference to the drawings.

[A. Overall Configuration and Operation of Tuning Mechanism]

The tuning control method of the present invention is characterized in that when the sine wave signal of a certain frequency is inputted to the tuning circuit, the phase difference between the input and output of the tuning circuit is detected to make the tuning frequency coincide with the frequency of the input signal .

1 is a diagram showing a configuration of a tuning mechanism according to an embodiment to which the tuning control method of the present invention is applied.

The tuning mechanism shown in the figure includes a tuning circuit 1 functioning as a filter for passing a signal in the vicinity of a certain frequency and a frequency control circuit 2 for controlling the passing center frequency of the tuning circuit 1.

The circuit 1 includes two or more circuits as described later. The circuit 1 takes out the output of the abnormal circuit at the subsequent stage as the output of the reference circuit 1, feeds back the signal through the feedback resistor, The input signal inputted through the feedback resistor and the feedback signal fed back through the feedback resistor are added to the previous abnormal circuit. With the above arrangement, the phase shift amount of two or more circuits is set to 360 degrees at a predetermined frequency.

In addition, the tuning frequency 1 can be arbitrarily set to a certain range by a control signal input from the outside. The detailed configuration and detailed operation of the inquiry road 1 will be described later.

In the frequency control circuit 2, the input signal and the output signal of the inquiry circuit 1 are input. When the phase difference between these input and output signals deviates from 360 degrees, that is, The tuning frequency of 1 of the tuning circuit is controlled so that this deviation does not occur when the frequency is deviated.

In order to perform such control, the frequency control circuit 2 includes a synchronous rectification circuit 3 and a control signal generation circuit 4.

The synchronous rectification circuit 3 uses the output signal of the inquiry circuit 1 as a reference signal to synchronously rectify the input signal of the inquiry circuit 1. [ The synchronously rectified output is input to the control signal generation circuit 4 at the subsequent stage. Considering the case where a signal of a single frequency is input to the synchronous rectification circuit 1, for example, the above-mentioned synchronous rectification circuit 3 has a configuration in which the frequency of the input signal to the inversion circuit 1 coincides with that of the tuning frequency, A full half wave rectified waveform voltage is output at 360 degrees, and a voltage corresponding to this deviation is outputted when it deviates at 360 degrees.

The control signal generating circuit 4 includes a pulse converting circuit 5, a polarity discriminating circuit 6, and a voltage synthesizing circuit 7. The control signal generating circuit 4 detects the phase error between input / output signals of the above- And generates a control signal for eliminating the error.

The pulse conversion circuit 5 outputs a pulse train having a pulse width corresponding to the time interval at which the voltage component corresponding to the shift outputted from the synchronous rectification circuit 3 appears. The polarity discrimination circuit 6 discriminates the polarity of the phase error by determining whether the voltage component corresponding to the shift outputted from the synchronous rectification circuit 3 appears before or after the half-wave rectification waveform. The polarity of this error indicates whether the tuning frequency is low or high, corresponding to the frequency of the input signal (precisely corresponding to the frequency of the signal extracted from the input signal by passing through the tuning circuit 1).

The voltage synthesizing circuit 7 generates a voltage corresponding to the pulse width of the signal outputted from the pulse converting circuit 5 and adds or subtracts the generated voltage in accordance with the polarity of the phase error discriminated by the polarity discriminating circuit 6 Synthesizes the voltage, and outputs the synthesized voltage toward the tuning circuit 1 as a control signal.

The detailed configuration and operation of the synchronous rectification circuit 3 and the control signal generation circuit 4 constituting the above-described frequency control circuit 2 will be described later.

[B. Detailed Configuration and Operation of Tuning Circuit]

Next, the details of the inquiry route 1 shown in Fig. 1 will be described. Fig. 2 is a circuit diagram showing the detailed configuration of the inquiry path 1. Fig. The reference numeral 1 shown in the figure shows two abnormal circuits 110C and 130C for performing a total 360. phase shift at a predetermined frequency by shifting the phase of an AC signal inputted thereto by a predetermined amount, The voltage dividing circuit 160, the feedback resistor 170, and the input resistor 174 (the input resistor 174 is assumed to have a resistance value n times as large as the resistance value of the feedback resistor 170) from the resistors 162 and 164 provided on the output sides of the voltage dividing circuits 160 (Input signal) input to the input terminal 190 at a predetermined ratio, as shown in Fig.

Fig. 3 is a diagram showing the configuration of the preceding stage anomaly circuit 110C shown in Fig. The anomaly circuit 110C of the former stage shown in the same figure includes an operational amplifier 112 which is a kind of differential amplifier, a variable resistor 116 which shifts the phase of the AC signal input to the input stage 122 by a predetermined amount and inputs the shifted signal to the non-inverting input terminal of the operational amplifier 112 A capacitor 114, a resistor 118 inserted between the input terminal 122 and the inverting input terminal of the operational amplifier 112, resistors 121 and 123 connected to the output terminal of the operational amplifier 112 and constituting a voltage dividing circuit, And a resistor 120 connected between the inverting input terminal of the operational amplifier 112 and the inverting input terminal of the operational amplifier 112.

In the ideal circuit 110C having such a configuration, the resistance values of the resistors 118 and 120 are set to be the same. 3, for example, the variable resistor 116 uses the channel of the FET as a resistor and is connected to the variable resistor 116 from the outside through a control terminal 194 shown in Fig. 2, as shown in Fig. 3, for example. And the resistance value is set by applying the supplied control voltage to the gate.

When a predetermined AC signal is input to the input terminal 122 shown in Fig. 3, a voltage VR1 appearing at both ends of the variable resistor 116 is applied to the non-inverting input terminal of the operational amplifier 112. [ At both ends of the resistor 118, a voltage VC1 equal to the voltage VC1 appearing at both ends of the capacitor 114 appears. The same current I flows through the two resistors 118 and 120. Further, since the resistance values of the resistors 118 and 120 are the same as described above, the voltage VC1 appears on both ends of the resistor 120 as well. When the inverting input terminal (voltage VR1) of the operational amplifier 112 is taken as a reference, the result of vectorially adding the both-end voltage VC1 of the resistor 118 is obtained by vector-subtracting the both-end voltage VC1 of the resistor 120 from the input voltage Ei (Partial voltage output) Eo 'at the connection point between the resistor 121 and the resistor 123. [

Fig. 4 is a vector diagram showing the relationship between the input / output voltage and the voltage appearing in the capacitor or the like in the preceding stage anomaly circuit 110C.

As described above, when the voltage VR1 applied to the non-inverting input terminal of the operational amplifier 112 is taken as a reference, the input voltage Ei and the divided voltage Eo 'are different only in the direction in which the voltage VC1 is synthesized, and their absolute values are the same . Therefore, the relationship between the magnitude of the input voltage Ei and the partial pressure output Eo 'and this phase can be expressed by an isosceles triangle having the input voltage Ei and the divided voltage output Eo' as the oblique side and having twice the voltage VC1 as the bottom, It can be seen that the amplitude of Eo 'is equal to the amplitude of the input signal regardless of the frequency, and the amount of phase shift is indicated by? 1 shown in FIG. The phase shift amount? 1 changes from 180 to 360. in the clockwise direction (retarded phase) with respect to the input voltage Ei according to the frequency.

Since the output terminal 124 of the error circuit 110C is connected to the output terminal of the operational amplifier 112, if the resistance value of the resistor 121 is R21 and the resistance value of the resistor 123 is R23, then the resistance between the output voltage Eo and the above- When R21 and R23 are sufficiently small with respect to the resistance value of 120, Eo = (1 + R21 / R23) Eo '. Therefore, by adjusting the values of R21 and R23, a gain greater than 1 can be obtained. As shown in Fig. 4, even when the frequency changes, the amplitude of the output voltage Eo is constant and only the phase can be shifted by a predetermined amount.

Similarly, FIG. 5 shows the configuration of the abnormal circuit 130C at the rear end shown in FIG. The abnormal circuit 130C in the subsequent stage shown in the diagram includes an operational amplifier 132, which is a kind of differential amplifier, a capacitor 134, which shifts the phase of a signal input to the input terminal 142 by a predetermined amount and inputs the shifted signal to the noninverting input terminal of the operational amplifier 132, Resistors 141 and 143 constituting a voltage dividing circuit connected to the resistor 138 inserted between the input terminal 142 and the inverting input terminal of the operational amplifier 132 and the output terminal of the operational amplifier 132, And a resistor 140 connected between the inverting input terminal of the operational amplifier 132 and the inverting input terminal of the operational amplifier 132.

In the ideal circuit 130C having such a configuration, the resistance values of the resistors 138 and 140 are set to be the same.

When a predetermined AC signal is input to the input terminal 142 shown in FIG. 5, a voltage VC2 appearing at both ends of the capacitor 134 is applied to the non-inverting input terminal of the operational amplifier 132. At both ends of the resistor 138, a voltage VR2 equal to the voltage VR2 appearing at both ends of the variable resistor 136 appears. Since the same current I flows through the two resistors 138 and 140, and the resistance values of the resistors 138 and 140 are the same as described above, the voltage VR2 appears on both ends of the resistor 140 as well. Considering the inverted input terminal (voltage VC2) of the operational amplifier 132 as a reference, it is obtained by vectorially adding the both-end voltage VR2 of the resistor 138 to the input voltage Ei and subtracting the both-end voltage VR2 of the resistor 140 from the vector (Partial voltage output) Eo 'at the connection point of the resistor 41 and the resistor 43. [

6 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit 130C at the subsequent stage and the voltage appearing on the capacitor or the like.

Considering the voltage VC2 applied to the noninverting input terminal of the operational amplifier 132 as described above, the input voltage Ei and the divided voltage output Eo 'are different from each other only in the direction in which the voltage VR2 is synthesized, and their absolute values are the same. Therefore, the relationship between the magnitude and phase of the input voltage Ei and the divided voltage output Eo 'can be expressed by an isosceles triangle having the input voltage Ei and the divided voltage output Eo' as oblique and the voltage VR2 as the base, Is equal to the amplitude of the input signal regardless of the frequency, and the amount of phase shift is represented by? 2 shown in FIG. This phase shift amount? 2 changes from 0 to 180 in the clockwise direction on the basis of the input voltage Ei according to the frequency.

Since the output terminal 144 of the abnormal circuit 130C is connected to the output terminal of the operational amplifier 132, the resistance value of the resistor 141 is R41, and the resistance value of the resistor 143 is R43. Eo = (1 + R41 / R43) Eo 'when R41 and R43 are sufficiently small with respect to the resistance value of the resistor R0. Therefore, by adjusting the values of R41 and R43, a gain greater than 1 can be obtained. Further, as shown in Fig. 6, even when the frequency changes, the amplitude of the output voltage Eo is constant and only the phase can be shifted by a predetermined amount.

In this way, the phases are shifted by a predetermined amount in each of the two abnormal circuits 110C and 130C, and the amount of phase shift in the whole of the circuit 1 as shown in Figs. 4 and 6 is 360 degrees at a predetermined frequency. .

2, the output of the abnormal circuit 130C at the subsequent stage is taken out from the output terminal 192 as an output of the inquiry circuit 1, and the output of the abnormal circuit 130C through the voltage dividing circuit 160 is fed back to the feedback resistor 170 to the input side of the abnormal circuit 110C at the previous stage. Then, the feedback signal is added to the signal input through the input resistor 174, and the added signal is input to the previous stage error circuit 110C.

As described above, the sum of the amounts of phase shift at a predetermined frequency is 360. The two abnormal circuits 110C and 130C cause the sum of the phase shift amounts at the predetermined frequency to be 360. At this time, the two abnormal circuits 110C and 130C, the voltage divider circuit 160, By setting the loop gain to 1 or less, a tuning operation for passing only the signal of the predetermined frequency component is performed.

Since the output of the abnormal circuit 130C before being input to the voltage dividing circuit 160 is extracted from the output terminal 192 of the inquiry circuit 1, the gain of the circuit 1 itself can be made gain, and the amplification of the signal amplification .

Fig. 7 is a circuit diagram in which the two abnormal circuits 110C and 130C and the voltage divider circuit 160 having the above-described configuration are entirely replaced with a circuit having a transfer function K1, and a feedback resistor 170 Is connected in series with an input resistor 174 having a resistance value nR0 of n times the feedback resistance 170. [

FIG. 8 is a circuit diagram of the circuit shown in FIG. 7 converted by Miller's theorem, and the transfer function A of the entire system after conversion is

As shown in FIG.

The time constant of the CR circuit T ₁ is as above circuit transfer function K2 of 110C of the front end, the variable resistor 116 and a capacitor 114 (when the resistance value of the variable resistance 116 R, a previous capacity of the capacitor 114 to the C T ₁ = CR) Quot;

. Here, s = jω, a ₁ is the gain of the error circuit 110C, and a ₁ = (1 + R21 / R23)> 1.

When the time constant of the CR circuit including the capacitor 134 and the resistor 136 is T ₂ (the capacitance of the capacitor 134 is C, and the resistance of the resistor 136 is R, T ₂ = CR), the transfer function K 3 of the rear- In other words,

. Here, a ₂ is the gain of the ideal circuit 130C and a ₂ = (1 + R41 / R43)> 1.

Assuming that the signal amplitude is attenuated to 1 / a ₁ a ₂ by passing through the voltage dividing circuit 160, the transfer function K 1 as a whole when the two abnormal circuits 110 C and 130 C and the voltage dividing circuit 160 are cascade-

. In order to simplify the calculation, the time constants T ₁ and T ₂ of the respective anomalous circuits are set to T in the above-described equation (4). Substituting Equation 4 into Equation 1 described above,

.

According to equation (5), A = -1 / (2n + 1) at the time when? = 0 (in the region of direct current), and the maximum attenuation is given. And, even when ω = ∞, A = -1 / (2n + 1), which gives the maximum attenuation. At the tuning point of ω = 1 / T, A = 1, which is irrelevant to the resistance ratio of the feedback resistor 170 and the input resistor 174. In other words, even if the value of n is changed as shown in Fig. 9, the tuning point is not shifted and the attenuation amount of the tuning point does not change.

In addition, by varying the resistance values of the variable resistor 116 included in the error circuit 110C at the previous stage and the variable resistor 136 included in the error circuit 130C at the subsequent stage, the time constant of each CR circuit included in the error circuits 110C and 130C can be changed, The frequency? Can be arbitrarily changed within a certain range.

7, when the global pass circuit represented by the transfer function K1 has the input impedance, the voltage divider circuit is formed by the feedback resistor 170 and the input impedance of the global pass circuit. Therefore, the feedback circuit including the global pass circuit The loop gain of the loop becomes smaller than the absolute value of the transfer function K1. The input impedance of the all-pass circuit is the input impedance of the preceding stage anomaly circuit 110C and the input impedance formed by connecting the series impedance of the CR circuit constituted by the variable resistor 116 and the capacitor 114 to the input resistor 118 of the operational amplifier 112 in parallel . Therefore, in order to compensate for the loss of the loop gain of the feedback loop due to the impedance of the global pass circuit, it is necessary to set the gain of the global pass circuit itself to 1 or more.

For example, over the circuit Ignoring the resistor 121, voltage dividing circuit by 123 included in the 110C and I (partial pressure in the case of a ratio of 1, considering a case in which a ₁ in the above-described formula (2) 1) above, The circuit 110C must operate within the range of the inverting amplifier whose gain is -1 times the gain from the 1-fold flow circuit according to the input frequency, so that the resistance ratio of the resistors 118 and 120 is set to be other than 1 Is not desirable. If the resistance values of the silver resistors 118 and 120 are R18 and R20, then the gain when the abnormal circuit 110C operates as an inverting amplifier is -R20 / R18, and the gain when operating as a flow circuit is the resistance of the resistors 118 and 120 Even if the resistance ratio of the resistor 118 and the resistor 120 is not 1, the phase of the input / output changes in the entire region where the error circuit 110C operates, and the abnormal condition in which the output amplitude does not change is satisfied It can not be done.

A voltage dividing circuit consisting of a resistor 121 and a resistor 123 is added to the output side of the ideal circuit 110C and the feedback is made to the inverting input terminal of the operational amplifier 112 through this voltage dividing circuit so that the resistance ratio between the resistor 118 and the resistor 120 is maintained at 1 The gain of the ideal circuit 110C can be set to 1 or more. Likewise, a voltage dividing circuit consisting of a resistor 141 and a resistor 143 is added to the output side of the ideal circuit 130C, and the inverting input terminal of the operational amplifier 132 is returned through the voltage dividing circuit to maintain the resistance ratio of the resistor 138 and the resistor 140 at 1 It is possible to set the gain of the excess circuit 130C to 1 or more.

(In the clockwise direction (phase slow direction) with respect to the input voltage Ei as shown in Fig. 4 and Fig. 6 in Eq. 2 or Eq. 3 and 180? 0. < / = 2 < / = 180 in the clockwise direction)

.

For example, when T ₁ = T ₂ (= T), the sum of the amounts of phase shift due to two abnormal circuits 110C and 130C is 360. When? = 1 / T, the above-described tuning operation is performed Φ1 = 270, and Φ2 = 90.

10 is a diagram showing the phase relation between signals input to and output from the two abnormal circuits 110C and 130C, and shows a case where the frequency of the signal input to the abnormal circuit 110C at the preceding stage is the same as the tuned frequency.

As shown in Fig. 10 (A), the phase of the output signal S2 of the previous-stage anomaly circuit 110C is shifted in the clockwise direction by? 1 = 270 with reference to the input signal S1. The phase of the output signal S3 of the posteriori error circuit 130C is shifted in the clockwise direction by? 2 = 90 ° based on the input signal S2.

Therefore, when the two abnormal circuits 110C and 130C are cascaded, the 360 phase is shifted as a whole as shown in Fig. 10 (C).

However, when the tuning frequency set higher than the frequency of the signal input to the anterior stage circuit 110C at the previous stage is higher, the result obtained by combining? 1 and? 2 does not become 360. However,

11 is a diagram showing the phase relationship between input / output signals of the respective anomalous circuits when the tuning frequency is higher than the frequency of the signal inputted to the preceding-stage fault circuit 110C. In FIG. 11 and FIG. 12 described later, as in the case of FIG. 10 described above, it is shown that the time constants T _{1 and} T ₂ of the respective anomalous circuits are the same as one example.

In the case where the frequency of the input signal is relatively lower than the frequency of the signal input to the anterior error circuit 110C, the frequency of the input signal is relatively lower than the tuning frequency. In this case, as apparent from Figs. 4 and 6, The phase shift amount PHI 1 becomes smaller than 270 DEG, and the phase shift amount PHI 2 of the subsequent error circuit 130C becomes smaller than 90 DEG. 11A and 11B, and the sum of the amount of phase shift when the two abnormal circuits 110C and 130C are cascade-connected is expressed as shown in Fig. 11 (C) Likewise, it becomes smaller than 360.

However, in such a case, in order to make the tuning frequency close to the frequency of the actually input signal, it is necessary to increase the above-mentioned? 1, specifically, the both-end voltage VR1 of the variable resistor 116 shown in FIG. For example, when the variable resistor 116 is formed of an n-channel type FET, the gate voltage may be lowered to increase the channel resistance.

On the other hand, even when the tuning frequency is lower than the frequency of the signal input to the previous stage of the anomalous circuit 110C, the sum of the above-described? 1 and? 2 does not reach 360. However,

12 is a diagram showing the phase relationship between the input / output signals of the respective anomalous circuits in the case where the tuned frequency is lower than the signal frequency inputted to the preceding-stage anomaly circuit 110C.

The case where the frequency of the tuning frequency is lower than the frequency of the signal input to the previous stage of the error circuit 110C means that the frequency of the input signal is relatively higher than the tuning frequency. In this case, as apparent from Figs. 4 and 6, The phase shift amount PHI 1 of the circuit 110C is larger than 270 DEG and the phase shift amount PHI 2 of the subsequent stage abnormal circuit 130C becomes larger than 90 DEG. 12A and 12B, and the sum of the amount of phase shift when the two abnormal circuits 110C and 130C are cascade-connected is expressed as shown in Fig. 12C 360.

In this case, in order to bring the tuning frequency close to the frequency of the actually input signal, it is necessary to decrease the absolute value of the above-mentioned? 1. Specifically, the both-end voltage VR1 of the variable resistor 116 shown in FIG. For example, when the variable resistor 116 is formed of an n-channel type FET, the gate voltage may be increased to reduce the channel resistance.

As described above, the resistance values of the resistors 118 and 120 in the abnormal circuit 110C are set to the same value and the resistance values of the resistors 138 and 140 in the abnormal circuit 130C are set to the same value in the above- It is possible to prevent amplitude fluctuation when the tuning frequency is changed and to obtain a tuning output having a substantially constant amplitude.

In particular, by suppressing the amplitude fluctuation of the tuning output, the above-described resistance ratio n can be increased to increase the Q value of the tuning circuit 1. That is, if the loop gain has frequency dependency, the Q gain does not increase even if the resistance ratio n is increased at the low gain, and the loop gain sometimes oscillates at a gain higher than 1 at the high gain. Therefore, when the amplitude fluctuation is large, the resistance ratio n can not be set to a too large value in order to prevent such oscillation, and the Q value of 1 is also reduced.

On the other hand, according to the resonant circuit 1 shown in FIG. 2, even if the resistance ratio n is set to be large in order to connect the voltage divider circuits to the abnormality circuits 110C and 130C, the tuning output of the tuning circuit 1 does not cause amplitude fluctuation. Therefore, the Q value can be increased by increasing the resistance ratio n in the resonance circuit 1 shown in Fig.

Then, a signal attenuated by the voltage dividing circuit 160 is used as a feedback signal, and at the same time, a signal before input to the voltage dividing circuit 160 is subtracted to the output of the tuning circuit 1 so as to extract only a predetermined frequency component from the input signal. A predetermined amplification can be performed on the signal.

2, either one of the voltage dividing circuits connected to the output terminals of the operational amplifier 112 or 132 in each of the abnormal circuits included in the inquiry circuit 1 may be omitted, May be set to one.

For example, the output terminal of the operational amplifier 112 may be directly connected to one end of the resistor 120 by omitting the voltage dividing circuit in the abnormal circuit 110C.

When the gain of the other abnormal circuit 110C is set to be larger than 1 by setting the gain to 1 by omitting the voltage dividing circuit for one of the two or more cascaded cascaded circuits, Is performed.

If the amplifying operation is not necessary, the voltage divider circuit 160 at the rear end of the abnormal circuit 130C may be omitted and the output of the abnormal circuit 130C may be directly fed back to the previous stage. Alternatively, the resistance of the resistor 162 in the voltage dividing circuit 160 may be set to an extremely small value, and the partial pressure ratio may be set to 1.

[C. Detailed Configuration and Operation of Frequency Control Circuit]

Next, the details of the frequency control circuit 2 shown in Fig. 1 will be described. FIG. 13 is a circuit diagram showing the configuration of the frequency control circuit 2 and shows the detailed configurations of the synchronous rectification circuit 3, the pulse conversion circuit 5, the polarity determination circuit 6, and the voltage synthesis circuit 7, respectively.

The synchronous rectification circuit 3 shown in FIG. 13 includes an analog switch 30, a voltage comparator 32, and a level shifter (LS) 34.

The output signal of the comparator 1 is input to one input terminal (for example, the inverting input terminal) of the voltage comparator 32, and the other input terminal (for example, the non-inverting input terminal) is grounded. The output of the voltage comparator 32 becomes L level (for example, 0 V) when the potential of the output signal of the reference signal line 1 is greater than 0 V, and conversely, when the potential of the output signal of the reference signal line 1 is 0 V or less, Level (for example, a predetermined constant voltage). The voltage comparator 32 has an inverting output terminal for outputting a signal whose logic is inverted on the other side of the above-mentioned output terminal, and this inverting output terminal is connected to a polarity discriminating circuit 6 which will be described later.

The level shifter 34 performs polarity inversion for the signal output from the voltage comparator 32, performs level shifting, and outputs a signal having a positive polarity and a negative polarity as a reference signal.

The analog switch 30 operates in synchronization with the reference signal output from the level shifter 34 and passes or blocks the input signal of the analogue signal line 1 inputted in parallel to the reference signal at a predetermined timing. For example, the analog switch 30 passes the input signal when the short waveform of the reference signal is at the positive voltage level and blocks the input signal when the voltage is at the negative voltage level.

Although the level shifter 34 between the voltage comparator 32 and the analog switch 30 is inserted in the synchronous rectification circuit 3 shown in Fig. 13, the level shifter 34 may be omitted and the analog switch 30 may be operated by using the output of the voltage comparator 32 as a direct reference signal good.

In this manner, the synchronous rectification circuit 3 performs synchronous rectification with respect to the input signal of the inquiry circuit 1 in synchronization with the output signal of the inquiry circuit 1. For example, when the frequency of the input signal of 1 and the tuning frequency of the tuning circuit 1 coincide with each other, the half-wave rectification waveform signal of only the positive side of the input signal is outputted as the synchronous rectification output from the synchronous rectification circuit 3 .

The pulse conversion circuit 5 shown in FIG. 13 includes a voltage comparator 50, and a voltage dividing circuit composed of resistors 52 and 54.

The output signal of the analog switch 30 in the synchronous rectification circuit 3 is input to one input terminal (for example, non-inverting input terminal) of the voltage comparator 50, and the divided output of the voltage dividing circuit is input to the other input terminal . Then, the voltage comparator 50 compares the voltages at both input terminals and outputs the comparison result. One end of the resistor 52 constituting the voltage dividing circuit is grounded, and one end of the resistor 54 is connected to the sub power source VSS. The voltage of the inverting input terminal of the voltage comparator 50 is set to a level lower than 0 V by setting the resistance value of the resistor 54 to a value larger than the resistance value of the resistor 52 (for example, 100 times).

The above-described synchronous rectification circuit 3 generates a component of the same polarity and a component of the opposite polarity to the reference signal. The component of this reverse polarity indicates a phase deviation of 1, and the voltage comparator 50 in the pulse conversion circuit 5 outputs a pulse train having a pulse width proportional to this phase deviation. Specifically, the voltage comparator 50 outputs two kinds of pulse strings having mutually different polarities, one of the pulse strings is inputted to the voltage synthesizing circuit 7, and the other pulse string is inputted to the polarity discriminating circuit 6.

As described above, when the frequency of the signal input to the inverse lookup table 1 coincides with the tuned frequency, a complete half-wave rectified waveform can be obtained as the synchronous rectified output, so that the voltage level is always positive or zero volts. However, when the frequency of the input signal and the tuning frequency do not coincide with each other, a voltage component having a negative polarity is generated at the output of the synchronous rectification at a timing corresponding to the phase shift. Therefore, when the tuning frequency deviates from the frequency of the input signal and this negative portion occurs, the output of the voltage comparator 50 in the pulse conversion circuit 5 becomes L level at the same timing as the generation timing of the negative portion.

The polarity determination circuit 6 shown in Fig. 13 includes two inverter circuits 60 and 61 and two D-type flip-flops 62 and 63.

In this embodiment, a delay circuit is constituted by two inverter circuits 60 and 61, and the output of the voltage comparator 50 in the pulse conversion circuit 5 is connected to the flip-flops 62 and 63 through the two inverter circuits 60 and 61, It is input to each clock terminal.

The D input terminal of the D flip-flop 62 in the polarity determination circuit 6 receives a signal having the same level as the reference signal of the synchronous rectification circuit 3 only at the same timing. The signal input to the D input terminal is latched in synchronization with the occurrence of the pulse string output from the pulse conversion circuit 5 and input to the D input terminal of the D flip-flop 63 at the next stage. The D-type flip-flop 63 in the next stage outputs a voltage of H or L level indicating the direction of the phase, based on the pulse string output from the voltage comparator 50 in the pulse conversion circuit 5.

13 includes two tri-state buffers 700 and 702, a differential amplifier, and a variable bias circuit. The differential amplifier includes an operational amplifier 704, and the variable bias circuit includes a variable resistor 706 .

One tristate buffer 700 has its input terminal connected to the inverting output terminal of the voltage comparator 50 in the pulse converting circuit 4 and its output terminal connected to the inverting input terminal of the differential amplifier through the resistor 710. This tristate buffer 700 operates in accordance with the logic of the signal output from the output terminal Q of the flip-flop 63 in the subsequent stage in the polarity determination circuit 6, and when the logic of this signal is H, for example, On the contrary, when the logic of this signal is L, the output terminal is put into the high impedance state.

Likewise, the other tri-state buffer 702 has its input terminal connected to the inverted output terminal of the voltage comparator 50 in the pulse conversion circuit 5, and its output terminal connected to the non-inverted input terminal of the differential amplifier through the resistor 708. This tristate buffer 702 operates in accordance with the logic of the signal output from the inverted output terminal of the flip-flop 63 at the rear end in the polarity determination circuit 6, and when the logic of this signal is H, for example, On the contrary, when the logic of this signal is L, the output terminal is put into the high impedance state.

The differential amplifier inputs the respective outputs of the two tri-start buffers 700 and 702 to the differential input terminals, amplifies the difference by a predetermined amplification degree, performs a predetermined smoothing operation to remove high-frequency components, Voltage is generated.

More specifically, the differential amplifier includes a feedback resistor 712 inserted between the inverting input terminal and the output terminal of the operational amplifier 704, a capacitor 714 connected in parallel to the feedback resistor 712, and an output Inverting input terminal of the operational amplifier 704 and the ground to adjust the two inputs of the operational amplifier 704 by dividing the voltage level of the output signal of the operational amplifier 704, a capacitor 718 and a capacitor 718 connected in parallel to the resistor 716, And a capacitor 720 inserted between the inverting input terminal of the amplifier 704 and the ground.

The inverting input terminal of the operational amplifier 704 is connected to the movable terminal of the variable resistor 706 through which the two fixed terminals are connected to the constant voltage Vdd and the negative voltage Vss via the resistor 722. [ Therefore, a predetermined bias voltage is set at the output terminal of the operational amplifier 704 by the bias circuit formed by the variable resistor 706. [ When the variable resistor 706 is actually formed on a semiconductor substrate, it can be formed using an active element such as a FET.

This bias circuit is applied to the gate of the variable resistor 116 included in the one-side abnormal circuit 110C when the tuning frequency of 1 is coincident with the frequency of the input signal (that is, when there is no error) To set the voltage.

The frequency control circuit 2 of the present embodiment has such a detailed configuration, and the detailed operation will be described as occasion demands.

[C-1. When the tuning frequency is higher than the frequency of the input signal]

14 is a timing chart in the case where the tuning frequency of the tuning circuit 1 is higher than the frequency of the signal inputted to the inquiry furnace 1, and the input / output timings of the respective constituents in the frequency control circuit 2 are displayed. The diagrams (A) to (N) correspond to the symbols A to N shown in the circuit diagram of FIG. Also, the diagonal lines included in the diagrams (I) to (N) correspond to the uncertain portions, and their states are determined corresponding to the states of the input and output waveforms at the timing before the input / output waveforms of the respective constituent elements actually shown in the diagram.

When the tuning frequency is higher than the frequency of the input signal of the inquiry circuit 1, the sum of the amounts of phase shift due to the entire two circuits 110C and 130C becomes smaller than 360 degrees as shown in Fig. 11 (C) Observation of the two input / output signals input / output to the inquiry line 1 at any point results in the phase relationship shown in Figs. 14 (A) and 14 (B).

One of the voltage comparators 32 in the synchronous rectification circuit 3 outputs a signal of H level when the output signal of the inquiry circuit 1 is at a voltage level lower than 0 V and a signal of L level when it is higher than 0 V. Therefore, as shown in Fig. 14 (C), the voltage comparator 32 has the same frequency and phase as the tuning output, and when the voltage level of the tuning output is positive, it is at the L level. Conversely, when the voltage level of the tuning output is negative A square wave of the level is output.

Further, the voltage comparator 32 outputs, in addition to the above-described output, a signal obtained by inverting the logic at the inverted output terminal, and the waveform thereof is shown in Fig. 14 (D).

The level shifter 34 inverts the logic corresponding to the output of the voltage comparator 32 shown in Fig. 14 (C), and outputs a square wave having the positive and negative polarity voltage states whose absolute values are equal to each other Output.

The analog switch 30 performs the ON / OFF operation of the switch corresponding to the voltage level of the square wave output from the level shifter 34. When the tuning frequency of the inquiry circuit 1 is higher than the frequency of the input signal, as shown in Fig. 14 (F), a waveform slightly shifted forward from the half-wave rectification waveform, that is, the upper half of the tuning output is extracted The analog switch 30 outputs the waveform taken out at a fast timing.

The voltage comparator 50 outputs the pulse train of the H level only when the voltage level of the output of the analog switch 30 becomes lower than 0 V and the other pulse train of the H level. Therefore, when the synchronous rectified output outputted from the analog switch 30 is slightly shifted forward from the half-wave rectified waveform, as shown in Fig. 14 (G), the output of the voltage comparator 50 is at the L level .

The voltage comparator 50 outputs, in addition to the above-described output, a signal obtained by inverting the logic from the inverted output terminal, and the waveform thereof is shown in Fig. 14 (H).

The flip flop 62 at the preceding stage in the polarity discrimination circuit 6 is turned on at the timing when the output of the voltage comparator 50 rises from the L level to the H level (accurately, the output of the voltage comparator 50 is shifted ) And holds the logic of the signal output from the inverted output terminal of the voltage comparator 32 in the synchronous rectification circuit 3 and holds it. As shown in Figs. 14 (G) and 14 (D), when the signal output from the voltage comparator 50 rises, the signal output from the inverted output terminal of the voltage comparator 32 becomes H level, This logic H is held by the flip-flop 62 of the previous stage as shown in Fig.

The output of the flip-flop 62 at the subsequent stage is taken in and held at the timing when the output of the voltage comparator 50 goes up from the L level to the H level at the next stage, and the output terminal Q And outputs a signal of logic H at the time t. Further, at the inverted output terminal of the flip-flop 63, as shown in Fig. 14 (K), a signal of logic L inversion of this logic H is outputted.

Thus, when the tuning frequency is higher than the frequency of the input signal of the inquiry circuit 1, a signal of logic H is output from the output terminal Q of the flip-flop 63 at the subsequent stage, and a signal of logic L is outputted from the inverted output terminal. Therefore, in the operation of the two tri-state buffers 700 and 702 in the voltage synthesizing circuit 7, the output terminal of the tri-state buffer 702 to which the signal of logic L is inputted to the control terminal is put into the high impedance state, Only the input tri-state buffer 700 operates as a buffer as shown in Fig. 14 (L).

In addition, since the output terminal of the tri-state buffer 702 is grounded through the resistors 708 and 716, the potential of this output terminal becomes 0 V shown in FIG. 14 (M).

Incidentally, in the tri-state buffer 700, the inverting output terminal of the voltage comparator 50 is connected to the input terminal, and the inverting input terminal of the operational amplifier 704 is connected to the output terminal through the resistor 710. Therefore, when the logic H signal is input to the control terminal and the tri-state buffer 700 functions as a simple buffer, the signal output from the inverting output terminal of the voltage comparator 50 is input to the inverting input terminal of the operational amplifier 704 through the resistor 710.

When the pulse of positive polarity is inputted to the inverting input terminal of the operational amplifier 704 in this way, the voltage of the output terminal of the operational amplifier 704 is decreased corresponding to the pulse input.

However, in reality, the capacitor 720 is connected between the inverting input terminal of the operational amplifier 704 and the ground, and the capacitor 714 is connected between the output terminal of the operational amplifier 704 and the inverting input terminal, and the output voltage is smooth. 14 (N), the differential amplifier including the operational amplifier 704 gently drops the output voltage, that is, the control voltage, corresponding to the pulse width of the signal inputted through the tri-state buffer 700.

In this way, the control voltage fed back to the inquiry line 1 is lowered and the tuning frequency of the tuning circuit 1 is changed to the lower side. This control is repeated until the frequency of the input signal of the inquiry circuit 1 and the tuning frequency are eliminated, and the tuning frequency coincides with the frequency of the input signal after a predetermined time elapses.

[C-2. When the tuned frequency is lower than the frequency of the input signal]

15 is a timing chart when the tuning frequency of the tuning circuit 1 is lower than the frequency of the signal inputted to the inquiry furnace 1, and the input / output timings of the respective constituents in the frequency control circuit 2 are displayed. Similar to Fig. 14, Figs. 15A to 15N correspond to the symbols A to N shown in the circuit diagram of Fig.

When the tuning frequency is lower than the frequency of the input signal of the inquiry circuit 1, the sum of the amounts of phase shift due to the entire two circuits 110C and 130C becomes larger than 360 degrees as shown in Fig. 12 (C) Observation of the two input / output signals input and output to the inquiry line 1 at any point results in the phase relationship shown in Figs. 15 (A) and 15 (B).

The voltage comparator 32 in the synchronous rectification circuit 3 outputs a signal (Fig. 15 (C)) synchronized with the tuning output of the tuning circuit 1 and the level shifter 34 inverts and amplifies this signal to perform a predetermined level shift. (Fig. 15 (E)). The analog switch 30 passes the input signal of the tuning circuit 1 only when the voltage level of the output signal of the level shifter 34 is positive, and thus the output waveform shown in Fig. 15 (F) is obtained.

Therefore, in the voltage comparator 50 in the pulse conversion circuit 5, a pulse string having a predetermined constant voltage is output to 0 V at the timing at which the voltage level becomes negative in the output waveform shown in Fig. 15 (F), and at the other timing. (Fig. 15 (G))

However, the flip flop 62 in the polarity discrimination circuit 6 takes in and holds the signal (Fig. 15 (D)) output from the inverted output terminal of the voltage comparator 32 in the synchronous rectification circuit 3 in synchronization with the occurrence of this pulse string, The rise timing of the square wave is substantially equal to the rise timing of the output of the voltage comparator 32 shown in Fig. 15 (D), and there is a possibility that the data will be blown before the input data of the flip-flop 62 is fixed. The inverter circuits 60 and 61 are delay circuits inserted to avoid such an inconsistency, and delay the data fetch timing by a predetermined time to prevent data from being taken in before the input data is determined.

In the configuration shown in Fig. 13, the two inverter circuits 60 and 61 are used to constitute the delay circuit. However, in the case where four or more inverter circuits and a plurality of buffers whose logic is not inverted are used, There are many ways to think about it.

In this way, each of the two flip-flops 62 and 63 in the polarity determination circuit 6 receives the 0V portion (corresponding to the logic L) of the signal output from the inverted output terminal of the voltage comparator 32 in the synchronous rectification circuit 3, 15 (J) and (K), the signals of logic L and logic H are output at the output terminal Q and the inverted output terminal of the flip-flop 63 at the subsequent stage, respectively.

14, the output signal of the flip-flop 63 has a logic state opposite to that of the case where the tuning frequency is higher than the frequency of the input signal, and only the tri-state buffer 702 in the voltage synthesizing circuit 7 is in the buffer . (Fig. 15 (L), (M)). Therefore, a pulse of positive polarity having a predetermined pulse width is input to the non-inverting input terminal of the differential amplifier constituted by the operational amplifier 704, and the control voltage output from the differential amplifier to the inverting amplifier 1 gently rises (Fig. 15 (N)), the tuning frequency of the tuning circuit 1 is changed to the higher side. Such control is repeated until there is no deviation between the frequency of the input signal of 1 and the tuning frequency, and the tuning frequency coincides with the frequency of the input signal after a predetermined time elapses.

Thus, according to the tuning mechanism of the present embodiment, by performing control so that the phase difference between the input and output signals of the tuning circuit 1 is eliminated, the tuning frequency always follows and coincides with the frequency of the input signal. Therefore, for example, when the receiver is used in a superheterodyne type receiver, the tuning frequency can be easily matched to the carrier frequency of the input broadcast wave or the like.

The tuning circuit 1 and the frequency control circuit 2 for implementing the tuning mechanism of the present embodiment are constituted by various digital circuits such as a flip-flop, an operational amplifier, a capacitor and a resistor. It is possible to integrate the entire tuning mechanism or the whole including the tuning mechanism and its peripheral circuits on the semiconductor substrate.

In particular, when the entire tuning mechanism is integrated, it is considered that the frequency characteristic is not constant due to a large disturbance in the circuit constant for each manufactured chip. Even in such a case, according to the tuning mechanism of this embodiment, Since the tuning frequency of the tuning circuit 1 changes so as to follow the input signal, the disturbance of the tuning characteristic does not affect the actual tuning characteristic, and the stable characteristic can always be realized.

When the entire tuning mechanism is integrated, it is conceivable that various element constants such as resistance change depending on the temperature change at the time of use. In the tuning control system of the present embodiment, however, control So that appropriate feedback is applied even when various element constants are changed, and fluctuation of the tuning frequency can be suppressed.

The tuning mechanism according to the present embodiment performs synchronous rectification with respect to the input signal by using the output signal (tuning output) of the tuning circuit 1 as a reference signal by the synchronous rectification circuit 3, and based on this synchronous rectification signal, A signal having a pulse width corresponding to the phase difference is generated and once converted into a pulse to be processed, it is possible to perform stable tuning control which is not affected by variations in the amplitude of the input signal and is hardly influenced by external factors.

In addition, by configuring the polarity determination circuit 6 to include two flip-flops 62 and 63, for example, when the tuning frequency is almost equal to the frequency of the input signal, the pulse shown in Fig. 14 (G) The voltage addition by the voltage synthesizing circuit 7 can be accurately performed even in the case of mutual output. That is, the flip-flop 62 of the preceding stage latches the inverted output of the voltage comparator 32 shown in Fig. 14 (D) or Fig. 15 (D) in synchronization with the rise of the signal shown in Fig. 14 , And the latched data is reflected in the control voltage at the timing when the pulse shown in Fig. 14 (G) or Fig. 15 (G) is output next.

Therefore, when the pulses shown in Figs. 14 (G) and 15 (G) are mutually output, the voltage corresponding to the other pulse is reflected to the control voltage when one pulse is output, Is not accurately reflected in the control voltage. However, when two (or more) even-numbered flip-flops 62 and 63 are cascade-connected, there is no such inconsistency that the reflection to the control voltage is delayed by one cycle.

[D. AM receiver]

Next, the case where the tuning mechanism of this embodiment is applied to an AM receiver will be described. Since the frequency control circuit 2 of the present embodiment includes the synchronous rectification circuit 3, the synchronous rectified output can be used as an AM detection signal when passing through a low-pass filter.

16 is a view showing a configuration of a tuning mechanism that also serves as AM detection. The configuration shown in the figure divides the output of the synchronous rectification circuit 3 in the frequency control circuit 2 shown in Fig. 1 and extracts this branched signal as an AM detection signal through a low-pass filter (LPF) 8 .

In general, the operation of switching the input signal in synchronization with a certain reference signal can be said to be equivalent to mixing the reference signal and the input signal. Now, let us consider first and second signals whose mutual frequencies approach each other as an input signal, and the frequency of the first signal is f1 and the frequency of the second signal is f2 (= f1 + DELTA f) fh. Alternatively, the frequency of the reference signal is fr.

When the synchronous rectification of the input signal is performed using such a reference signal, it corresponds to multiplying each signal that can be represented by the trigonometric function. As a result, the sum of the frequency fr of the reference signal and the frequency fr of the reference signal, . Thus, by multiplying the first signal in the input signal by the reference signal, the respective frequency components of f1 + fr and f1-fr appear and by multiplying the second signal in the input signal by the reference signal, f1 + DELTA f + fr and f1 + DELTA the frequency components of f-fr appear.

When the frequency fr of the reference signal is made to coincide with the frequency f1 of the first signal, the frequency components of 2f1 and 0 appear by multiplying the first signal by the reference signal. By multiplying the second signal by the reference signal, 2f + the frequency component of f appears. Therefore, the frequency components of 2f +? F, 2f1,? F, and 0 appear as the synchronous rectified output. Since the component of the frequency "0" is a direct current component and actually the direct current component includes the modulating signal, the direct current component and the other alternating current components (2f + Δf, 2f1, Δf) The detection using synchronous rectification and the tuning separation can be performed at the same time.

In the case of domestic AM broadcasting, since the above-mentioned? Fsms is 9 kHz, it is possible to extract only a desired broadcast wave having the same frequency as the reference signal by using the low-pass filter 8 capable of removing the frequency component of 9 kHz or more.

17 is a circuit diagram showing the detailed configuration of the frequency control circuit 2 shown in Fig. The detailed configuration of each of the synchronous rectification circuit 3, the pulse conversion circuit 5, the polarity determination circuit 6, and the voltage synthesis circuit 7 constituting the frequency control circuit 2 is the same as the detailed configuration of each circuit shown in Fig. 13, The output of the analog switch 30 included in the pulse comparator circuit 5 is input to the voltage comparator 50 in the pulse conversion circuit 5 and taken out to the outside.

As described above, since the signal output from the low-pass filter 8 provided at the rear end of the synchronous rectification circuit 3 in the frequency control circuit 2 is the AM detection signal, when the tuning mechanism of this embodiment is applied to an AM receiver, The AM detection circuit provided separately at the rear end of the tuning mechanism becomes unnecessary, and the tuning mechanism can be simplified.

As described above using the detailed configuration shown in Fig. 2, the synchronous signal processor 1 used in the present embodiment has theoretically no attenuation of the signal amplitude, and even when the tuning frequency changes, Can be obtained. However, when actually assembling the tuning circuit 1 or simulating the tuning circuit 1, the output amplitude slightly changes due to the change of the tuning frequency, or the type of the FET constituting the variable resistor 116, There is. However, as shown in Fig. 16 and Fig. 17, synchronous rectification is performed on the input signal of the inquiry circuit 1, so that there is no influence of amplitude fluctuation and deformation, It is possible to extract a good AM detection signal.

Further, since the synchronous rectification output is used for AM detection, it is possible to eliminate the dead band region equal to or less than the forward voltage as in the case of performing AM detection using a diode, for example, and it is possible to achieve good AM reception with good linearity . In particular, when integrating the entire tuning mechanism including the AM detection circuit on a semiconductor substrate, a germanium diode having a low forward voltage is not used, and a silicon diode or the like having a high forward voltage is used, so a diode- Needs to be. The method of using the above-described synchronous rectification output together with the AM detection signal has many advantages.

16 and 17 are required for the control by the frequency control circuit 2, and the synchronous rectified output is branched and used for the AM detection signal. Naturally, as in the case of the conventional receiver, The AM detection signal may be obtained by connecting an AM detection circuit using synchronous rectification or by connecting an AM detection circuit using another detection method to the rear end of the reference circuit 1. [

18 is a diagram showing a configuration of an AM receiver using the tuning mechanism shown in Fig.

The AM receiver shown in Fig. 18 includes the tuning circuit 1, the frequency control circuit 2 and the low-pass filter 8, the high-frequency amplifying circuit 10, the low-frequency amplifying circuit 12, the speaker 14 and the antenna 16 shown in Figs. 16 and 17 Consists of.

The high-frequency amplifying circuit 10 high-frequency amplifies the am wave received by the antenna 16 and inputs the amplified wave to the inquiry circuit 1. As described above, the tuning frequency is controlled by the frequency control circuit 2 in the tuning circuit 1, and the tuning frequency coincides with the frequency of the input AM wave.

Since the frequency control circuit 2 detects the phase difference of the input / output signal of the inquiry channel 1 as an error signal and controls the phase difference to be eliminated, the variable resistor 706 constituting the bias circuit in the voltage synthesizing circuit 7 is adjusted in advance It is necessary to set the tuning frequency of the tuning circuit 1 so as to be near the frequency of the AM wave to be received.

The low-frequency amplifying circuit 12 performs low-frequency amplification on the signal (AM detection signal) output from the low-pass filter 8, and outputs a voice from the speaker 14. Alternatively, the sound may be converted into an audio signal by an earphone or the like without using the speaker 14.

The AM receiver shown in Fig. 18 extracts the AM wave of the desired frequency directly from the antenna 1 without using the LC circuit by the bar-code and the bar antenna at the input portion of the antenna 16, . Therefore, the antenna 16 can be formed of a short rod-shaped or tie-shaped conductive material, and the AM wave can be efficiently received. Specifically, the antenna is formed by a rod antenna used in a car radio or the like, or by using the lead portion of the earphone as the antenna 16, a desired AM wave can be received sensitively, It is possible.

Further, in order to solve the problem without using the bar antenna, almost all the constituent circuits of the AM receiver including the tuning circuit 1, the frequency control circuit 2, the high-frequency amplifying circuit 10 and the like can be integrated on the semiconductor substrate, It can also be formed on one chip.

[E. FM receiver]

Next, the case where the tuning mechanism of the present embodiment described above is applied to an FM receiver will be described. The frequency control circuit 2 shown in Fig. 1 changes the control voltage for changing the frequency of the input signal of the inquiry circuit 1 to follow the frequency change and converting the control voltage fed back to the inquiry circuit 1. Therefore, in principle, this control voltage includes the same frequency component as the modulation signal of the FM wave, that is, the frequency change of the input signal of the reference signal 1, and can be used as the FM detection signal.

Fig. 19 is a diagram showing a configuration of a tuning mechanism that also serves as FM detection. Fig. In the configuration shown in the figure, the voltage synthesizing circuit 7 in the control signal generating circuit 4 shown in Fig. 1 is replaced with the voltage synthesizing circuit 7A, and in parallel with the return control voltage from the voltage synthesizing circuit 7A to the in- The signal is extracted.

20 is a circuit diagram showing the detailed configuration of the frequency control circuit 2 shown in Fig. The detailed configuration of each of the synchronous rectification circuit 3, the pulse conversion circuit 5 and the polarity determination circuit 6 constituting the frequency control circuit 2 is slightly different from the voltage synthesis circuit 7 shown in Fig.

The voltage synthesizing circuit 7A includes a differential amplifier including two tri-state buffers 700 and 702 and an operational amplifier 704 connected to the latter, and the voltage synthesizing circuit 7A controls the resistance of the variable resistor 706, The bias voltage of the control voltage to be applied to the line 1 can be arbitrarily changed in the same way as the voltage synthesizing circuit 7 shown in Fig.

In addition to these configurations, the voltage synthesizing circuit 7A has a second differential amplifier having a configuration substantially identical to that of the above-described first differential amplifier at the rear stage of the two tri-state buffers 700 and 702. [

Specifically, the second differential amplifier includes an operational amplifier 724, a feedback resistor 732 inserted between the inverting input terminal and the output terminal of the operational amplifier 724, a capacitor 734 connected in parallel to the feedback resistor 732, Inverting input terminal of the operational amplifier 724 and a resistor 736 interposed between the non-inverting input terminal of the op-amp 724 and the resistor 736 for performing the adjustment between the two inputs of the operational amplifier 724 by dividing the voltage level of the signal inputted through the resistor 728 at 702, And a capacitor 740 connected between the inverting input terminal of the operational amplifier 724 to which the signal is inputted through the resistor 730 and the ground, from the tristate buffer 700.

Thus, the second differential amplifier has the same configuration as the first differential amplifier.

However, the bias circuit configured by the variable resistor 706 is connected to the first differential amplifier, and this bias circuit is for setting a bias voltage to be applied to the gate of the variable resistor 116 included in the abnormality circuit 110C , It is not directly connected to the second differential amplifier since it is not directly related to the FM detection operation.

Further, in the first differential amplifier, the control voltage obtained by adjusting the capacitance of the capacitor 714 or the like connected in parallel with the feedback resistor 712 to smoothly change the voltage appearing at the output terminal of the operational amplifier 704 is obtained. In the second differential amplifier, The capacitance of the capacitor 734 and the capacitor 738 or 740 connected in parallel with the resistor 732 is adjusted to remove the high frequency component of about 20 kHz or more from the voltage appearing at the output terminal of the operational amplifier 724. Therefore, in the second differential amplifier, it is possible to extract FM detection signals such as frequency components of about 20 kHz or less, that is, FM voice.

As the configuration of the entire FM receiver including the tuning mechanism shown in Fig. 20, most of the configuration of the receiver shown in Fig. 18 (the low-pass filter 8 is unnecessary) can be applied as it is. That is, the FM wave received by the antenna 16 is high-frequency amplified by the high-frequency amplifying circuit 10, Only the FM wave (carrier) having the desired frequency is extracted by the control circuit 1 under the control of the frequency control circuit 2, and the FM detection circuit 2 which performs this control outputs the FM detection signal. The FM detection signal is amplified by the low-frequency amplifying circuit 12 and then output from the speaker 14. When various data such as characters are taken into consideration as the FM modulation signal, the data processing circuit may be substituted at the downstream end of the low-frequency amplification circuit 12. [

20, the frequency control circuit 2 shown in Fig. 20 detects the phase difference of the input / output signal of the inverse lookup circuit 1 as an error signal and controls the phase difference to be zero, so that the bias in the voltage synthesizing circuit 7A It is necessary to previously adjust the variable resistor 706 constituting the circuit and to set the tuning frequency of the tuning circuit 1 so as to be near the frequency of the FM wave to be received.

In this way, by adjusting the time constant of the smoothing circuit included in the differential amplifier of the voltage synthesizing circuit 7 in the frequency control circuit 2, it is possible to easily extract only the FM modulated signal from the FM-modulated signal input to the inquiry circuit 1 . When the tuning mechanism shown in Fig. 20 is applied to the FM receiver, the FM detection circuit, which is separately provided at the rear end of the tuning mechanism, is unnecessary, and the circuit configuration can be simplified.

In the conventional FM receiver, a limiter circuit is provided between the tuning mechanism and the FM detection circuit in order to perform FM detection after eliminating the influence of the amplitude fluctuation. However, in the tuning mechanism shown in Fig. 20, There is no influence of the amplitude fluctuation for converting into the pulse width corresponding to the change amount of the phase by using the included pulse conversion circuit 5 and a conventionally required limiter circuit is not necessary.

19 and 20 illustrate the case of extracting the FM detection signal from the voltage synthesizing circuit 7A in the frequency control circuit 2, it is a matter of course that, as in the conventional receiver, It is also possible to obtain an FM detection signal by connecting an FM detection circuit using various detection methods.

[F. Other Example of Frequency Control Circuit 1]

Next, another example of the configuration of the frequency control circuit 2 shown in Fig. 1 will be described. The voltage synthesizing circuit 7 in the frequency control circuit 2 shown in FIG. 13 has a tristate buffer, but other elements can be used.

Fig. 21 is a detailed circuit diagram showing another example of the configuration of the frequency control circuit, and has a configuration in which the voltage synthesizing circuit 7B shown in Fig. 13 is replaced by a voltage synthesizing circuit 7B. The voltage synthesizing circuit 7B shown in Fig. 21 includes two inverter-equipped Noah gates 744 and 746 for inverting the signals input to two input terminals to logically obtain their logical values, a differential amplifier including an operational amplifier 704 therein, and a variable resistor 706 And a bias circuit included therein.

Comparing the voltage synthesizing circuit 7B shown in Fig. 21 with the voltage synthesizing circuit 7 shown in Fig. 13, the configurations of the differential amplifier and the bias circuit except the two NOR gates 744 and 746 are the same as those of the voltage synthesizing circuit 7 And the tri-state buffers 700 and 702 shown in FIG. 13 are replaced with the NOR gates 744 and 746, and the wiring of the input / output is changed.

One of the input terminals of one of the NOR gates 744 is connected to the output terminal of the inverter circuit 61 at the rear end in the polarity determination circuit 6 and the other input terminal is connected to the inverted output terminal of the flip flop 63 at the rear end in the polarity determination circuit 6 . One of the input terminals of the other NOR gate 746 is connected to the output terminal of the inverter circuit 61 and the other input terminal of the NOR gate 744 is connected to the output terminal Q of the flip flop 63 described above.

22 is a timing chart in the case where the tuning frequency of the tuning circuit 1 is higher than the frequency of the signal inputted to the tuning circuit 1 shown in Fig. 21, and the synchronizing rectifying circuit 3, the pulse converting circuit 5 , The polarity determination circuit 6, and the voltage composition circuit 7B, respectively. 22 (A) - (M) correspond to the symbol A - M shown in the circuit diagram of FIG.

(A) to (J) of FIG. 22 are the same as those of FIGS. 14A to 14K except for FIG. 14H. In the following description, attention is focused on the operation of two N0 gates 744 and 746 do.

When the frequency of the input signal of 1 is higher than the tuning frequency, the flip-flop 63 at the rear stage of the polarity determination circuit 6 outputs a signal of logic H at the output terminal Q as shown in Figs. , And outputs a signal of logic L at the inverted output terminal.

Therefore, only the NOR gate 744 to which the signal of logic L is input inverts the logic of the output signal of the inverter circuit 61 having the waveform substantially the same as that of FIG. 22 (G), and outputs the signal shown in FIG. Further, the Noah gate 746 to which the signal of logic H is inputted always outputs a signal having a state of logic L, regardless of the logic state of the output signal of the inverter circuit 61, as shown in Fig. 22 (L).

As described above, positive pulses are output from only one of the NOR gates 744, and input to the inverting input terminal of the operational amplifier 704 through the resistor 710. 22 (M), the differential amplifier including the operational amplifier 704 gradually decreases the output voltage, that is, the control voltage, corresponding to the pulse width of the signal input from the Noah gate 744. Thus, the control voltage fed back to the inquiry line 1 is lowered, and the tuning frequency of the tuning circuit 1 is changed to the lower side.

23 is a timing chart when the tuning frequency of the tuning circuit 1 is lower than the frequency of the signal input to the tuning circuit 1 shown in Fig. 21, and Figs. 23 (A) to 23 (M) Corresponds to the symbol A - M shown in Fig.

As shown in (I) and (J) of FIG. 23, when the tuning frequency is higher, the flip-flop 63 at the rear end in the polarity determination circuit 6 outputs the signal of logic L at the output terminal Q, Respectively.

Therefore, only the Noah gate 746 to which the signal of logic L is input inverts the logic of the output signal of the inverter circuit 61 having substantially the same waveform as that of Fig. 23 (G), and outputs the signal shown in Fig. 23 (L). Further, the Noah gate 744 to which the signal of logic H is inputted is not related to the logic state of the output signal of the inverter circuit 61, and outputs a signal having a logic (L) state at all times do.

In this manner, positive pulses are output from only one of the NOR gates 746, and are input to the non-inverting input terminal of the operational amplifier 704 through the resistor 708. 23 (M), the differential amplifier including the operational amplifier 704 gently increases the output voltage, that is, the control voltage, by an amount corresponding to the pulse width of the signal input from the Noah gate 746. [ In this way, the control voltage fed back to the inquiry line 1 becomes high and the tuning frequency of the tuning circuit 1 is changed to the higher side.

21, when the frequency of the input signal to the tuner circuit 1 deviates from the tuning frequency, the control voltage is generated so that this deviation is small, The frequency of the input signal is always followed.

Since the respective components can be formed on the semiconductor substrate in the same manner as the tuning mechanism shown in Fig. 13, the tuning mechanism shown in Fig. 21 can be formed entirely of a tuning mechanism, a tuning mechanism, And can be integrated on a substrate. Particularly, when the entire tuning mechanism is integrated, appropriate feedback is applied even if various element constants change, and a stable tuning frequency can be achieved. In addition, the above-mentioned tuning mechanism is free from the influence of the amplitude variation of the input signal, and is capable of stable tuning control which is less affected by external factors.

The basic operation of the tuning mechanism shown in Fig. 21 is the same as that of the tuning mechanism shown in Fig. 13, and when the AM wave is considered as the input to the tuning circuit 1, the synchronous rectifying circuit 3 Through the low-pass filter, the AM detection signal can be taken out and configured in the AM receiver.

Likewise, when the FM wave is taken into consideration as the input to the inquiry circuit 1, the FM detection signal can be taken out from the voltage synthesizing circuit as shown in Fig. 19 to constitute the FM receiver. In this case, in the voltage synthesizing circuit 7B shown in Fig. 21, a second differential amplifier (a differential amplifier including an operational amplifier 724 in the voltage synthesizing circuit 7A shown in Fig. 20 and a differential amplifier And the FM detection signal of about 20 kHz or less is taken out from the second differential amplifier.

[G. Another example of frequency control circuit 2]

Next, other examples of the configuration of the frequency control circuit 2 shown in Fig. 1 will be described. The voltage synthesizing circuit 7 shown in detail in FIG. 13 uses a tri-state buffer or the voltage synthesizing circuit 7B shown in FIG. 21 in detail, using a N0 gate. Instead of these elements, Can be used.

Fig. 24 is a circuit diagram showing another configuration of the frequency control circuit. The synchronous rectification circuit 3, the pulse conversion circuit 5, the polarity determination circuit 6, and the voltage synthesis circuit 7 shown in Fig. 13 are connected to the synchronous rectification circuit 3A, the pulse conversion circuit 5A The polarity determination circuit 6A, and the voltage synthesis circuit 7C.

The synchronous rectification circuit 3A includes an analog switch (AS) 35 and a voltage comparator. The inverting input terminal of the voltage comparator 36 is grounded. When the potential of the signal input to the non-inverting input terminal is greater than 0 V, the output terminal is at a predetermined positive voltage level. On the other hand, Becomes a predetermined negative voltage level. By using such a voltage comparator 36, it is possible to directly generate the voltage of the positive bipolar without using the level shifter 34 shown in Fig.

The analog switch 35 performs ON / OFF operation of the switch in response to the voltage of the signal output from the voltage comparator 36. When the output terminal of the voltage comparator 36 is at a predetermined constant voltage, And blocks this input signal when the output is a predetermined negative voltage.

The pulse conversion circuit 5A has basically the same configuration as that of the pulse conversion circuit 5 shown in Fig. 13, except that the voltage comparator 50 shown in Fig. 13 is replaced by a voltage comparator 58. Fig. The voltage comparator 58 outputs a negative pulse when the voltage level of the synchronous rectified output inputted to the non-inverting input terminal is lower than 0 V, and when the voltage level of the synchronous rectified output is 0 V or positive, The level becomes 0 V.

The polarity determination circuit 6A includes a voltage comparator 64 for outputting a pulse train having a voltage state of a positive polarity, two inverter circuits 65 and 66 for operating as a delay circuit, and two flip flops 67 and 68.

Signals input to the two input terminals of the voltage comparator 58 described above are input in parallel to the two input terminals of the voltage comparator 64. The voltage comparator 64 performs the same voltage comparison operation as that of the voltage comparator 58, And a pulse train having a positive or negative voltage state is output.

The two inverter circuits 65 and 66 and the two flip-flops 67 and 68 correspond to the two inverter circuits 60 and 61 and the two flip-flops 62 and 63 shown in Fig. 13 and basically perform the same operation. However, There is a difference in that the logic H corresponds to a predetermined constant voltage and the logic L corresponds to a predetermined negative voltage.

The voltage synthesizing circuit 7C includes two analog switches (AS) 750 and 752, a first inverting amplifier made up of an operational amplifier 754 and two resistors 756 and 758, an operational amplifier 760, and a second A capacitor 768 connected in parallel to the resistor 766 for smoothing the output voltage of the second inverting amplifier, and a bias circuit composed of a variable resistor 770 and a resistor 772 connected between the power supplies Vdd and Vss. .

The one-way analog switch 750 performs ON / OFF operation of the switch in accordance with the voltage level of the signal output from the output terminal Q of the flip-flop 68 at the rear end in the polarity determination circuit 6A. When the logic of the signal output from the output terminal Q is H, that is, when a predetermined positive voltage is applied, the analog switch 750 inputs the signal output from the voltage comparator 58 in the pulse conversion circuit 5A to the first inverting amplifier through the resistor 756 .

The first inverting amplifier inverts the voltage polarity of the signal output from the analog switch 750 and inputs the inverted signal of the voltage polarity to the second inverting amplifier through the resistor 762. [

The other analog switch 752 performs ON / OFF operation of the switch in accordance with the voltage level of the signal output from the inverted output terminal of the flip-flop 68 at the rear end in the polarity determination circuit 6A. When the logic of the signal output from the inverting output terminal is H, that is, when a predetermined predetermined voltage is applied, the analog switch 752 inputs the signal output from the voltage comparator 58 in the pulse converting circuit 5A to the second inverting amplifier through the resistor 764 .

A resistor 762 whose output terminal of the first inverting amplifier is connected at one end to the inverting input terminal of the second inverting amplifier, a resistor 772 whose one end is connected to the bias circuit constituted by the resistor 770, And the resistor 764 is connected. The second inverting amplifier further reverses the polarity of the added voltage. In parallel with this reversal operation, the voltage of the capacitor 768 is smoothed.

Next, the operation of the tuning mechanism shown in Fig. 24 will be described by dividing the case where the tuning frequency is high and the case where the tuning frequency is low, with respect to the frequency of the input signal of the inquiry circuit 1. Fig.

25 is a timing chart in the case where the tuning frequency of the tuning circuit 1 is higher than the frequency of the signal input to the tuning circuit 1 shown in Fig. 24, and the synchronous rectifying circuit 3A, the pulse converting circuit 5A The polarity determination circuit 6A, and the voltage synthesis circuit 7C. Each of the timing waveforms in FIGS. 25A to 25M corresponds to the symbol A - M shown in the circuit diagram of FIG.

When the tuning frequency is higher than the frequency of the input / output signal of the inquiry line 1, a potential difference corresponding to the shift of the frequency occurs. Thus, when two signal waveforms at any point are observed, It becomes the phase relation shown.

The voltage comparator 36 in the synchronous rectification circuit 3A outputs the signal of the L level having the predetermined negative voltage when the voltage level of the output signal of the reference signal line 1 is lower than 0 V and the signal of L level having the predetermined constant voltage when it is higher than 0 V And outputs a signal. Therefore, the voltage comparator 36 outputs a rectangular wave having the same frequency and phase as the tuning output shown in Fig. 25 (C).

The analog switch 35 performs the ON / OFF operation of the switch corresponding to the voltage level of the square wave output from the voltage comparator 36. [ When the tuned output of the inquiry furnace 1 is higher than the input signal, the waveform slightly shifted forward from the complete full-wave rectified waveform shown in Fig. 25 (D), that is, the timing at which the upper half of the tuning output is extracted at a slightly earlier timing The extracted waveform is outputted from the analog switch 35.

The voltage comparator 58 in the pulse conversion circuit 5A is set to the L level (predetermined negative voltage) only when the voltage level of the output of the analog switch 35 becomes lower than 0 V, and the signal of the H level (0 V) otherwise Output. 25 (E), when the synchronous rectified output outputted from the analog switch 35 is slightly shifted forward from the half-wave rectified waveform, the voltage comparator 58 outputs the L level at the timing corresponding to this forward shift, That is, a negative pulse is output.

25 (F) when the voltage comparator 64 in the polarity discriminating circuit 6A carries out the same voltage comparison operation and the synchronous rectified output outputted from the analog switch 35 is shifted slightly forward from the half-wave rectified waveform, The output becomes the L level (predetermined negative voltage) at the timing corresponding to the shift in the front direction, and the output becomes the H level (predetermined constant voltage) at the other timing. As described above, the output of the voltage comparator 64 corresponds to a predetermined constant voltage at the H level, which differs from the voltage comparator 58 described above.

The flip flop 67 at the previous stage in the polarity discrimination circuit 6A outputs the signal outputted from the voltage comparator 36 in the synchronous rectification circuit 3A at the timing at which the output of the voltage comparator 64 goes from the L level to the H level (exactly this timing is delayed by a predetermined time) Lt; / RTI > 25 (F) and (C), when the signal outputted from the voltage comparator 64 goes up, the signal outputted from the voltage comparator 36 goes to the H level. Is held by the flip-flop 67 of the previous stage.

Further, the flip-flop 68 at the subsequent stage receives and holds the output of the flip-flop 67 at the preceding stage at the timing at which the output of the voltage comparator 64 rises next. At the output terminal Q, Respectively.

Thus, when the tuning frequency is higher than the frequency of the input signal of the inquiry circuit 1, a signal of logic H is output from the output terminal Q of the flip-flop 68 at the subsequent stage, and the switching operation of one analog switch 750 in the voltage synthesizing circuit 7C Is turned on. Therefore, the analog switch 750 outputs the signal (negative pulse train) output from the voltage comparator 58 as it is (Fig. 25 (J)) and blocks the signal output from the voltage comparator 58 in the other analog switch 752. (Fig. 25 (K))

The first inverting amplifier configured with the operational amplifier 754 inverts the pulse string of the negative polarity output from the analog switch 750 and converts it into a pulse train of positive polarity shown in Fig. 25 (L).

The pulse train of positive polarity is input to a second inverting amplifier constituted by the operational amplifier 760. The second inverting amplifier gently reduces the output voltage, that is, the control voltage, by an amount corresponding to the pulse width of the positive pulse (Fig. 25 (M)).

In this way, the control voltage fed back to the inquiry line 1 is lowered and the tuning frequency of the tuning circuit 1 is changed to the lower side. Such control is repeated until there is no deviation between the frequency of the input signal of 1 and the tuning frequency, and the tuning frequency coincides with the frequency of the input signal after a predetermined time elapses.

26 is a timing chart when the tuning frequency of the tuning circuit 1 is lower than the frequency of the signal inputted to the tuning circuit 1 shown in Fig. Each of the timing waveforms in Figs. 26A to 26M corresponds to the reference numeral A - M shown in the circuit diagram of Fig.

When the tuning frequency is lower than the frequency of the input signal of the inquiry circuit 1, a signal corresponding to the logic H is outputted from the inverted output terminal of the flip flop 68 at the rear stage of the polarity determination circuit 6A, as opposed to the case where the above- , Only the switching operation of the other analog switch 752 in the voltage synthesizing circuit 7C is turned on. Thus, in this analog switch 752, the signal (negative pulse train) output from the voltage comparator 58 is output as it is (Fig. 26 (K)) and the analog switch 750 cuts off the signal output from the voltage comparator 58. (Fig. 26 (J))

26 (L), the output terminal of the first inverting amplifier connected to the output side of the analog switch 750 maintains the voltage state of 0 V, and the negative pulse train output from the analog switch 752 and the predetermined pulse train Only the bias voltage is applied as an input to the second inverting amplifier configured to include the operational amplifier 760. [ Therefore, the second inverting amplifier gently raises the output voltage, that is, the control voltage, corresponding to the pulse width of the negative pulse. (Fig. 26 (M))

In this way, the control voltage fed back to the inquiry line 1 becomes high, and the tuning frequency of the tuning circuit 1 is changed to the higher side. Such control is repeated until there is no deviation between the frequency of the input signal of 1 and the tuning frequency, and the tuning frequency coincides with the frequency of the input signal after a predetermined time elapses.

[H. Another example of frequency control circuit 3]

Next, another example of the configuration of the frequency control circuit shown in Fig. 1 will be described. The voltage synthesizing circuit 7C having the detailed configuration in Fig. 24 has first and second inverting amplifiers, and if necessary, converts the negative pulse train into a positive pulse train by the first inverting amplifier, The first inverting amplifier can be omitted by providing the pulse string.

Fig. 27 is a detailed circuit diagram showing another example of the configuration of the frequency control circuit. The pulse conversion circuit 5A, the polarity determination circuit 6A, and the voltage synthesis circuit 7C shown in Fig. 24 are respectively connected to the pulse conversion circuit 5B, the polarity determination circuit 6B, And is replaced with a synthesis circuit 7D.

The pulse conversion circuit 5B has a voltage comparator 59 to which a synchronous rectified output outputted from the analog switch 35 in the synchronous rectification circuit 3A is inputted to a non-inverted input terminal and a voltage comparator 59 for applying a voltage slightly lower than 0 V to the inverted input terminal of the voltage comparator 59 And a voltage dividing circuit composed of resistors 52 and 54. The voltage comparator 59 outputs a pulse string having a certain voltage level as a comparison result.

The voltage synthesizing circuit 7D includes two inverter circuits 780 and 782 used as a delay circuit and used for extracting mutually inverted signals, a diode 784 for extracting positive pulses at the output of the inverter circuit 780 at the previous stage, a resistor 786 A diode 788 and a resistor 790 for extracting a pulse train having a negative polarity from the output of the inverter circuit 782 at the rear stage, two tristate buffers 700 and 702, an inverting amplifier including an operational amplifier 760 and a resistor 766, And a bias circuit formed by a capacitor 768 connected in parallel to the resistor 766 and a variable resistor 770 connected between the power supplies Vdd and Vss for smoothing the voltage. Among them, the inverting amplifier and the bias circuit perform basically the same operations as those included in the voltage synthesizing circuit 7C shown in Fig.

The inverter circuit 780 at the previous stage outputs a signal obtained by inverting the logic of the pulse string output from the voltage comparator 59 in the pulse conversion circuit 5B. When the voltage level of this signal becomes equal to or higher than the forward echo voltage of the diode 784, 786, only a positive pulse train is taken out and input to one tristate buffer 700.

Similarly, when the voltage level of this signal becomes lower than the forward voltage of the diode 788 that inverts the polarity, the inverter circuit 782 at the rear stage outputs a signal obtained by inverting the logic of the pulse string output from the inverter circuit 780 at the previous stage. 790, only the negative pulse train is taken out and input to the other tri-state buffer 702. [

The output of the inverter circuit 782 in the subsequent stage is input to the clock terminal C of the flip-flop 67 in the preceding stage in the polarity determination circuit 6B. As described above, the signal output from the voltage comparator 59 in the pulse conversion circuit 5B is input to the flip-flop 67 at the preceding stage in the polarity determination circuit 6B via the two inverter circuits 780 and 782 functioning as a delay circuit, In the polarity determination circuit 6A shown in Fig. 24, the signal output from the voltage comparator 64 is input to the flip-flop 67 at the previous stage through the two inverter circuits 65 and 66 functioning as a delay circuit.

In this manner, in the voltage synthesizing circuit 7D shown in Fig. 27, since the positive pulse train is generated by the diode 784 or the like, the first inverting amplifier including the operational amplifier 754 shown in Fig. 24 is not necessary. Therefore, after the output of the one tristate buffer 700 and the output of the other tri-state buffer 702 are simply calculated through the resistor 762 or 764, the inverting amplifier configured including the operational amplifier 760 inverts the polarity so that the desired control Voltage can be generated.

28 is a timing chart when the tuning frequency of the tuning circuit 1 is higher than the frequency of the signal inputted to the tuning circuit 1 shown in Fig. 27, and the operation timings of the input / output signals of the respective circuits constituting the frequency control circuit are Lt; / RTI > Each of Figs. 28 (A) - (N) corresponds to A-N shown in the circuit diagram of Fig.

(A) to (I) except for FIG. 28 (F) are the same as FIGS. (A) to (I) except for FIG. 25 (E).

When the frequency of the input signal of 1 is different from that of the tuning frequency, a signal having a pulse width corresponding to the phase difference is outputted from the voltage comparator 59 in the pulse converting circuit 5A (Fig. 28E) A signal obtained by inverting this signal is outputted from the inverter circuit 780 in the preceding stage. (Fig. 28 (F)).

28 (J), since the current flows through the diode 784 and the resistor 786 when the voltage of the signal output from the inverter circuit 780 of the previous stage becomes higher than the predetermined value, the diode 784 A pulse of a positive polarity is taken out and input to the tri-state buffer 700. Likewise, when the voltage of the signal output from the inverter circuit 782 in the subsequent stage becomes lower than a predetermined value, a current flows through the diode 788 and the resistor 790, A pulse of negative polarity is taken out and input to the tristate buffer 702.

However, when the tuning frequency is higher than the frequency of the input signal of 1, the signal (Fig. 28 (I)) corresponding to the logic H is outputted from the output terminal Q of the flip flop 68 in the subsequent stage in the polarity determination circuit 6B 28 (L) and (M), only one tri-state buffer 700 operates as a buffer.

Therefore, the pulse voltage of the positive polarity outputted from the one tristate buffer 700 is added to the predetermined bias voltage set by the bias circuit constituted by the variable resistor 770 at a predetermined cycle, and by the amount corresponding to the pulse width of this positive pulse , The output voltage of the inverting amplifier including the operational amplifier 760 is gradually lowered. In this manner, as shown in Fig. 28 (N), the control voltage applied to the tuning circuit 1 in the voltage synthesizing circuit 7D is lowered, and the tuning frequency is changed to the lower side.

29 is a timing chart when the tuning frequency is low as compared with the frequency of the input signal of the tuning circuit 1 shown in Fig. 27, and Figs. 29 (A) to 29 (N) Respectively.

When the tuning frequency is lower than the frequency of the input signal, the signal (FIG. 29 (H)) corresponding to the logic L at the output terminal Q of the flip flop 68 in the subsequent stage in the polarity determination circuit 6B is inverted (Fig. 29 (I)) are outputted respectively, and only the other tristate buffer 702 operates as a buffer, as shown in Figs. 29 (L) and 29 (M).

Therefore, the negative pulse voltage output from the other tri-state buffer 702 is added to the predetermined bias voltage set by the bias circuit configured by the variable resistor 770 at predetermined cycles, that is, the voltage is subtracted. As much as the pulse width of the pulse. The output voltage of the inverting amplifier including the operational amplifier 760 is gradually increased. 29 (N), the control voltage applied to the tuning circuit 1 in the voltage amplifying circuit 7D rises, and the tuning frequency is changed to the higher side.

In this way, according to the tuning mechanism shown in Fig. 24 or Fig. 27, when the frequency of the input signal of the tuning circuit 1 is deviated from the tuning frequency, the control voltage is changed so as to reduce the deviation, May always follow and match the frequency of the input signal.

The tuning mechanism shown in Fig. 24 or Fig. 27 can form each constituent element on a semiconductor substrate in the same manner as the tuning mechanism shown in Fig. 13, so that the entire tuning mechanism, the entire tuning mechanism Can be integrated on the semiconductor substrate. Particularly, when the entire tuning mechanism is integrated, even if various element constants are changed, appropriate feedback is applied and a stable tuning frequency can be set. In addition, the above-mentioned tuning mechanism is free from the influence of variations in the level of the input signal, and is capable of stable tuning control which is less susceptible to external influences.

The basic operation of the tuning mechanism shown in Fig. 24 or Fig. 27 is the same as that of the tuning mechanism shown in Fig. 13, and when the AM wave is taken as an input to the tuning circuit 1, 24 or the output of the synchronous rectification circuit 3A of Fig. 27 corresponding to Fig. 3 through the low-pass filter, the AM detection signal can be taken out to configure the AM receiver.

Likewise, when the FM wave is taken into consideration as the input to the inquiry circuit 1, the FM detection signal can be taken out as in the voltage synthesizing circuit 7A of FIG. 19 to configure the FM receiver.

In this case, in the voltage synthesizing circuit 7C shown in Fig. 24, one set of the third and fourth inverting amplifiers is separately set on the output sides of the two analog switches 750 and 752, It is sufficient to extract the FM detection signal. Alternatively, in the voltage synthesizing circuit 7D shown in Fig. 27, a second inverting amplifier may be connected in parallel to the output sides of the two tri-state buffers 700 and 702, and the FM detection signal of about 20 kHz or less may be taken out from the second inverting amplifier.

[First Modification of Tuning Circuit]

2, each of the ideal circuits 110C and 130C includes a CR circuit. However, by using an ideal circuit in which a CR circuit is replaced by an LR circuit constituted by a resistor and an inductor, a tuning circuit .

Fig. 30 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit. Fig. 30 shows a configuration that can be replaced with the abnormal circuit 110C of the preceding stage of the circuit 1 shown in Fig. The abnormal circuit 110L shown in the diagram has a configuration in which the capacitor 114 in the abnormal circuit 110C shown in Fig. 3 and the CR circuit made of the variable resistor 116 are replaced by an LR circuit composed of the variable resistor 116 and the inductor 117. [

Therefore, the relationship of the input / output voltage and the like of the abnormal circuit 110L shown in Fig. 30 is obtained by adding the voltage VC1 shown in Fig. 4 to the voltage VR1 across the variable resistor 116 as shown in the vector diagram of Fig. 31, VR1 may be replaced with the voltage VL1 across the inductor 117, respectively.

When the inductance of the inductor 117 is L and the resistance of the variable resistor 116 is R, the phase shift amount? 3 of the anomalous circuit 110L is determined by the LR circuit formed by the inductor 117 and the variable resistor 116, R) is the same as? 1 shown in the above-mentioned expression (6).

Fig. 32 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit. Fig. 32 shows a configuration that can be replaced with the abnormal circuit 130C at the rear stage of the circuit 1 shown in Fig. The abnormal circuit 130L shown in the diagram has a configuration in which the CR circuit constituted by the variable resistor 136 and the capacitor 134 in the abnormal circuit 130C shown in Fig. 5 is replaced with an LR circuit composed of the inductor 137 and the variable resistor 136. [

Therefore, as shown in the vector diagram of Fig. 33, the relationship of the input / output voltage of the abnormal circuit 130L shown in Fig. 32 is obtained by multiplying the voltage VC2 shown in Fig. 6 by the voltage VR2 across both ends of the variable resistor 136, May be replaced with the both-end voltage VL2 of the inductor 137, respectively.

The phase shift amount phi 4 of the anomalous circuit 130L is set to T2 when the time constant of the LR circuit constituted by the variable resistor 136 and the inductor 137 is T2 (the resistance value of the variable resistor 136 is R and the inductance of the inductor 137 is L, L / R) is the same as? 2 shown in the above-mentioned expression (7).

As described above, each of the abnormal circuit 110L shown in Fig. 30 and the abnormal circuit 130L shown in Fig. 32 is equivalent to the abnormal circuits 110C and 130C shown in Fig. 3 or Fig. 5. In the circuit 1 shown in Fig. 2 It is possible to replace the abnormal circuit 110C at the previous stage with the abnormal circuit 110L shown in Fig. 30 and replace the abnormal circuit 130C at the subsequent stage with the abnormal circuit 130L shown in Fig. 32, respectively. The tuning frequency of the tuning circuit including the above-mentioned circuits 110L and 130L is proportional to the reciprocal R / L of the time constant of the LR circuit in each of the abnormal circuits 110L and 130L, for example, the dual inductance L can be easily reduced Therefore, by integrating all of the tuning circuits constituted by the two abnormal circuits 110L and 130L, it becomes easy to increase the frequency of the tuning frequency.

Any one of the abnormal circuits 110C and 130C in the circuit 1 shown in Fig. 2 may be replaced with the abnormal circuits 110L and 130L shown in Fig. 30 or Fig. In the case where the tuning circuit is constituted by cascade-connecting the ideal circuit including the CR circuit and the ideal circuit including the LR circuit, the variation of the tuning frequency due to the temperature change is prevented when the tuning circuit is integrated. In other words, temperature compensation becomes possible.

When the abnormal circuit 110C shown in Fig. 3 is compared with the abnormal circuit 110L shown in Fig. 30, the direction of the change of each phase shift amount when the gate voltage of the FET forming the variable resistor 116 is changed is reversed. For example, in the ideal circuit 110C, the tuning frequency is changed to the high frequency side when the gate voltage of the variable resistor 116 is made lower in the voltage VR1. On the other hand, in the ideal circuit 110L, when the gate voltage of the variable resistor 116 is set to a lower voltage VR1, the tuning frequency changes to the low frequency side. 13, the connection between the two output terminals of the flip-flop 63 and the tri-state buffers 700 and 702 is changed or the output terminals of the two tri-state buffers 700 and 702 are connected to each other A slight variation is required so that the direction of the change in the control voltage applied to the tuning circuit 1 in the frequency control circuit 2 and the direction of the change in the tuning frequency in the tuning circuit 1 are reversed.

When at least one of the preceding and following error circuits 110C and 130C is replaced with the abnormal circuits 110L and 130L shown in Figs. 30 and 32 in the circuit 1 shown in Fig. 2, Any one of the voltage dividing circuits connected to the output terminals 112 or 132 may be omitted. Alternatively, it is also possible to omit the voltage dividing circuits of both, and to adjust the resistance ratio of the resistors 118 and 120 and the resistance ratio of the resistors 138 and 140 so as to compensate the loss occurring in the feedback loop of the reference circuit 1.

When the amplifying operation is unnecessary, the voltage divider circuit 160 at the rear end of the abnormal circuit at the rear end may be omitted and the output of the abnormal circuit at the rear end may be directly fed back to the front end. Or the resistance value of the resistor 162 in the voltage dividing circuit 160 may be set to an extremely small value and the division ratio may be set to 1.

[Second Modification of Tuning Circuit]

34 is a circuit diagram showing a second modification of the tuning circuit; Reference numeral 1A denotes a two-phase circuit 210C or 230C that performs phase shift 360. In total at a predetermined frequency by shifting a phase of an AC signal inputted thereto by a predetermined amount, a feedback resistor 170 and an input resistor 174 (the input resistor 174 is assumed to have a resistance value of n times the resistance value of the feedback resistor 170), so that the output (feedback signal) of the subsequent stage abnormal circuit 230C and the signal (input signal) And an adder circuit for adding in a predetermined ratio.

2, by setting the resistance values of the resistor 118 and the resistor 120 in the anterior error circuit 110C to be the same, it is possible to suppress the amplitude change when the frequency of the input AC signal is changed, The gain of the abnormal circuit 110C is set to a value larger than 1 by connecting a voltage dividing circuit composed of the resistors 121 and 123 to the output side. In contrast, the abnormal circuit 210C in the preceding stage included in the circuit 1A shown in Fig. 29 is not provided with the voltage dividing circuit in the abnormal circuit, and the resistance value of the resistor 120 'is set larger than the resistance value of the resistor 118' Is set to a value greater than one.

The same holds for the abnormal circuit 230C at the subsequent stage. The gain of the abnormal circuit 230C is set to a value larger than 1 by setting the resistance value of the resistor 140 'to be larger than the resistance value of the resistor 138'. A feedback resistor 170, an output terminal 192, and a resistor 178 are connected to the output terminal of the abnormal circuit 230C.

29, the output of the rear-stage abnormal circuit 230C is directly fed back, but the voltage-dividing circuit at the rear end of the rear-stage abnormal circuit 230C is connected to feed back the divided output through the feedback resistor 170 You can.

Incidentally, when the resistance values are set as described above and the gain of the abnormal circuit is set to a value larger than 1, a gain variation occurs depending on the frequency of the input signal. For example, in the case of the abnormal circuit 210C at the front end, when the frequency of the input signal is low, the abnormal circuit 210C becomes a voltagedifferential circuit, so that the gain at this time is doubled, Since the circuit 210C becomes an inverting amplifier, the gain at this time becomes -m times (m is the resistance ratio of the resistor 120 'and the resistor 180'). When the frequency of the input signal changes, the gain of the error circuit 210C also changes, The amplitude fluctuation occurs.

Such amplitude fluctuation can be suppressed by connecting a resistor 119 to the inverting input terminal of the operational amplifier 112 and matching the gain when the frequency of the input signal is low and when the frequency is high. More specifically, when the resistance value of the resistor 118 'is r and the resistance value of the resistor 120' is mr, the resistance value of the resistor 119 is set to mr / (m-1) Can be matched. Likewise, by connecting the resistor 139 having a predetermined resistance value to the inverting input terminal of the operational amplifier 132, the amplitude fluctuation of the output signal can be suppressed. Further, one end of the resistor 119 and the resistor 139 may be connected to a fixed potential other than the ground level.

[Third Modification of Tuning Circuit]

In the inquiry circuit 1A shown in Fig. 34, an example in which the CR circuit is included in the abnormal circuits 210C and 230C has been described, but the same abnormal circuit can be constructed even when the LR circuit is included in place of the CR circuit.

Fig. 35 is a circuit diagram showing the configuration of the abnormal circuit including the LR circuit. Fig. 35 shows a configuration that can be replaced with the abnormal circuit 210C in the preceding stage of the circuit 1A shown in Fig. The abnormal circuit 210L shown in the diagram has a configuration in which the capacitor 114 in the preceding abnormal circuit 210C and the variable resistor 116 shown in Fig. 34 are replaced by the LR circuit consisting of the variable resistor 116 and the inductor 117.

When the abnormal circuit 210C shown in Fig. 34 is compared with the abnormal circuit 210L shown in Fig. 35, the direction of the change in the phase shift amount when the gate voltage of the FET forming the variable resistor 116 is changed is reversed. For example, in the abnormal circuit 210C, when the gate voltage of the variable resistor 116 is raised to lower the voltage across the variable resistor 116, the tuning frequency changes to the high frequency side. On the other hand, in the ideal circuit 210L, the tuning frequency changes to the low frequency side when the gate voltage of the variable resistor 116 is made low at both ends of the variable resistor 116. 13, the connection between the two output terminals of the flip-flop 63 and the tri-state buffers 700 and 702 is changed or the connection between the output terminals of the two tri-state buffers 700 and 702 is changed It is necessary to slightly change the direction of the change of the control voltage applied to the tuning circuit 1 and the direction of the change of the tuning frequency of the tuning circuit 1 in the frequency control circuit 2 by reversing the connecting lines.

36 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit, and shows a configuration that can be replaced with the abnormal circuit 230C at the rear stage of the circuit 1A shown in Fig. The abnormal circuit 230L shown in the diagram has a configuration in which a CR circuit constituted by the variable resistor 136 and the capacitor 134 in the rear stage abnormal circuit 230C shown in Fig. 34 is replaced with an LR circuit composed of the inductor 137 and the variable resistor 136. [

35 is equivalent to the preceding-stage abnormal circuit 210C shown in Fig. 34, and in the inquiry circuit 1A shown in Fig. 34, the abnormal circuit 210C at the preceding stage corresponds to the abnormal circuit 210C shown in Fig. 210L, and the rear stage anomaly circuit 230C can be replaced with the abnormal circuit 230L shown in Fig. 36, respectively. When the two abnormal circuits 210C and 230C are replaced with the abnormal circuits 210L and 230L, the tuning frequency can be easily increased by integrating the entire tuning circuits. Any one of the two abnormal circuits 210C and 230C may be replaced by the abnormal circuit 210L or 230L. In this case, there is an effect of suppressing the variation of the tuning frequency with respect to the temperature change.

However, the resonance circuit 1A shown in Fig. 34 prevents the amplitude fluctuation when the tuning frequency is varied by connecting the resistors 119 or 139 to each of the two abnormal circuits 210C and 230C, but when the variable range of the frequency is narrow, It is also possible to construct the tuning circuit by removing the resistors 119 and 139 described above because the variation is small. Alternatively, the tuning circuit may be constituted by removing only one resistor 119 or 139.

[Fourth Modification of Tuning Circuit]

In the above-described circuits 1 and 1A, the loss of the loop gain of the feedback circuit made up of the feedback circuit 170 and the all-pass circuit including two abnormal circuits 110C and the like is caused by the input impedance of the preceding- In order to suppress the loss caused by the input impedance, a flow circuit of the transistor is inserted before the preceding stage anomaly circuit 110C and the like, and a signal fed back through this flow circuit is fed to the previous anomaly circuit (for example, 110C, 110L, and the like).

37 is a circuit diagram showing an example of a tuning circuit including a flow circuit therein. 1B is different from the circuit 1 shown in Fig. 2 in that the flow circuit 50 of the transistor Star is inserted at the front end side of the abnormal circuit 110C at the previous stage. The flow circuit 50 shown in Fig. 37 is constituted by a so-called source flow circuit, but it may be constituted by a limiter flow circuit. In FIG. 37, the voltage division ratio of the voltage divider circuit 160 may be set to 1, or by omitting the voltage divider circuit 160 itself, only the tuning operation may be performed without performing the amplifying operation as a whole.

When the flow circuit of the transistor star is cascaded to the front end side of the error circuit 110C or the like of the front end in this way, the resistance value of the feedback resistor 170 and the input resistor 174 can be increased as compared with the circuit of Fig. Particularly, in the case where the whole is integrated on a semiconductor substrate, it is preferable to increase the occupied area of the element in order to reduce the resistance value of the feedback resistor 170 and the like. Therefore, in the case of integration, it is effective to connect the flow circuit 50 shown in Fig. 37 in particular.

[Modified example 5 of the tuning circuit]

2, the phase shift amount by which the two abnormal circuits 110C and 130C are combined is 360. However, a non-inverting circuit that does not shift the phases is connected to the abnormal circuits 110C and 130C connected in cascade, .

38 is a circuit diagram showing the configuration of a 1C circuit which is obtained by connecting a noninverting circuit 150 to two preceding circuits. As shown in the figure, the inquiry circuit 1C includes the abnormal circuit 310C having the configuration in which the resistors 121 and 123 are omitted from the abnormal circuit 110C shown in Fig. 3, and the resistors 141 and 143 from the abnormal circuit 130C shown in Fig. An abnormal circuit 330C having an omitted configuration, a noninverting circuit 150 connected to the previous stage of the abnormal circuit 310C, a voltage dividing circuit 160 comprising resistors 162 and 164, and an adding circuit consisting of a feedback resistor 170 and an input resistor 174.

The abnormal circuits 310C and 330C shown in Fig. 38 have the same configuration as the abnormal circuits 110C and 130C shown in Fig. 3, except that no voltage divider circuit is connected to the output terminals of the operational amplifier 112 or 132, And the phase shift amount are the same as those of the abnormal circuits 110C and 130C. However, a ₁ = 1 in equation (2) and a ₂ = 1 in equation (3).

The non-inverting circuit 150 is constituted by an operational amplifier 152 to which an inverting input terminal to which an AC signal is inputted through a non-inverting input terminal is grounded via a resistor 154 and a resistor 156 connected between the inverting input terminal and the output terminal of the operational amplifier 152 . The operational amplifier 152 requires a predetermined amplification degree determined by the resistance ratio of the two resistors 154 and 156.

The abnormal circuit 310C has a gain of 1 because the resistance values of the resistors 118 and 120 are the same. Likewise, in the abnormal circuit 330C, since the resistance values of the resistors 138 and 140 are the same, the gain becomes 1. Therefore, in the above-described circuit 1C, the gain of the above-described non-inverting circuit 150 is set to a value larger than 1 instead of making a gain in each of the above-mentioned abnormal circuits.

The non-inversion circuit 150 having such a configuration outputs without changing the phase of the input circuit, and by adjusting the gain, it becomes easy to compensate for the attenuation of the signal amplification by the voltage divider circuit 160 and the loss occurring in the feedback loop. The noninverting circuit 150 also functions as a buffer connected to the front end side of the abnormal stage circuit 210C at the preceding stage in the same manner as the flow circuit by the above-described transistor star.

The non-inverting circuit 150 shown in Fig. 38 may be connected to the preceding stage of the tuning circuit 1 or 1A shown in Fig. 2 or Fig.

[Sixth Modification of Tuning Circuit]

Each of the above-described motion estimation circuits 1, 1A, 1B and 1C performs a predetermined tuning operation at a frequency at which the sum of the amounts of phase shift by two or more circuits is 360. However, two or more circuits The tuning circuit may be combined to perform a predetermined tuning operation at a frequency at which the sum of the amounts of phase shift by two or more circuits is 180. [

39 is a circuit diagram showing a sixth modified example of the tuning circuit, in which an abnormal circuit 310C 'is connected in place of the abnormal circuit 330C in the subsequent stage of FIG. 38, and a phase inverting circuit 180 is connected in place of the non- The abnormal circuit 310C 'in the subsequent stage has the same configuration as the abnormal circuit 310C in the preceding stage except that a resistor 115 having a fixed resistance value is connected instead of the variable resistor 116. [

The phase inversion circuit 180 is connected between the inverted input terminal through the resistor 184 and the op-amp 182 grounded by the non-inverted input terminal and the inverted input terminal and the output terminal of the op-amp 182 Resistors 186 and 186 are formed. When an AC signal is input to the inverting input terminal of the operational amplifier 182 through the resistor 184, a reverse-phase signal whose phase is inverted is output from the output terminal of the operational amplifier 182. The inverted signal is inputted to the preceding- do. The phase inversion circuit 180 has a predetermined amplification degree determined by the resistance ratio of the two resistors 184 and 186 and can obtain a gain greater than 1 by increasing the resistance value of the resistance 186 rather than the resistance value of the resistance 184.

As described above, each of the two abnormal circuits 310C and 310C 'is shifted in phase from 180 ° to 360 ° clockwise with respect to the input voltage Ei as the frequency ω of the input signal changes from 0 to ∞ . When the time constant of the CR circuits in the two abnormal circuits 310C and 310C 'is the same (referred to as T), the phase shift amount is 270 in each of the two abnormal circuits 310C and 310C' at the frequency of? = 1 / T . Therefore, the phase is shifted by 270.times.2 = 540. (= 180.) By all of the two abnormal circuits 310C and 310C ', and further, by the phase inverting circuit 180 connected to the two stages of the abnormal circuits 310C and 310C' A signal whose phase is shifted in phase and whose phase shift amount is 360. is output from the posteriori error circuit 310C '.

39, the gain of the above-described phase inversion circuit 180 is set to a value larger than 1, and the attenuation of the signal amplitude by the voltage dividing circuit 160 and the attenuation of the feedback loop It is easy to compensate for the loss occurring in the semiconductor device.

[Seventh Modification of Tuning Circuit]

Although the circuit 1D shown in Fig. 39 shows an example in which the abnormal circuits 310C and 310C 'are cascade-connected, it is also possible to perform the tuning operation even when the abnormal circuits 330C and 330C' shown in Fig. 38 are cascade-connected.

40 is a circuit diagram showing a seventh modification of the tuning circuit. The reference numeral 1E shown in the diagram is a cascade connection of the abnormal circuits 330C and 330C 'instead of the abnormal circuits 310C and 310C' shown in FIG. The anomaly circuit 330C 'at the previous stage has the same configuration as the anomaly circuit 330C at the previous stage except that a variable resistor 135 configured by FET or the like is connected instead of the resistor 136. [

Each abnormal circuit 330C and 330C 'in FIG. 40 has a phase shift from 0. to 180. clockwise from the input voltage Ei as the frequency? Of the input signal varies from 0 to? do. When the time constant of the CR circuit in the two abnormal circuits 330C is the same (referred to as T), the phase shift amount in each of the two abnormal circuits 330C and 330C 'becomes 90. at the frequency of? = 1 / T. Therefore, the phase is shifted 180 by the entirety of the two abnormal circuits 330C and 330C ', and the phase is reversed by the phase inversion circuit 180 connected to the two preceding circuits 330C and 330C' A signal whose phase shift amount is 360. is output from the posteriori error circuit 330C.

39, the gain of the above-described phase inversion circuit 180 is set to a value larger than 1, instead of making a gain in each of the above-mentioned circuits. In the above-described circuit 1E, It becomes easy to compensate for attenuation of the signal amplification and loss caused by the feedback loop.

Although the circuits 1C, 1D, and 1E shown in Figs. 38 to 40 each include two or more circuits including a CR circuit, they may be configured to include an LR circuit. For example, in the circuit 1C shown in Fig. 38, the abnormal circuit 310C at the preceding stage is replaced with the abnormal circuit omitted from the voltage divider circuit 110L shown in Fig. 30, and the abnormal circuit 330C at the subsequent stage is replaced with the abnormal circuit The abnormal circuit 130L may be replaced with an abnormal circuit which omits the voltage dividing circuit.

When the abnormal circuit 310C shown in FIG. 38 is compared with the abnormal circuit 110L shown in FIG. 30, the direction of the change in the phase shift amount when the gate voltage of the FET forming the variable resistor 116 is changed is reversed. For example, in the abnormal circuit 310C, when the gate voltage of the variable resistor 116 is raised to lower the voltage across the variable resistor 116, the tuning frequency changes to the high frequency side. On the other hand, in the ideal circuit 110L, the tuning frequency changes to the low frequency side when the gate voltage of the variable resistor 116 is set to a lower voltage across the variable resistor 116. Therefore, in the case of replacing the abnormal circuit of the front stage shown in Fig. 38 or 39 with the abnormal circuit omitting the voltage dividing circuit from the abnormal circuit 110L shown in Fig. 30, the two output terminals of the flip- State buffers 700 and 702 or the connection lines of the output terminals of the two tristate buffers 700 and 702 are interchanged to change the direction of the change in the control voltage applied to the tuning circuit 1 from the frequency control circuit 2 A slight change is required to be opposite to the direction of change of the tuning frequency of the inquiry line 1.

In the case where only the tuning operation is performed without amplifying the signal amplitude in the circuits 1C, 1D, and 1E shown in Figs. 38 to 40, the voltage divider circuit 160 may be omitted. A voltage dividing circuit may be connected to at least one output terminal of the operational amplifier in the two or more circuits. For example, when the voltage dividing circuit is connected to the output terminal of the operational amplifier 112 in the preceding stage circuit 310C and the output terminal of the operational amplifier 132 in the rear stage abnormal circuit 330C in the 1D circuit shown in Fig. 39, Inverting circuit 150 is connected to the front end of the anomaly circuit 110C at the preceding stage in the 1 st stage.

The connection positions of the non-inverting circuit 150 and the phase inverting circuit 180 shown in Figs. 38 to 40 are not limited to the front end side of the connected abnormal circuit, .

[Modification 8 of the tuning circuit]

Although any one of the first to seventh modifications of the above-described tuning circuit includes an operational amplifier in the ideal circuit, it is also possible to configure an ideal circuit using Transistor in place of the operational amplifier.

The synchronizing signal line 1F shown in Fig. 41 includes two more circuits 410C and 430C for performing a total 360 占 phase shift at a predetermined frequency by shifting the phase of the AC signal inputted thereto by a predetermined amount, and an output A noninverting circuit 450 amplifying and outputting a signal at a predetermined amplification degree without changing the phase of the signal, a voltage dividing circuit 160 consisting of resistors 162 and 164 provided at the rear end of the noninverting circuit 450, a feedback resistor 170 and an input resistor 174 (Feedback signal) of the voltage divider circuit 160 and a signal (input signal) input to the input terminal 190 at a predetermined ratio through each of the resistors .

The capacitor 172 connected in series with the feedback resistor 170 and the capacitor 176 inserted between the input resistor 174 and the input terminal 190 are intended to block the direct current and this impedance is extremely small at the operating frequency, Capacity.

Fig. 42 shows the configuration of the preceding stage anomaly circuit 410C shown in Fig. The anomaly circuit 410C of the former stage shown in the same figure has a FET 412 whose gate is connected to the input stage 122, a capacitor 414 connected in series between the source and the drain of the FET 412, and a variable resistor 416 and between the drain of the FET 412 and the constant- And a resistor 420 connected between the connected resistor 418 and the source of the FET 412 and the ground. At least one of the FET 412 and the FET 432 described later may be replaced with a Hypo Tr trainer star.

Here, the resistance values of the two resistors 418 and 420 connected to the source and the drain of the FET 412 are set to be substantially equal to each other. Considering the AC component of the input voltage applied to the input terminal 122, (Shifted in phase by 180) from the source of the FET 412 are respectively output from the drain of the FET 412. [

The resistor 426 in the abnormal circuit 410 shown in FIG. 41 is for applying a proper bias voltage to the FET 412. 42, for example, a channel formed in the source / drain of a junction-type FET is used as a resistor, and the resistance value can be arbitrarily changed within a certain range by varying the gate voltage.

When a predetermined AC signal is input to the input terminal 122, that is, when a predetermined AC voltage (input voltage) is applied to the gate of the FET 412, the source of the FET 412 is connected to the input voltage An in-phase AC voltage appears. On the other hand, an AC voltage having the same amplitude and the same voltage as the source appears in the drain of the FET 412 in the opposite phase to the input voltage. The amplitudes of the alternating-current voltage appearing at the source and drain are denoted by Ei.

A series circuit (CR circuit) constituted by a variable resistor 416 and a capacitor 414 is connected between the source and the drain of the FET 412. Therefore, a signal obtained by synthesizing the voltages appearing at the source and the drain of the FET 412 through the variable resistor 416 or the capacitor 414 is output from the output terminal 124.

Fig. 43 is a vector diagram showing the relationship between the input / output voltage of the preceding stage anomaly circuit 410C and the voltage appearing on the capacitor or the like.

Since the source and the drain of the FET 412 are in phase and in phase with the input voltage and the alternating voltage of the voltage amplitude Ei appears, the potential difference (alternating current component) between the source and drain becomes 2Ei. The voltage VC1 appearing at both ends of the capacitor 414 and the voltage VR1 appearing at both ends of the variable resistor 416 are out of phase with each other by 90 degrees and the resultant vector is the same as the voltage 2Ei between the source and the drain of the FET 412 .

Therefore, as shown in FIG. 43, a right triangle constituting two sides orthogonal to the voltage E1 across the capacitor 414 and the voltage across both ends of the capacitor 414 and the variable resistor 416 is formed by doubling the voltage Ei. Therefore, when the amplitude of the input signal is constant and only the frequency changes, the both-end voltage VC1 of the capacitor 414 and the both-end voltage VR1 of the variable resistor 416 change in accordance with the semicircular circumference shown in Fig.

However, if the potential difference between the connection point of the capacitor 414 and the variable resistor 416 and the ground level is subtracted as the output voltage Eo, the output voltage Eo is set such that the voltage VC1 and the voltage VR1 cross each other And the size of the circle is equal to the radius Ei of the semicircle. In addition, even if the frequency of the input signal changes, the end point of the vector only moves in the circumferential direction, so that a stable output can be obtained in which the output amplitude does not vary according to the frequency.

43, since the voltage VR1 and the voltage VC1 intersect at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 412 and the voltage VR1 is theoretically changed from 0 The voltage changes from 270 to 360 in the clockwise direction based on the voltage Ei of the voltage and the in-phase. The phase shift amount? 5 of the entire anomalous circuit 410C changes from 180. to 360. depending on the frequency. Furthermore, by varying the resistance value of the variable resistor 416, the phase shift amount? 5 can be changed.

The transfer function of the abnormal circuit 410C shown in Fig. 42 is a time constant of the CR circuit composed of the capacitor 414 and the variable resistor 416 as T ₁ (when the capacitance of the capacitor 414 is C and the resistance of the variable resistor 416 is R, ₁ = CR), it is possible to apply K2 as shown in the expression (2) (where a ₁ <1), and the phase shift amount Φ 5 shown in FIG. 43 is also expressed by the expression ? 1.

Likewise, FIG. 44 shows the configuration of the rear stage anomaly circuit 430C shown in FIG. The abnormal circuit 430C in the subsequent stage, which is shown in the same figure, includes a FET 432 whose gate is connected to the input terminal 142, a capacitor 434 and a variable resistor 436 connected in series to the source / drain of the FET 432, And a resistor 440 connected between the source of the FET 432 and the ground.

The resistance values of the two resistors 438 and 440 connected to the source and the drain of the FET 432 shown in FIG. 44 are set to be substantially equal to each other and the AC component of the input voltage applied to the input terminal 142 A signal whose phase is inverted from the source of the FET 432 is outputted from the drain of the FET 432, respectively.

The resistor 446 in the abnormal circuit 430C shown in Fig. 41 is for applying a bias voltage suitable for the FET 432. Fig. The capacitor 148 provided on the input side of the abnormal circuit 430C is a DC current blocking type excluding the DC component from the output of the abnormal circuit 410C, and only the AC component is inputted to the abnormal circuit 430C.

When a predetermined alternating voltage (input voltage) is applied to the gate of the FET 432 when a predetermined AC signal is input to the input terminal 142 in the ideal circuit 430C having such a configuration, An alternating voltage having the same amplitude and the same voltage appearing as a source opposite to the input voltage appears at the drain of the FET 432. [ The amplitudes of the alternating-current voltage appearing at the source and drain are denoted by Ei.

A series circuit (CR circuit) constituted by a capacitor 434 and a variable resistor 436 is connected between the source and the drain of the FET 432. Therefore, a signal obtained by synthesizing the voltages appearing at the source and the drain of the FET 432 through the capacitor 434 or the variable resistor 436 is output from the output terminal 144.

45 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit 430C at the subsequent stage and the voltage appearing on the capacitor or the like.

The potential difference between the source and the drain is 2Ei because the source and drain of the FET 432 exhibit an AC voltage of the same amplitude and opposite phase and voltage amplitude Ei with the input voltage, respectively. The voltage VR2 appearing at both ends of the variable resistor 436 and the voltage VC2 appearing at both ends of the capacitor are 90 degrees out of phase with each other, and the sum of them is equal to the potential difference 2Ei between the source and the drain of the FET 432.

Therefore, as shown in FIG. 45, a right angle triangle constituting two sides orthogonal to the voltage E2 of the variable resistor 436 and the voltage VC2 of both ends of the capacitor 434 is formed by doubling the voltage Ei. Therefore, when the amplitude of the input signal is constant and only the frequency is changed, the both-end voltage VR2 of the variable resistor 436 and the both-end voltage VC2 of the capacitor 134 change in accordance with the circumference of the semicircle shown in Fig.

Assuming that the potential difference between the connection point between the variable resistor 436 and the capacitor 434 and the ground level is taken out as the output voltage Eo, this output voltage Eo is obtained by crossing the voltage VR2 and the voltage VC2 with the center point of the semi- It can be expressed as a vector whose end point is a circle, and its size is equal to the radius Ei of the semicircle. Furthermore, even if the frequency of the input signal changes, the end point of the vector only moves on the circumference, and a stable output can be obtained in which the output amplitude does not change according to the frequency.

45, since the voltage VR2 and the voltage VC2 cross each other at right angles on the circumference, the phase difference between the input voltage applied to the gate of the FET 432 and the voltage VC2 theoretically becomes zero as the frequency ω changes from 0 to ∞. To 90. &lt; / RTI &gt; The phase shift? 6 of the entire anomalous circuit 430C varies from 0 to 180 according to the frequency.

Further, the transfer function of the one or more circuit 430C shown in Fig. 51 when the time constant of the CR circuit with the capacitor 434 and variable resistor 436 to the capacitance of the T ₂ (the capacitor 434 to the C, R the resistance value of the variable resistor is T ₂ = CR) Speaking is, expression (3) can be applied as a K3 shown in which (where, a ₂ <1), the phase shift amount Φ6 shown in FIG. 45 one Φ2 shown in the above expression (7) .

In this manner, the phase is shifted by a predetermined amount in each of the two abnormal circuits 410C and 430C, and as shown in Figs. 43 and 45, the phase shift amount of the two abnormal circuits 410C and 430C A signal having a total of 360. is output.

In the non-inverting circuit 450 shown in Fig. 41, the FET 452 in which the resistor 454 is connected between the drain and the positive power source and the resistor 456 is connected between the source and the ground, and the FET 452 is connected between the base and the drain of the FET 452, A transistor star 458 connected to the source of the FET 452 through the collector resistance 460, and a resistor 462 for applying a proper bias voltage to the FET 452. The capacitor 164 provided at the front end of the non-inverting circuit 450 shown in FIG. 41 and the output of the subsequent-stage abnormal circuit 430C exclude the direct current component, and only the AC component is input to the non-inverting circuit 450.

The FET 452 outputs a reverse-phase signal from the drain when an AC signal is input to the gate. When the signal of the opposite phase is inputted to the base of the transistor star 458, if the phase of the signal inputted to the gate of the FET 452 is regarded as a signal obtained by inverting the phase of the silver phase, the same phase signal is outputted from the collector, A signal is output from the non-inverting circuit 450. [

The output of the noninverting circuit 450 is taken out from the output terminal 192 as the output of the inquiry circuit 1 and the output of the noninverting circuit 450 is fed through the feedback resistor 160 to the input side of the anterior- It is returned. Then, the feedback signal is added to the signal inputted through the input resistor 174, and the voltage of the added signal is applied to the input terminal (input terminal 122 shown in FIG. 42) of the previous stage abnormal circuit 410C.

The gain of the non-inverting circuit 450 is determined by the resistance values of the resistors 454, 456 and 460 described above. By adjusting the resistance values of the resistors 454, 456 and 460, the two abnormal circuits 410C and 430C, 160, and the loop gain of the whole loop is set to be 1 or less.

Since the output signal of the noninverting circuit 450 before being input to the voltage dividing circuit 160 is taken out from the output terminal 192 of the inquiry circuit 1, the gain of the 1F itself can be made gain and the signal amplitude can be amplified Lt; / RTI &gt;

[Ninth Modification of Tuning Circuit]

The tuning circuit shown in Fig. 41 includes a CR circuit in each of the ideal circuits 410C and 430C, but it is also possible to configure a tuning circuit by using an ideal circuit in which the CR circuit is replaced by an LR circuit constituted by a resistor and an inductor.

Fig. 46 is a circuit diagram showing the configuration of the abnormal circuit including the LR circuit and is shown in a configuration that can be replaced with the abnormal circuit 410C in the preceding stage of the circuit 1F shown in Fig. The abnormal circuit 410L shown in the diagram has a configuration in which the CR circuit constituted by the capacitor 414 and the variable resistor 416 in the preceding abnormal circuit 410C shown in Fig. 41 is replaced with an LR circuit composed of the variable resistor 416 and the inductor 417, And the resistance value of the resistance 420 are set to the same value. The capacitor 419 inserted between the inductor 417 and the drain of the FET 412 is for DC current blocking.

Output voltage and the like of the above-described abnormal circuit 410L is obtained by multiplying the voltage VC1 shown in Fig. 43 by the voltage VR1 across the variable resistor 416 and the voltage VR1 shown in Fig. 43 by the voltage VR1 of the inductor 417 End voltage VL1, respectively.

And if the time constant of the LR circuits in degrees shown in 46 circuit transfer function of 410L has inductor 417 and variable resistor 416, the inductance of T ₁ (inductor 417 to the L, R the resistance value of the variable resistor 416 is T ₁ = (A ₁ < 1), the phase shift amount? 7 shown in FIG. 47 is also the same as the phase shift amount? 1 shown in the above-mentioned formula (6) .

Therefore, the abnormal circuit 410L shown in Fig. 46 is basically equivalent to the abnormal circuit 410C shown in Fig. 42, and the abnormal circuit 410C shown in Fig. 42 can be replaced with the abnormal circuit 410L shown in Fig.

When the abnormal circuit 410C shown in Fig. 42 is compared with the abnormal circuit 410L shown in Fig. 46, the direction of the change in the phase shift amount when the gate voltage of the FET forming the variable resistor 416 is changed is reversed. For example, in the ideal circuit 410C, when the gate voltage of the variable resistor 416 is raised to a lower voltage VR1, the tuning frequency changes to the low frequency side. 13, the connection between the two output terminals of the flip-flop 63 and the tri-state buffers 700 and 702 is changed or the connection between the output terminals of the two tri-state buffers 700 and 702 is changed It is necessary to change the connection line so that the direction of the change of the control voltage applied to the tuning circuit from the frequency control circuit 2 and the direction of the change of the tuning frequency of the tuning circuit are reversed.

Fig. 48 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit and is shown in a configuration that can be replaced with the abnormal circuit 430C at the rear stage of the circuit 1F shown in Fig. The abnormal circuit 430L shown in the diagram has a configuration in which a CR circuit constituted by a capacitor 434 and a variable resistor 436 in a rear stage abnormal circuit 430C shown in Fig. 44 is replaced with an LR circuit composed of a variable resistor 436 and an inductor 437, And the resistance value of the resistance 440 are set to the same value. The capacitor 439 inserted between the variable resistor 436 and the drain of the FET 432 is for DC current blocking.

The relationship of the input / output voltage of the above-described abnormal circuit 430L is obtained by multiplying the voltage VR2 shown in Fig. 45 by the voltage VL2 across the inductor 437 as shown in the vector diagram of Fig. 49 and by multiplying the voltage VC2 shown in Fig. And the voltage VR2, respectively.

The transfer function of the abnormal circuit 430L shown in FIG. 48 is T ₂ (the resistance value of the variable resistor 436 is R, and the inductance of the inductor 437 is L, the time constant of the LR circuit consisting of the variable resistor 436 and the inductor 437 is T ₂ = (A ₂ <1), the phase shift amount? 8 shown in FIG. 49 is also the same as the phase shift amount? 8 shown in the above-mentioned formula (7) .

Therefore, the abnormal circuit 430L shown in FIG. 48 is basically equivalent to the abnormal circuit 430C shown in FIG. 44, and the abnormal circuit 430C shown in FIG. 44 can be replaced with the abnormal circuit 430L shown in FIG.

One or both of the two abnormal circuits 410C and 430C shown in Fig. 41 can be replaced by the abnormal circuits 410L and 430L shown in Figs. 46 and 48, and both of the two abnormal circuits 420C and 430C can be replaced by abnormal In the case where the circuits 410L and 430L are replaced with each other, the tuning frequency can be easily increased by integrating the entire tuning circuits.

In the case where only one of the two abnormal circuits 410C and 430C is replaced with the abnormal circuit 410L or 430L, if the inductors constituting the LR circuit are included or all of the circuits except the inductors are integrated, Thereby preventing fluctuation of the tuning frequency. So-called temperature compensation becomes possible.

When at least one of the abnormal circuits 410C and 430C shown in FIG. 41 is replaced by the abnormal circuits 410L and 430L, the voltage divider circuit 160 may be omitted and the output of the abnormal circuit at the subsequent stage may be directly fed back to the preceding stage. Alternatively, the resistor 162 in the voltage dividing circuit 160 may be removed to make only the resistor 164. In the case where the voltage dividing circuit 160 is omitted or the resistor 162 is removed, only the tuning operation can be performed.

[Tenth modification of tuning circuit]

50 is a circuit diagram showing another modification of the tuning circuit; The reference numeral 1G denotes two abnormal circuits 410C and 410C 'that perform a total of 180 phase shifts at a predetermined frequency by shifting the phases of the AC signals inputted thereto by a predetermined amount, and the two abnormal circuits 410C and 410C' (Feedback signal) output to the phase inversion circuit 480 through the feedback resistor 170 and the input resistor 174, and a signal (input signal) input to the input terminal 190. The phase inversion circuit 480 inverts the phase of the output signal ) At a predetermined ratio.

42 and 43. For example, assuming that the time constant of the CR circuit constituted by the capacitor 414 and the variable resistor 416 is T ₁ , the phase relationship of the input / the phase shift amount PHI _{5 at} the frequency of? = 1 / T ₁ becomes 270 in the clockwise direction (phase slowing direction).

The rear stage anomaly circuit 410C 'has the same basic structure as the preceding stage anomaly circuit 410C except that the variable resistor 416 in the abnormal circuit 410C is replaced by a resistor 415 having a fixed resistance value. Therefore, assuming that the time constant of the CR circuit constituted by the resistor 415 and the capacitor 414 is T ₃ , for example, the phase shift amount? 5 'at the frequency of? = 1 / T _{3 corresponds to} the clockwise 270.

Therefore, the sum of the amount of phase shift in the phase slow direction by the entirety of the two abnormal circuits 410C and 410C 'becomes? 5 +? 5' = 270. + 270. = 540. (= 180.) At a predetermined frequency.

The error inversion circuit 480 includes a FET 482 having a resistor 484 connected between the drain and the positive power source and a resistor 486 connected between the source and the ground, and a resistor 488 applying a predetermined bias voltage to the gate of the FET 482 Consists of. When an AC signal is input to the gate of the FET 482, a reverse phase signal obtained by inverting the phase from the drain of the FET 482 is output. And the phase inversion circuit 480 has a predetermined gain determined by the resistance ratio of the two resistors 484 and 486.

As described above, the phase by the two or more circuits 410C is shifted by 180. At the predetermined frequency, the phase is inverted by the phase inversion circuit 480 connected at the subsequent stage, and the sum of the amounts of phase shift by the entirety of these three circuits is 360. Accordingly, the output of the phase inversion circuit 480 is fed back to the input side of the anomaly circuit 410C at the previous stage through the feedback resistor 170, the signal inputted through the input resistor 174 is added to the feedback signal, and the gain of the phase inversion circuit 480 is adjusted The same tuning operation as that of the tuning reference 1 shown in Fig. 2 is performed.

50, the output of the phase inversion circuit 480 is directly fed back through the feedback resistor 170. However, in the same way as the phase 1F shown in Fig. 41, the output of the phase inversion circuit 480 is fed back to the divisor circuit 160 And the partial pressure output may be returned.

[Eleventh Modification of Tuning Circuit]

Fig. 51 is a circuit diagram showing another modified example of the tuning circuit, and contrary to Fig. 50, the tuning circuit includes a rear stage anomaly circuit 430C shown in Fig.

The 1H circuit shown in FIG. 51 includes two abnormal circuits 430C and 430C 'for performing a phase shift of a total of 180. at a predetermined frequency by shifting the phases of AC signals inputted thereto by a predetermined amount, (Feedback signal) output from the phase inversion circuit 480 and a signal (input signal) input to the input terminal 190 through the feedback resistor 170 and the input resistor 174, respectively, and a phase inversion circuit 480 for inverting the phase of the output signal Signal) at a predetermined ratio.

44 and 45. For example, assuming that the time constant of the CR circuit constituted by the capacitor 434 and the variable resistor 436 is T ₂ , the phase relationship between the detailed configuration and the input of each of the ideal circuits 430C is as follows. The phase shift amount phi 6 at the frequency of 1 / T ₂ becomes 90 in the clockwise direction (phase slow direction).

The anomaly circuit 430C 'of the preceding stage is the same as the above-described abnormal circuit 430C in the basic stage described above, except that the resistor 435 in the abnormal circuit 430C is replaced with a variable resistor 436 whose resistance value can be changed by a control voltage applied from the outside I have. Therefore, assuming that the time constant of the CR circuit constituted by the resistor 436 and the capacitor 434 is T ₄ , for example, the phase shift amount? 6 'at the frequency of? = 1 / T ₄ is the clockwise 90.

In this manner, the phase is shifted 180 degrees by two more circuits 430C and 430C 'at a predetermined frequency, the phase is inverted by the phase inversion circuit 480 connected at the subsequent stage, and the phase shift amount The total is 360. Therefore, the output of the phase inversion circuit 480 is fed back to the input side of the anterior error circuit 430C 'through the feedback resistor 170, the signal input through the input resistor 174 is added to the feedback signal, and the gain of the phase inversion circuit 480 The same tuning operation as that of the tuning reference 1 shown in Fig. 2 is performed.

In the tuning circuit shown in Fig. 51, like the tuning circuit shown in Fig. 41, the voltage dividing circuit 160 may be connected to the rear end of the phase inversion circuit 480 so that amplification is performed simultaneously with tuning.

1F, 1G, 1H, and the like as described above are constituted by two or more abnormal circuits, a non-inverting circuit, two abnormal circuits, and a phase inverting circuit, And the total phase shift amount in the frequency is 360. The predetermined tuning operation is performed. Therefore, if only the amount of phase shift is taken into consideration, there is a certain degree of freedom in how to connect the three circuits in order, and the order of connection can be determined as needed.

50 and Fig. 51, an example in which the CR circuit is included in the abnormal circuit is shown in 1G and 1H. However, even if the tuning circuit is constructed by cascade-connecting the abnormal circuits including the LR circuit do. For example, instead of connecting the abnormal circuit 410L shown in FIG. 46 instead of the two abnormal circuits 410C shown in FIG. 50, the variable resistor 116 of the abnormal circuit 410L may be replaced by a resistance value An abnormal circuit replaced with a fixed resistor may be connected. Alternatively, it is also possible to connect an abnormal circuit obtained by replacing the resistance 436 of the abnormal circuit 430L shown in Fig. 48 with a variable resistor instead of the two abnormal circuits 430C 'in 1H, The circuit 430L may be connected.

[Twelfth Modification of Tuning Circuit]

52 is a circuit diagram showing a twelfth modification of the tuning circuit; The reference numeral 1J denotes a non-inverting circuit 550 that outputs the input AC signal without changing the phase of the input AC signal, and each of the non-inverting circuits 550 shifts the phase of the input signal by a predetermined amount so that a total of 360.phase shifts And the feedback resistor 170 and the input resistor 174 (the input resistor 174, which is n times the resistance value of the feedback resistor 170, are set to be the resistors 162 and 164 provided at the rear ends of the two abnormal circuits 510C and 530C, (Feedback signal) of the voltage divider circuit 160 and a signal (input signal) input to the input terminal 190 at a predetermined ratio.

The non-inverting circuit 550 functions as a buffer circuit and is provided to prevent signal loss or the like, which occurs when the preceding-stage abnormal circuit 510C and the above-described addition circuit are directly connected. The non-inverting circuit 550 is constituted by, for example, an emitter flow circuit and a source flow circuit. In the case where the element constant of each element is selected as the feedback resistor 170 or the like in order to minimize the loss or the like in the case of direct connection, the noninverting circuit 550 may be omitted to constitute the tuning circuit.

Fig. 53 shows the configuration of the preceding stage anomaly circuit 510C shown in Fig. The anomalous circuit 510C of the preceding stage shown in the diagram shows a differential amplifier 512 for amplifying and outputting a differential voltage of two inputs with a predetermined degree of amplification and a differential amplifier 512 for shifting the phase of a signal inputted to the input stage 122 by a predetermined amount and inputting to the non- And a resistor 518 and a resistor 520 for dividing the voltage level of the signal input to the input stage 122 and inputting the divided voltage to the inverting input terminal of the differential amplifier 512 .

The above-described variable resistor 516 is used as a resistor for a channel formed between the source and the drain of a junction-type FET, for example, as shown in FIG. 53, and the resistance value can be arbitrarily changed within a certain range by varying the gate voltage.

When a predetermined AC signal is input to the input terminal 122 shown in FIG. 53, a voltage obtained by dividing the voltage Ei applied to the input terminal 122 by the resistor 518 and the resistor 520 is applied to the inverting input terminal of the differential amplifier 512 .

When the input signal is input to the input terminal 122, a signal appearing at the connection point between the capacitor 514 and the variable resistor 516 is input to the non-inverting input terminal of the differential amplifier 512. Since the input signal is inputted to one end of the CR circuit constituted by the capacitor 514 and the variable resistor 516, the voltage of the signal obtained by shifting the phase of the input signal by a predetermined amount by this CR circuit is applied to the non-inverting input terminal of the differential amplifier 512 do. The differential amplifier 512 outputs a signal obtained by amplifying the difference between the voltages applied to the two input terminals by a predetermined amplification degree.

Fig. 54 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit 510C shown in Fig. 53 and the voltage appearing on the capacitor or the like.

As shown in the figure, the voltage VR1 appearing at both ends of the variable resistor 516 and the voltage VC1 appearing at both ends of the capacitor 514 are shifted by 90 degrees from each other. The input voltage Ei is obtained by adding them vectorially. Therefore, when the amplitude of the input signal is constant and only the frequency is changed, the both-end voltage VR1 of the variable resistor 516 and the both-end voltage VC1 of the capacitor 514 change according to the circumference of the semicircle shown in Fig.

The voltage (the both end voltage Ei / 2 of the voltage 520) applied to the inverting input terminal from the voltage (the both end voltage VR1 of the variable resistor 516) applied to the noninverting input terminal of the differential amplifier 512 is obtained by subtracting the difference voltage Eo '. This difference voltage Eo 'can be expressed by a vector having a circle point at the intersection of the voltage VR1 and the voltage VC1 at the center point of the semicircle shown in FIG. 54, and its size is represented by the radius Ei / 2 .

The output voltage Eo of the differential amplifier 512 is obtained by amplifying the difference voltage Eo 'by a predetermined amplification degree. Therefore, in the above-described abnormal circuit 510C, the output voltage Eo is constant regardless of the frequency of the input signal and operates as a global pass circuit.

54, since the voltage VR1 and the voltage VC1 intersect at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VR1 varies in the clockwise direction with respect to the input voltage Ei as the frequency ω changes from 0 to ∞ Phase slowing direction). The total phase shift amount phi 9 of the error circuit 510C varies from 180 to 360 depending on the frequency.

Similarly, FIG. 55 shows the configuration of the rear stage error circuit 530C shown in FIG. The anomaly circuit 530C in the subsequent stage, which is shown on the same diagram, shifts the phase of the signal input to the input stage 142 by a predetermined amount to the differential amplifier 532 for amplifying and outputting the difference voltage of two inputs with a predetermined amplification degree and outputs the shifted voltage to the noninverting input terminal of the differential amplifier 532 Resistors 538 and 540 for inputting a variable resistor 536 and a capacitor 534 to the inverting input terminal of the differential amplifier 532 by dividing the voltage level of the variable resistor 536 and the signal input to the input terminal 142 by about 1/2, have.

When a predetermined AC signal is input to the input terminal 142 shown in FIG. 55, a voltage obtained by dividing the voltage Ei applied to the input terminal 142 by the resistor 538 and the resistor 540 is applied to the inverting input terminal of the differential amplifier 532 .

When the input signal is input to the input terminal 142, a signal appearing at the connection point between the variable resistor 536 and the capacitor 534 is input to the non-inverting input terminal of the differential amplifier 532. Since the input signal is inputted to one end of the CR circuit constituted by the variable resistor 536 and the capacitor 534, the voltage of the signal obtained by shifting the phase of the input signal by a predetermined amount by this CR circuit is applied to the non-inverting input terminal of the differential amplifier 532 do. The differential amplifier 532 outputs a signal obtained by amplifying the difference between the voltages applied to the two input terminals by a predetermined amplification degree.

56 is a vector diagram showing the relationship between the input / output voltage of the error circuit 530C and the voltage appearing on the capacitor or the like.

The voltage VC2 appearing at both ends of the capacitor 534 and the voltage VR2 appearing at both ends of the variable resistor 536 are delayed by 90 degrees from each other as shown in the diagram, and the input voltage Ei is obtained by adding them vectorially. Therefore, when the amplitude of the input signal is constant and only the frequency is changed, the both-end voltage VC2 of the capacitor 534 and the both-end voltage VR2 of the variable resistor 536 change along the circumference of the semicircle shown in Fig.

The voltage (the both end voltage Ei / 2 of the resistor 540) applied to the inverting input terminal from the voltage (the both end voltage VC2 of the capacitor 534) applied to the noninverting input terminal of the differential amplifier 532 is obtained by subtracting the difference voltage Eo ' . This differential voltage Eo 'can be represented by a vector whose end point is a circumferential point where the voltage VC2 and the voltage VR2 intersect with the center point of the semicircle shown in FIG. 56 and whose size is represented by a radius Ei / 2 .

The output voltage Eo of the differential amplifier 532 is obtained by amplifying the differential voltage Eo 'by a predetermined amplification degree. Therefore, in the above-described abnormal circuit 530C, the output voltage Eo is constant regardless of the frequency of the input signal and operates as a global pass circuit.

56, since the voltage VC2 and the voltage VR2 cross at right angles on the circumference, the phase difference between the input voltage Ei and the voltage VC2 varies from 0 to 90 as the frequency ω changes from 0 to ∞. The phase shift amount? 10 of the whole of the ideal circuit 530C varies from 0 to 180 according to the frequency.

In this manner, the phases are shifted by a predetermined amount in each of the two abnormal circuits 510C and 530C, and as shown in Figs. 54 and 56, the sum of the phase shifts by the entirety of the two abnormal circuits 510C and 530C at a predetermined frequency A signal of 360 degrees is output.

The output of the error circuit 530C at the rear stage is taken out from the output terminal 192 as the output of the reference circuit 1J and the output of the error circuit 530C is fed back through the feedback resistor 170 to the input side of the non- do. The signal to which the feedback signal is inputted through the input resistor 174 is added, and the added signal is input to the anterior error circuit 510C through the noninversion circuit 550. [

By adjusting the gains of the above two abnormal circuits 510C and 530C, it is possible to compensate for the loss caused by the attenuation caused by the two abnormal circuits 510C and 530C and the voltage divider circuit 160 shown in FIG. 52 or the feedback loop, So that the total loop gain is set to 1 or less. Instead of adjusting the respective gains of the error circuits 510C and 530C, the non-inverting circuit 550 may have one or more gains to adjust this value.

Since the output of the ideal circuit 530C is taken out from the 1J output terminal 192 before being input to the voltage dividing circuit 190, the gain can be given to the 1J itself, and the signal amplitude can be amplified simultaneously with the tuning operation do.

When the amplitude operation is unnecessary in the tuning circuit shown in Fig. 52, the voltage divider circuit 160 may be omitted and the output of the abnormal circuit 530C may be directly fed back to the previous stage. Alternatively, the resistance value of the resistor 162 in the voltage dividing circuit 160 may be set to an extremely small value, and the division ratio may be set to 1.

[Modification 13 of the tuning circuit]

52, each of the ideal circuits 510C and 530C includes a CR circuit. However, a tuning circuit can be constructed by using an ideal circuit in which a CR circuit is replaced with an LR circuit constituted by a resistor and an inductor.

Fig. 57 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit, and shows a configuration that can be replaced with the abnormal circuit 510C in the preceding stage of the circuit 1J shown in Fig. The abnormal circuit 510L shown in the diagram has a configuration in which the capacitor 514 and the variable resistor 516 in the abnormal circuit 510C shown in Fig. 52 are replaced by the LR circuit consisting of the variable resistor 516 and the inductor 517. [ The capacitor 519 connected in series to the inductor 517 is for direct current blocking and its impedance is set to be extremely small at the operating frequency, that is, it has a large capacitance.

57 is a vector diagram showing the relationship between the input / output voltage of the abnormal circuit 510L and the voltage appearing in the inductor and the like. The phase shift amount? 11 of the abnormal circuit 510L displayed on the same diagram is represented by T ₁ (the resistance value of the variable resistor 516 is R, and the inductance of the inductor 517 is L, which is represented by L) by the time constant of the LR circuit constituted by the variable resistor 516 and the inductor 517 ₁ = L / R) is the same as? 1 shown in the above-mentioned equation (6).

When the abnormal circuit 510C shown in FIG. 52 is compared with the abnormal circuit 510L shown in FIG. 57, the direction of the change in the phase shift amount when the gate voltage of the FET forming the variable resistor 516 is changed is reversed. For example, in the abnormal circuit 510C, when the gate voltage of the variable resistor 516 is raised to a lower voltage VR1, the tuning frequency changes to the higher frequency side. On the other hand, in the ideal circuit 510L, the tuning frequency changes to the low frequency side when the gate voltage of the variable resistor 516 is made lower in the voltage VR1. 13, the connection between the two output terminals of the flip-flop 63 and the tri-state buffers 700 and 702 is changed or the connection between the output terminals of the two tri-state buffers 700 and 702 is changed It is necessary to slightly change the direction of the change of the control voltage applied to the tuning circuit from the frequency control circuit 2 and the direction of the change of the tuning frequency of the tuning circuit.

Fig. 59 is a circuit diagram showing another configuration of the abnormal circuit including the LR circuit, and shows a configuration that can be replaced with the abnormal circuit 530C in the rear stage of 1J shown in Fig. The abnormal circuit 530L shown in the diagram has a configuration in which the CR circuit constituted by the variable resistor 536 and the capacitor 534 in the abnormal circuit 530C shown in Fig. 55 is replaced by an LR circuit composed of the inductor 537 and the variable resistor 536. [ The capacitor 539 connected in series to the inductor 537 is for direct current blocking, and its impedance is set to be extremely small at the operating frequency, that is, it has a large capacitance.

This abnormal circuit 530L has a configuration in which a CR circuit constituted by a resistor 536 and a capacitor 534 in the abnormal circuit 530C shown in Fig. 55 is replaced by an LR circuit composed of an inductor 537 and a resistor 536. [

60 is a vector diagram showing the relationship between the input / output voltage of the error circuit 530L and the voltage appearing in the inductor and the like. The phase shift amount phi 12 of the abnormal circuit 530L shown in the diagram is T ₂ (the inductance of the inductor 137 is L, and the resistance value of the variable resistor 536 is R, the time constant of the LR circuit constituted by the inductor 537 and the variable resistor 536 is T ₂ = L / R) is equal to? 2 shown in the above-mentioned equation (7).

As described above, each of the abnormal circuit 510L shown in Fig. 57 and the abnormal circuit 530L shown in Fig. 59 is equivalent to the abnormal circuits 510C and 530C shown in Fig. 53 or 55, The abnormal circuit 510C of FIG. 57 can be replaced with the abnormal circuit 510L shown in FIG. 57, and the abnormal circuit 530C of the succeeding stage can be replaced with the abnormal circuit 530L shown in FIG. In the case where both of the two abnormal circuits 510C and 530C are replaced with the abnormal circuits 510L and 530L, it is easy to increase the frequency of the tuning frequency by integrating the entire circuit.

Even when one of the two abnormal circuits 510C and 530C is replaced by the abnormal circuit 510L or 530L, if the inductor constituting the LR circuit is included or the entire tuning circuit excluding the inductor is integrated, Thereby preventing fluctuation of the tuning frequency. So-called temperature compensation becomes possible.

[Fourteenth modification of the tuning circuit]

Although the tuning circuit 1J shown in Fig. 52 includes two or more circuits differing from each other in the ideal direction, a tuning circuit can be formed by combining two or more circuits having basically the same configuration.

61 is a circuit diagram showing another configuration of the tuning circuit. 1K shows a phase inversion circuit 580 for inverting and outputting the phase of an input AC signal and a phase inversion circuit 580 for shifting the phases of the AC signals inputted thereto by a predetermined amount, And the resistors 162 and 164 provided at the rear ends of the abnormal circuit 510C 'at the rear stage, the feedback resistor 170, and the input resistor 174, respectively, so that the divided output of the voltage divider circuit 160 (Feedback signal) and a signal (input signal) input to the input terminal 190 at a predetermined ratio.

The detailed configuration of the two abnormal circuits 510C and the phase relationship between the input and output signals are as described with reference to FIGS. 53 and 54. The abnormal circuit 510C 'in the subsequent stage includes a variable resistor 516 in the abnormal circuit 510C in the preceding stage, And the like. Therefore, at a predetermined frequency, the sum of the amount of phase shift by the entirety of the two more circuits 510C and 510C 'becomes 180. [

The phase inverting circuit 580 connected to the previous stage of the two abnormal circuits 510C and 510C 'inverts the phase of the input AC signal. For example, the phase inverting circuit 580 inverts the phases of the emitter ground circuit, the source ground circuit, .

In this manner, the phase is shifted 180 degrees by two more circuits 510C and 510C 'at a predetermined frequency, the phase is inverted by the phase inversion circuit 580 connected to the preceding stage, and the phase shift amount The total is 360.

The output of the error circuit 510C 'at the subsequent stage is taken out from the output terminal 192 as an output of the 1K circuit and the output of the error circuit 510C' at the subsequent stage is input to the phase inversion circuit 580 through the feedback resistor 170 And is returned to the input side. Then, the feedback signal is added to the signal input through the input resistor 174, and the added signal is input to the phase inversion circuit 580.

In this way, the output of the voltage divider circuit 160 is fed back to the input side of the phase inverter circuit 580 through the feedback resistor 170, the signal inputted through the input resistor 174 is added to the feedback signal, and the gain of the two more circuits 510C is adjusted, It is possible to perform the tuning operation and the amplifying operation similarly to 1J shown in Fig. 52 by compensating for the loss occurring at the connection of the circuit 160 or the feedback resistor 170 and the input resistor 174. Instead of adjusting the gains of the error circuits 510C and 510C ', the gain of the phase inversion circuit 580 may be adjusted.

When the amplifying operation is not necessary in the inquiry circuit 1K shown in FIG. 61, the voltage dividing circuit 160 may be omitted and the output of the abnormal circuit 510C 'may be directly fed back to the previous stage. Alternatively, the resistance value of the resistor 162 in the voltage dividing circuit 160 may be set to an extremely small value, and the division ratio may be set to 1.

[Modification 15 of the tuning circuit]

Fig. 62 is a circuit diagram showing another modified example of the tuning circuit. Contrary to Fig. 55, the tuning circuit includes the following error circuit 530C shown in Fig.

62 includes two abnormal circuits 530C 'and 530C for performing a total 180 占 phase shift at a predetermined frequency by shifting the phases of AC signals inputted thereto by a predetermined amount, (Feedback signal) output from the phase inversion circuit 580 and a signal (input signal) input to the input terminal 190 through the phase inversion circuit 580 for further inverting the phase of the output signal of the phase inversion circuit 530C, the feedback resistor 170 and the input resistor 174, ) At a predetermined ratio.

55 and 56. For example, when the time constant of the CR circuit constituted by the capacitor 534 and the variable resistor 536 is T ₂ , the phase relationship between the detailed configuration and the input / The phase shift amount? 10 at the frequency of 1 / T ₂ becomes 90 in the clockwise or counterclockwise direction (phase slowing direction).

In addition, the former stage anomaly circuit 530C 'has the same basic configuration as the above-mentioned latter stage anomaly circuit 530C, and has a configuration in which the resistor 536 in the abnormal circuit 530C is replaced with a variable resistor 535 whose resistance value can be changed by a control voltage applied from the outside I have. Therefore, for example, when the time constant of the CR circuit constituted by the variable resistor 535 and the capacitor 534 is T ₂ , the phase shift amount? 10 'at the frequency of? = 1 / T _{2 corresponds to} the clockwise or counterclockwise 90. Therefore, at a predetermined frequency, the sum of the amount of phase shift by the entirety of two more circuits 530C 'and 530C is 180. [

530C ', and 530C, the phase is shifted by 180.degree. By two abnormal circuits 530C' and 530C at a predetermined frequency, and the phase is inverted by the phase inversion circuit 580 connected to the preceding stage, And the sum of the amounts of phase shift by the entirety of these three circuits is 360. [

Therefore, in the above-described circuit 1L, the output of the voltage dividing circuit 160 is fed back to the input side of the phase inversion circuit 580 through the feedback resistor 170, the signal inputted through the input resistor 174 is added to the feedback signal, The gain of the feedback loop is adjusted to compensate for the loss or the like occurring at the junction of the feedback resistor 170 and the input resistor 174, and the loop gain of the feedback loop is set to 1 or less. As a result, It is possible to perform the tuning operation and the amplifying operation.

61 and FIG. 62, the abnormal circuits including the CR circuit therein are cascade-connected, but the LR circuit may be included in both of the abnormal circuits.

Concretely, two abnormal circuits 510C in 1K shown in Fig. 61 are connected to the abnormal circuit 510L shown in Fig. 57 or the abnormal circuit 510C 'in the subsequent stage is connected to the variable resistor 516 in the abnormal circuit 510L shown in Fig. 57 Instead, the resistance value may be replaced with an ideal circuit 510L 'using a resistor 515 having a fixed resistance value. Alternatively, both of the two abnormal circuits 510C and 510C 'may be replaced with the abnormal circuits 510L and 510L' described above.

Alternatively, in the reference circuit 1L shown in FIG. 62, the following circuit 530C 'may be replaced by an abnormal circuit 530L' using a variable resistor 535 instead of the resistor 536 in the abnormal circuit 530L shown in FIG. 59, Can be replaced with the abnormal circuit 530L shown in Fig. Alternatively, both of the two abnormal circuits 530C and 530C 'may be replaced with the abnormal circuits 530L and 530L' described above.

However, when the preceding stage circuit 510C shown in FIG. 61 is replaced with the abnormal circuit 510L shown in FIG. 57, or when the preceding stage circuit 530C 'shown in FIG. 62 is replaced with the resistance of the abnormal circuit 530L shown in FIG. 59 In the case of replacing the variable resistor with the abnormal circuit changed, the direction of the change of the phase shift amount when the gate voltage of the FET forming the variable resistor is changed is opposite to that of FIG. 13, It is possible to change the connection between the output terminal and the tri-state buffers 700 and 702 or change the connection lines of the output terminals of the two tri-state buffers 700 and 702 so that the frequency control circuit 2 changes the direction And the direction of the change of the tuning frequency of the tuning circuit is opposite.

When the amplifying operation is not necessary in the circuits 1K and 1L shown in FIGS. 61 and 62, the voltage dividing circuit 160 may be omitted, and the output of the abnormal circuit 510C 'may be directly fed back to the previous stage. Alternatively, the resistance value of the resistor 162 in the voltage dividing circuit 160 may be set to a small value at the extreme end, and the division ratio may be set to 1.

However, in the above-described circuits, 1J, 1K, and 1L are configured to include a non-inverting circuit, two or more phase shifting circuits, and two or more phase shifting circuits. A predetermined tuning operation is performed by setting the total phase shift amount at 360. for a predetermined frequency. Therefore, considering only the amount of phase shift, there is a certain degree of freedom in which one of the two or more circuits is to be used in the preceding stage or in which order the three circuits are connected, and the order of connection can be determined if necessary.

[J. Other Modifications]

However, various tuning mechanisms shown in Fig. 1 and the like may be configured such that variable resistors 116 and the like in one of the abnormal circuits constituting the tuning circuit are formed by using junction-type FETs, but variable resistors may be formed by other elements .

63 is a circuit diagram showing a configuration in which the variable resistor 116 in the abnormal circuit 110C shown in Fig. 3 is replaced with a variable resistor 126 formed of a MOS type FET. Thus, the channel formed in the source and drain of the MOS type FET can be used as a resistor. In this case, since the channel resistance of the FET can be changed by changing the control voltage applied to the gate, the tuning frequency of the tuning circuit 1 can be arbitrarily changed within a certain range.

Although the tuning frequency is changed by changing the resistance value of the variable resistor 116 inside the abnormal circuit at the preceding stage in each of the above-mentioned tuning circuits, the fixed resistance of the variable resistor is replaced with the resistance 136 May be replaced with a variable resistor formed by a junction type or MOS type FET so that the entire tuning frequency may be changed by changing the control voltage applied to the gate of this FET. 13, the connection between the two output terminals of the flip-flop 63 and the tri-state buffers 700 and 702 is changed, or when the two tri-state buffers 700, It is necessary to change the connection line of the output terminal of the tuning circuit 702 so that the direction of the change of the control voltage applied to the tuning circuit 1 and the direction of the change of the tuning frequency of the tuning circuit 1 are reversed in the frequency control circuit 2 .

Alternatively, a variable resistor may be provided in each of the abnormal circuits in the front stage and the rear stage.

In this case, there is an advantage that the variation amount of the entire tuning frequency, that is, the variable range of the tuning frequency can be set to be large in order to simultaneously vary the phase shift amounts of both of the error circuits. Further, in Fig. 2 or the like, two or more circuits in the tuning circuit may be connected back and forth.

The above-described abnormal circuit 110C changes the total tuning frequency by changing the resistance value of the variable resistor 116 or the like connected in series with the capacitor 114 or the like to change the amount of phase shift. However, by changing the capacitance of the capacitor 114 or the like, The tuning frequency may be changed.

For example, it is possible to change the tuning frequency by changing the amount of phase shift by each of the above-mentioned abnormal circuits by replacing the capacitor 114 or the like included in at least one of the two or more circuits with a variable capacitance element. More specifically, the above-described variable capacitance element can be formed by a variable capacitance diode whose reverse bias voltage applied between the anode and the cathode can be changed or by a FET whose gate capacitance can be changed by the gate voltage. To change the reverse bias voltage to be applied to the above-mentioned variable capacitance element, it is sufficient to connect a capacitor for blocking direct current to this variable capacitance element in series.

2 or the like, the variable resistor 116 of the abnormal circuit 110C is formed by the FET, but the variable resistor 116 may be formed using an element other than the FET. For example, FIG. 64 is a circuit diagram showing an example in which elements other than FETs are used as variable resistors in the error circuit 110C or 130C. In the same figure, one of the abnormal circuits 110C 'included in the inquiry line 1 is configured to include the CdS photo coupler, and a voltage synthesizing circuit 7E included in the frequency control circuit 2 and a control voltage And a voltage-current conversion circuit 200 for converting the control current into a control current.

The abnormal circuit 110C 'shown in FIG. 64 has a configuration in which the variable resistor 116 formed by using the FET in the abnormal circuit 110C shown in FIG. 3 is replaced with a CdS photo sensor and a CdS photo-clave 177 which is a light-emitting diode. Since the CdS photo sensor included in the photo frame 177 has a characteristic that the resistance value becomes smaller as the amount of light emitted from the light emitting diode increases, the CdS photo frame 177 can be used as a variable resistor whose resistance value can be changed according to an external control current .

The voltage synthesizing circuit 7E shown in Fig. 64 has a constitution in which the voltage synthesizing circuit 7 shown in Fig. 13 is partially modified, and the bias circuit composed of the variable resistor 706 and the resistor 722 in the voltage synthesizing circuit 7 of Fig. 13 is removed There is a difference.

The voltage-to-current conversion circuit 200 shown in FIG. 64 is configured so that the control voltage, which is the output of the voltage composition circuit 7E, is connected to the operational amplifier 204 input to the inverting input terminal through the resistor 202, 206, &lt; / RTI &gt;

In the operational amplifier 204, the light emitting diode in the photo-coupler 177 is connected between the output terminal and the inverting input terminal, and the non-inverting input terminal is grounded. Therefore, when the output voltage (control voltage) of the voltage synthesizing circuit 7E is determined, a predetermined current determined by the resistance ratio of the resistor 202 and the variable resistor 206 flows in the light emitting diode in the photocapacitor 177, and CdS The photosensor has a certain resistance value depending on the light emission amount of the light emitting diode.

Therefore, by dropping the output voltage of the voltage amplifying circuit 7E, the current value flowing through the light emitting diode is reduced, the light emission amount is reduced, the resistance value of the CdS photosensor is increased, and the tuning frequency of the tuning circuit 1 is lowered. On the other hand, by increasing the output voltage of the voltage synthesizing circuit 7E, the current value flowing through the light emitting diode also becomes large, so that the amount of light emission increases, and the resistance value of the CdS photosensor becomes low and the tuning frequency of the tuning circuit 1 becomes high. This relationship is the same as the relation between the variable resistor formed by the above-described FET and the control voltage, and the tuning frequency of the tuning circuit 1 can be matched to the frequency of the input signal by the same control procedure as a whole.

As described above, the tuning circuit for realizing the tuning mechanism of the above-described embodiment can also be constituted by using the photo coupler 177 as a variable resistor. When the photo coupler 177 is used as a variable resistor, a constant resistance value can always be obtained irrespective of the voltage across the variable resistor or the like, so that there is an advantage that a tuning output with small distortion can be easily obtained. However, since it is not possible to integrate the whole of the inquiry furnace 1 including the photo cabinets 177 on the semiconductor substrate, only the photo cabinets 177 are connected using a connecting line or the like.

In the above-described embodiment, a high stability can be achieved by configuring the 1-11E by the ideal circuit 110C using an op-amp. However, in the case of using the circuit with the abnormal circuit 110C of the present embodiment, Since the voltage gain is not required to be such high performance, a differential amplifier having a predetermined amplification degree may be used in place of the op-amp of each ideal circuit.

Fig. 65 is a circuit diagram of a portion of an op-amp structure necessary for operation of the abnormal circuit, and the whole circuit operates as a differential amplifier having a predetermined amplification degree. The differential amplifier shown in the figure includes a differential input stage 100 configured by FETs, a constant current 102 sending a constant current to the differential input stages 100, a bias circuit 104 providing a predetermined bias to the constant current circuit 102, and an output amplifier 106 connected to the differential input stage 100 Respectively. It is possible to omit the multi-stage amplifying circuit for obtaining the voltage gain included in the actual op-amp as shown in the diagram, to simplify the configuration of the differential amplifier and to make it wider. Since the upper limit of the operating frequency can be increased by simplifying the circuit as described above, the upper limit of the tuning frequency of the tuning circuit 1 constructed using the differential amplifier can be increased by that minute.

The present invention is not limited to the above-described various embodiments, and various modifications can be made within the scope of the present invention.

2, for example, the input resistance 174 is used as the feedback impedance 170 as the feedback impedance element, but the input resistance 174 is used as the feedback impedance 170. However, The feedback impedance element and the input impedance element may be formed by a capacitor instead of a resistor or a resistor or a capacitor may be combined so that the ratio of the real part and the imaginary part to the impedance can be adjusted simultaneously.

At least one of the feedback resistor 170 and the input resistor 114 may be constituted by a variable resistor and the tuning bandwidth in the tuning amplifier 1 or the like may be varied.

In the abnormal circuit 110C shown in Fig. 2, the variable resistor 116 is composed of one FET, but a P-channel FET and an n-channel FET may be connected in parallel to constitute one variable resistor. By constructing the variable resistor by combining the two FETs as described above, it is possible to improve the nonlinear region of the FET, so that the stress of the tuning output can be reduced.

As described above, the tuning control system of the present invention can reliably match the tuning frequency to the frequency of the input signal in order to feedback-control the tuning frequency of the tuning circuit so that either the frequency of the input signal or the tuning frequency of the tuning circuit disappears. Therefore, when the entire tuning mechanism is integrated, the tuning characteristics do not change even if the frequency characteristics vary from chip to chip. Even if the element constants of the elements for determining the tuning frequency fluctuate due to temperature or the like, the tuning frequency does not fluctuate and is suitable for integration.

Claims (61)

The output of two or more crossover-connected crossover-connected all-pass circuits and the output of the above-mentioned abnormal circuit as a feedback signal is fed back to the input side of the above-mentioned abnormal circuit at the previous stage, and the feedback signal and the input signal are added to the above- A tuning circuit including an adding circuit for inputting only a signal in the vicinity of a predetermined frequency, A frequency control circuit for matching a tuning frequency of the tuning circuit with a frequency of an input signal of the tuning circuit based on a phase difference between input and output signals of the tuning circuit when a signal having a frequency near the predetermined frequency is inputted to the tuning circuit; Wow, And a tuning control method The method according to claim 1, Wherein at least one of the two abnormal circuits included in the tuning circuit is capable of changing the phase shift amount in accordance with the control signal output from the frequency control circuit and the frequency of the signal input to the tuning circuit and the tuning frequency of the tuning circuit The tuning frequency is made to coincide with the frequency of the input signal of the tuning circuit by changing at least one phase shift amount of the two or more circuits. 3. The method of claim 2, The frequency control circuit includes a synchronous rectification circuit for performing synchronous rectification on an input signal of the tuning circuit based on a reference signal synchronized with an output signal of the tuning circuit, And a control signal generation circuit for performing phase difference detection between the input and output signals of the tuning circuit based on the output of the synchronous rectification circuit and outputting a control signal by changing the tuning frequency of the tuning circuit in a direction in which the phase difference is not present A tuning control method The method of claim 3, Wherein the synchronous rectification circuit includes a reference signal generation circuit for outputting a reference signal synchronized with an output signal of the tuning circuit and a switch for passing or blocking an input signal of the tuning circuit in synchronization with the reference signal And a tuning control method. 5. The method of claim 4, Wherein the reference signal generating circuit includes a voltage comparator for comparing a voltage level of an output signal of the tuning circuit with a predetermined voltage value to output a rectangular wave according to the comparison result as the reference signal, Wherein the tuning control circuit causes the two voltage levels of the square wave to be in an on state and an off state, respectively, and to pass an input signal of the tuning circuit in an on state. The method of claim 3, Wherein the control signal generation circuit comprises: a pulse conversion circuit for outputting a signal having a pulse width corresponding to a phase difference between input / output signals of the tuning circuit based on an output of the synchronous rectification circuit; A polarity discriminating circuit for discriminating the polarity of the phase difference; and a control circuit for generating a voltage component proportional to the pulse width of the signal outputted from the pulse converting circuit, And a voltage synthesizing circuit for synthesizing a control voltage by adding or subtracting the voltage from the voltage synthesizing circuit, wherein the control voltage synthesized by the voltage synthesizing circuit is output as the control signal. The method according to claim 6, Wherein the pulse conversion circuit includes a voltage comparator and outputs a signal having a pulse width based on the comparison result by comparing the voltage level of the synchronous rectified output outputted from the synchronous rectification circuit with a predetermined voltage value Tuning control method. The method according to claim 6, Wherein the polarity determination circuit determines the polarity of the phase difference based on the reference signal at a timing synchronized with the rise or fall of the output signal of the pulse conversion circuit. 9. The method of claim 8, Wherein the polarity determination circuit includes two stages of cascade-connected flip-flops, and maintains a logic level corresponding to the reference signal in synchronization with the rise or fall of the output signal of the pulse conversion circuit. 10. The method of claim 9, Wherein the polarity determination circuit further includes a delay element that delays the output signal of the pulse conversion circuit by a predetermined time and determines the polarity of the phase difference at a timing delayed by the predetermined time from the rising or falling of the output signal of the pulse conversion circuit And a tuning control method. The method according to claim 6, Wherein the voltage synthesizing circuit includes two switching means for passing or blocking the output signal of the pulse conversion circuit based on a result of the determination by the polarity determination circuit and a pulse generating circuit for generating a pulse of a signal output from either one of the two switching means And voltage adding means for adding the voltage by the width and subtracting the voltage by the pulse width of the signal output from any of the other. 12. The method of claim 11, Wherein each of the two opening and closing means includes a first input terminal, a second input terminal, and an output terminal, a signal indicating a result of determination by the polarity determination circuit is input to the first input terminal, And a signal having a logic level equal to or different from that of the second input terminal is output at the output terminal by the voltage level of the first input terminal Tuning control method. 13. The method of claim 12, Wherein each of the two switching means comprises one of a tri-state buffer, an analog switch, and a logic gate. 12. The method of claim 11, Wherein the voltage adding means includes a differential circuit for calculating a difference between the output voltages of the two switching means. 15. The method of claim 14, Wherein the voltage addition means further includes a smoothing circuit for removing high frequency components of the output of the differential circuit. The method of claim 3, Pass filter is connected to the rear end of the synchronous rectification circuit, and when the AM wave is inputted to the tuning circuit, the AM detection signal is outputted from the low-pass filter. The method of claim 3, Wherein the frequency control circuit includes a high frequency elimination circuit for removing a frequency component of a predetermined frequency or more included in a signal correlated with the control signal generated by the control signal generation circuit, and when the FM wave is input to the tuning circuit, And outputs the FM detection signal in the elimination circuit. The method of claim 3, At least one of the two abnormal circuits included in the tuning circuit is a differential amplifier in which one end of a first resistor is connected to an inverting input terminal and an AC signal is inputted through the first resistor, A second resistor connected between the inverting input terminal of the differential amplifier and the inverting input terminal of the differential amplifier, and a reactance element and a third resistor by a capacitor or an inductor, the time constant being changeable by the control signal, And a series circuit connected to the other end of the resistor of the differential amplifier, wherein a connection portion of the third resistor and the reactance element is connected to a non-inverting input terminal of the differential amplifier. 19. The method of claim 18, Wherein the tuning circuit includes a non-inverting circuit that outputs the input AC signal without changing the phase of the input AC signal, the non-inverting circuit is inserted into a part of the feedback loop formed by the two cascaded circuits, Wherein the circuit passes only the signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 360. by the entirety of the two or more cascaded circuits connected in cascade. 19. The method of claim 18, Wherein the tuning circuit is provided with a phase inversion circuit for inverting and outputting the phase of the input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two cascaded circuits, Only the signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 180. is passed through all of the two or more cascaded circuits connected in cascade. 19. The method of claim 18, And a flow circuit by a transistor is inserted in a front end of the two or more cascaded circuits. 19. The method of claim 18, Wherein a voltage dividing circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, and the tuning circuit outputs an AC signal input to the voltage dividing circuit as a tuning signal. 19. The method of claim 18, At least one of the resistors constituting the series circuit in the cascade-connected two or more cascaded circuits is formed as a variable resistor, and the tuning frequency of the tuning circuit is varied by changing the resistance value of the variable resistor in accordance with the voltage level of the control signal The tuning control method comprising: 19. The method of claim 18, Wherein the differential amplifier is an operational amplifier. 19. The method of claim 18, Wherein the component parts are integrally formed on a semiconductor substrate. 3. The method of claim 2, At least one of the two abnormal circuits included in the tuning circuit includes a differential amplifier in which one end of a first resistor is connected to an inverting input terminal and an AC signal is input through the first resistor, A second resistor connected between an output terminal of the first voltage divider circuit and an inverting input terminal of the differential amplifier; a reactance element formed by a capacitor or an inductor and a third resistor; And a series circuit connected to the other end of the first resistor, the time constant being changeable by the control signal, and the connection of the third resistor and the reactance element is connected to the non-inverting input terminal of the differential amplifier Wherein the tuning control method comprises: 27. The method of claim 26, Wherein the non-inverting circuit is inserted in a part of a feedback loop formed by the two cascaded circuits, and the non-inverting circuit is inserted into a part of the feedback loop formed by the two cascade- Wherein the tuning circuit passes only a signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 360. due to all of the two or more cascaded circuits connected in cascade. 27. The method of claim 26, Wherein the tuning circuit is equipped with a phase inversion circuit for inverting and outputting the phase of an input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two cascaded circuits, Only the signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 180. is passed through all of the two or more cascaded circuits connected in cascade. 27. The method of claim 26, And a flow circuit by a transistor is inserted in a front end of the two or more cascaded circuits. 27. The method of claim 26, The second voltage dividing circuit is inserted into a part of the feedback loop formed by the two cascade-connected cascaded circuits, and the tuning circuit outputs the alternating signal inputted to the second voltage dividing circuit as a tuning signal Tuning control method. 27. The method of claim 26, Wherein at least one of the resistors constituting the series circuit in the cascade-connected two or more cascaded circuits is formed by a variable resistor and the frequency of the tuning circuit is varied by changing the resistance value of the variable resistor in accordance with the voltage level of the control signal. And the tuning control method. 27. The method of claim 26, Wherein the differential amplifier is an operational amplifier. 27. The method of claim 26, And the component parts are integrally formed on the semiconductor substrate. 3. The method of claim 2, At least one of the two abnormal circuits included in the tuning circuit includes a differential amplifier in which one end of a first resistor is connected to an inverting input terminal and an alternating signal is input through the first resistor, A second resistor connected between the input terminal and the output terminal, a third resistor having one end connected to the inverting input terminal of the differential amplifier and the other end grounded, a reactance capacitor connected to the capacitor or the inductor, And a series circuit connected to the other end of the first resistor, the time constant being changeable by the control signal, and the connection of the fourth resistor and the reactance element is connected to the non-inverting input terminal And the tuning control method. 35. The method of claim 34, Wherein the tuning circuit is equipped with a non-inverting circuit for outputting the input AC signal without changing its phase, the non-inverting circuit being inserted in a part of the feedback loop formed by the two cascaded circuits, Wherein the circuit passes only the signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 360. by the entirety of the two or more cascaded circuits connected in cascade. 35. The method of claim 34, Wherein the tuning circuit is provided with a phase inversion circuit for inverting and outputting the phase of an input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, Passes only a signal in the vicinity of a frequency at which the sum of the amounts of phase shift is 180. by the entirety of two or more circuits connected in cascade. 35. The method of claim 34, And a flow circuit is inserted by a transistor at the front end of the two or more cascaded circuits. 35. The method of claim 34, Wherein a partial voltage circuit is inserted into a part of a feedback loop formed by the two or more cascade-connected cascaded circuits, and the tuning circuit outputs an alternating signal inputted to the voltage dividing circuit as a tuning signal. 35. The method of claim 34, At least one of the sub circuits constituting the series circuit in the cascade-connected two or more circuits is formed by a variable resistor, and the tuning frequency of the tuning circuit is varied by changing the resistance value of the variable resistor in accordance with the voltage level of the control signal The tuning control method comprising: 35. The method of claim 34, Wherein the differential amplifier is an operational amplifier. 35. The method of claim 34, And the component parts are integrally formed on the semiconductor substrate. 3. The method of claim 2, Wherein the non-inverting circuit is inserted in a part of a feedback loop formed by the two cascaded circuits, and the non-inverting circuit is inserted into a part of the feedback loop formed by the two cascade- At least one of the number of the abnormal circuits includes conversion means for converting an input AC signal into an in-phase and reverse-phase AC signals and outputting the inverted AC signal and a reactance element by a capacitor or an inductor and a first resistor, And a synthesizing means for synthesizing one of the AC signals converted by the converting means through one end of the series circuit and the other AC signal through the other end of the series circuit . 43. The method of claim 42, Wherein the tuning circuit passes only a signal in the vicinity of a frequency at which the sum of the amounts of phase shift is 360. by the entirety of the two or more cascaded circuits connected in cascade. 43. The method of claim 42, And a voltage dividing circuit is inserted in a part of the feedback loops formed by the cascade-connected two-phase circuit and the non-inverting circuit, and the tuning circuit outputs an AC signal input to the voltage dividing circuit as a tuning signal Tuning control method. 43. The method of claim 42, Wherein the switching means in the two or more circuits includes a transistor and a second resistor having substantially the same resistance value is connected to the source and the drain or the emitter and the collector of the transistor, And the reactance element and the first resistor constituting the series circuit are connected between a source, a drain, an emitter, and a collector of the transistor. 43. The method of claim 42, At least one of the first resistors in the cascade-connected two or more circuits is formed by a variable resistor, and the resistance value of the variable resistor is changed in accordance with the voltage level of the control signal so that the tuning frequency of the tuning circuit is varied And the tuning control method. 43. The method of claim 42, Wherein the component parts are integrally formed on a semiconductor substrate. 3. The method of claim 2, Wherein the tuning circuit is provided with a phase inversion circuit for inverting and outputting the phase of an input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, At least one of the circuits includes conversion means for converting the input AC signal into an in-phase and reverse-phase AC signal and outputting the converted AC signal, a reactance element formed by a capacitor or an inductor and a first resistor, And a synthesizing means for synthesizing one AC signal converted by said converting means through one end of said series circuit and the other AC signal through another end of said series circuit, Control method. 49. The method of claim 48, Wherein the tuning circuit passes only a signal in the vicinity of a frequency at which the sum of the amounts of phase shift is 180. The tuning control method according to claim 1, 49. The method of claim 48, A voltage dividing circuit is inserted in a part of the feedback loop formed by the cascade-connected two-phase circuit and the phase inversion circuit, and the tuning circuit outputs the AC signal input to the voltage dividing circuit as a tuning signal Tuning control method. 49. The method of claim 48, Wherein said conversion means in said two more circuits connect a second resistor having substantially the same resistance value as the source and drain of said transistor or the emitter and collector of said transistor, And the reactance element constituting the series circuit between the emitter of the transistor and the emitter of the transistor, and the resistor are connected to each other. 49. The method of claim 48, At least one of the first resistors in the cascade-connected two or more circuits is formed by a variable resistor and the tuning frequency of the tuning circuit is varied by changing the resistance value of the variable resistor in accordance with the voltage level of the control signal And a tuning control method. 49. The method of claim 48, And the component parts are integrally formed on the semiconductor substrate. 3. The method of claim 2, At least one of the two abnormal circuits included in the tuning circuit includes a first series circuit formed by first and second resistors having substantially the same resistance value and a second series circuit including a reactance element by a capacitor or an inductor, And a second series circuit which is constituted by the first series circuit and the second series circuit, and a second series circuit constituted by the first series circuit and the second series circuit, And a differential amplifier for amplifying and outputting the amplified difference signal with an amplification degree of a difference between a potential of a connection point of the resistor and an output of the differential amplifier, wherein the AC signal is input to one end of each of the first and second series circuits, Wherein the time constant is changeable by the tuning control method. 55. The method of claim 54, Wherein the tuning circuit is equipped with a non-inverting circuit for outputting the input AC signal without changing its phase, the non-inverting circuit being inserted in a part of the feedback loop formed by the two cascaded circuits, Wherein the circuit passes only the signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 360. by the entirety of the two or more cascaded circuits connected in cascade. 55. The method of claim 54, Wherein the tuning circuit is provided with a phase inversion circuit for inverting and outputting the phase of an input AC signal and the phase inversion circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, Passes only a signal in the vicinity of the frequency at which the sum of the amounts of phase shift is 180. due to the entirety of two or more cascaded circuits connected in cascade. 55. The method of claim 54, Wherein a voltage dividing circuit is inserted in a part of a feedback loop formed by the two or more cascaded circuits, and the tuning circuit outputs an AC signal input to the voltage dividing circuit as a tuning signal. 55. The method of claim 54, Wherein at least one of the resistors constituting the first and second series circuits in the cascade-connected two or more circuits is formed by a variable resistor, and the resistance value of the variable resistor is changed in accordance with the voltage level of the control signal, And the tuning frequency of the tuning circuit is varied. 55. The method of claim 54, And the component parts are integrally formed on the semiconductor substrate. 3. The method of claim 2, Wherein the tuning circuit includes an input impedance element in which the input signal is input at one end and a feedback impedance element in which a feedback signal is input at one end, and the addition circuit adds a signal at the other end of the input impedance element and a feedback signal at the other end And a signal of &lt; RTI ID = 0.0 &gt; 1, &lt; / RTI &gt; 64. The method of claim 60, Wherein the bandwidth of the tuning circuit is changed by changing the ratio of the element constants of the input impedance element and the feedback impedance element.