KR19990029445A - Emitter-coupled logic circuit operating at high speed - Google Patents

Abstract

The output load of the emitter coupled logic (ECL) circuit is formed using a transistor and a resistor connected to each base and power supply of the transistor.

Description

Emitter-coupled logic circuit operating at high speed

FIELD OF THE INVENTION The present invention relates to emitter coupling logic (hereinafter referred to as ECL) circuits, and more particularly to improvements for ECL circuits that can operate at high speeds.

The implementation of a typical ECL circuit in terms of operating speed depends on the switching response of the transistors forming the ECL circuit and the time constant between the output resistance and the total load capacity connected to this output resistance. The total capacitance is the sum of the load capacitance connected to the output resistance and the parasitic capacitance associated with the wire and the resistance. Therefore, to increase the speed of the ECL circuit, it is necessary to consider the layout design to reduce the size of the transistor to improve the switching speed of the transistor, optimize the current and gain values to reduce the output load resistance, and reduce the parasitic capacitance.

The switching speed of a transistor is mainly influenced by three factors: switching response time, base response time and collector response time of the transistor. In the conventional ECL circuit, the switching response time and the base response time of the transistor can be reduced, but it is difficult to reduce the collector response time.

Accordingly, one object of the present invention is to provide an ECL circuit that can operate at high speed by reducing collector response time as well as base response time.

It is another object of the present invention to provide an ECL circuit which can increase the output amplitude level to a level that does not cause problems in practical terms without reducing the circuit gain.

According to an aspect of the present invention, there is provided a differential bipolar transistor having a base for receiving a different input signal, a load transistor respectively connected to a collector of the differential bipolar transistor, and a resistor connected to each base of the load transistor and a power supply. An emitter combining logic circuit is provided.

According to another aspect of the present invention, there is provided a differential bipolar transistor comprising a first transistor having a base adapted to receive a first input signal, a collector having an output signal generated therein, and a second transistor having a base to which a reference voltage is applied. Circuit; A third transistor having an emitter and a collector commonly connected to the emitter and the collector of the first transistor, and a base adapted to receive a second input signal; Load transistors connected to collectors of the first and second transistors, respectively; An emitter coupled logic circuit is provided that includes a resistor connected to each base of the load transistor and a power supply.

1 is a circuit diagram showing a conventional emitter coupling logic (ECL) OR circuit of a resistive load type.

2 is a circuit diagram showing a conventional ECL OR circuit with cascade connection.

3 is a circuit diagram showing an ECL circuit according to the first embodiment of the present invention.

4 is a circuit diagram showing an ECL circuit according to a second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10, 11, 100: OR circuit

20: back end circuit

30: master flip flop

40: slave flip-flop

Referring to Fig. 1, a conventional ECL circuit is first described for the purpose of facilitating the understanding of the present invention. In Fig. 1, the OR circuit 10 is formed of a conventional ECL circuit. The rear end 20 is connected to the OR circuit 10. OR circuit 10 includes input transistors Q1 and Q2. The bases of the input transistors Q1 and Q2 are connected to the input terminals In1 and In2, respectively. The ECL circuit 10 also includes an additional input transistor Q3 with a base connected to an additional input terminal In3. The emitters of transistors Q1, Q2 and Q3 are connected to a common constant current source CIS1. Thus, the differential amplifier is formed of input transistors Q1 and Q2 in combination with an additional input transistor Q3. The collectors of the input transistors Q1 and Q2 are connected to the load resistor R1 which is the output load, and the collector of the additional input transistor Q3 is connected to the load resistor R2 which is the output load. The collectors of the input transistors Q1 and Q2 are inverted output terminals ( ), And the collector of the additional input transistor Q3 is connected to the output terminal Out1. Capacitives C1 and C2 are output terminals (Out1) and inverted output terminals ( ) Is the parasitic capacitance with respect to the ground (GND) of the wiring connecting the circuit to the input of the circuit at the rear stage 20.

In the OR circuit 10, when the reference potential is applied to the additional input terminal In3 and the input signals of the ECL level are supplied to the input terminals In1 and In2, the logical sum OR of the input signals is output to the output terminal Out1. ) And reverse output terminal ( Is provided.

In terms of operating speed, the implementation of a typical ECL circuit and the OR circuit 10 of FIG. 1 depends on the switching response of the transistors forming the ECL circuit and the time constant between the output resistance and the total load capacitance connected to this output resistance. The total capacitance is the sum of the load capacitance connected to the output resistance and the parasitic capacitance associated with the wiring and the resistance. Therefore, to increase the speed of the ECL circuit, the layout design is considered to reduce the size of the transistor to improve the switching speed of the transistor, optimize the current and gain values to reduce the output load resistance, and reduce the parasitic capacitance.

Next, the factors influencing the switching speed of the ECL circuit are described. More specifically, the switching speed can be influenced by three factors:

1) Switching response time of transistor forming ECL circuit

The switching response time may be expressed as a forward transition time τf. The forward transition time (τf) has been greatly reduced by the reduction in device size.

2) Base response time (mirror response time)

The base response time can be expressed as G0 × rbb × Cjc, where G0 is the circuit gain, rbb is the resistance of the base resistor, and Cjc is the base collector junction capacitance. The rbb and Cjc values can be reduced by reducing the device size. However, the circuit gain G0 is a constant determined by the circuit structure. Therefore, it is necessary to reduce the circuit gain G0 in order to reduce the base response time.

3) Collector response time (resistance load response time)

The collector response time can be expressed as RL × Cjs + RL × CL, where RL is the load resistance value, Cjs is the collector semiconductor substrate junction capacitance value, and CL is the load capacity value. Cjs and CL values are reduced by reducing device size. However, the load resistance value RL is a constant determined by the circuit structure, such as the circuit gain G0 described in factor 2). It is necessary to design a circuit that reduces the load resistance (RL) to reduce the collector response time.

Referring to FIG. 2, the OR circuit 11 is described with the improved base response time described with respect to factor 2). In FIG. 2, the emitters of transistors Q1, Q2 and Q3 are connected to a common constant current source CIS1 as in FIG. 1. The differential amplifier is formed of input transistors Q1 and Q2 in combination with an additional input transistor Q3. The collectors of input transistors Q1 and Q2 are cascaded to transistor Q4. Similarly, the collector of the additional input transistor Q3 is cascaded to the transistor Q5. More specifically, the collectors of input transistors Q1 and Q2 are connected to the emitter of transistor Q4. The collector of the further input transistor Q3 is connected to the emitter of transistor Q5. The collectors of transistors Q4 and Q5 are connected to load resistors R1 and R2, respectively. The bases of the transistors Q4 and Q5 are connected to the bias terminal In4. Thus a constant bias is applied to the bases of transistors Q4 and Q5.

The circuit operation of the OR circuit 11 is similar to the circuit operation of the OR circuit 10 in FIG. 1. The logical sum OR of the input signals is the output terminal Out2 and the inverted output terminal when the reference potential is applied to the additional input terminal In3 and the input signals of the ECL level are supplied to the input terminals In1 and In2. Is provided. In this OR circuit 11, the circuit gain is calculated to be logical 1 for the power supply having the voltage level of Vcc from the input terminals In1 and In2. Therefore, the circuit gain G0 of the base response time (G0 × rbb × Cjc) described in 2) is smaller than the circuit gain of the OR circuit 10 in FIG. According to various simulations, it was found that the switching response time of the OR circuit 11 is improved by about 5-6% compared to the switching response time of the OR circuit 10 of FIG. 1.

The conventional ECL circuit can reduce the base response time and the switching response time of the transistor by reducing the size of the cascaded input differential transistor and the device. However, the conventional ECL circuit is difficult to reduce the collector response time. More specifically, it is necessary to maintain the load resistance value RL to a certain degree or more in order to secure the circuit gain G0. On the other hand, when the load resistance value RL is increased, the collector response speed becomes slow.

Referring to Fig. 3, an ECL circuit according to a first embodiment of the present invention executed in an OR circuit is described. In FIG. 3, elements and components similar to those of FIG. 1 are shown with the same reference numerals and symbols as in FIG. OR circuit 100 includes input transistors Q1 and Q2 and an additional input transistor Q3. The emitters of transistors Q1, Q2 and Q3 are connected to a common constant current source CIS1. Thus, the differential amplifier is formed of input transistors Q1 and Q2 in combination with an additional input transistor Q3. The collectors of transistors Q1, Q2 and Q3 are connected to the output load. The output load consists of transistors Q6 and Q7 and resistors R3 and R4 connected between the bases of the transistors Q6 and Q7 and the power supply having the voltage Vcc. The resistors R3 and R4 are formed of a material having a low parasitic capacitance such as thin film resistance and polysilicon. The circuit at the rear end 20 includes transistors Q8 and Q9 and a constant current source CIS2. As described above in connection with FIG. 1, the capacitances C1 and C2 are formed by the output terminal Out3 and the inverted output terminal of the OR circuit 100. ) Is the parasitic capacitance with respect to the ground (GND) of the wiring connecting the input to the circuit input of the rear stage 20.

Next, the basic operation of the OR circuit 100 is described. The logical sum OR of the input signals is the output terminal Out3 and the inverted output terminal when the reference potential is applied to the additional input terminal In3 and the input signals of the ECL level are supplied to the input terminals In1 and In2. Is provided. When both input terminals In1 and In2 receive the ECL low level signal, the additional input transistor Q3 is turned on while the input transistors Q1 and Q2 are off. As a result, the output terminal Out3 has a low level and the inverted output terminal ( ) Has a high level. This turns transistor Q8 on and transistor Q9 off in the circuit 20 on the subsequent stage. When both input terminals In1 and In2 receive the ECL high level signal, the additional input transistor Q3 is turned off while either or both of the input transistors Q1 and Q2 are on. As a result, the output terminal Out3 has a high level and the inverted output terminal ( ) Has a low level. This turns off the transistor Q8 and turns on the transistor Q9 in the circuit 20 of the subsequent stage.

If the high and low potentials of the DC level across the output terminal (Out3) are set to Vout (H) and Vout (L), respectively, the potential can be given by the following equation:

Vout (H) = Vcc-(kT / q) × ln (I2 / Is) ... (1)

Vout (L) = Vcc-(kT / q) × ln (I1 / Is)-R × I1 / h _FE ... (2)

Vcc is the voltage of the power supply, k is the hole constant, T is the absolute temperature, q is the charge of the electron, Is is the reverse saturation current, I1 is the emitter current through transistor Q7 while transistor Q3 is ON, I2 is the base current through transistor Q9 while transistor Q3 is OFF and transistor Q9 is ON, R is the resistance value of resistors R3 and R4, and h _FE is the direct current of transistor Q7. Amplification factor.

Therefore, based on equations (1) and (2), the DC output amplitude ΔVout (Dc) of the output terminal Out3 can be given as:

ΔVout (Dc) = Vout (H)-Vout (L)

= (kT / q) × ln (I1 / I2) + R × I1 / h _FE

= (kT / q) × lnh _FE + R × Ic / h _FE ... (3)

Ic is the current through the constant current source. The direct current amplification factor h _FE is assumed to be the same between transistors Q7 and Q9, and a relationship in which I1 = Ic and I2 = I1 / h _FE is used.

As evident in equation (3), the AC output amplitude ΔVout (Ac) of the output terminal Out3 receiving AC can be given by the following equation (4):

ΔVout (AC) = (kT / q) × lnh _re + R × I1 / h _fc ... (4)

h _fc is the AC current amplification factor of transistor Q7. The effective load resistance R (AC) at the time of receiving an AC signal can be given by the following equation (5):

R (AC) = α × (h _fe / h _FE ) × {re (Ic / 2) + R / h _fe } ... (5)

α is a constant and re (Ic / 2) is the emitter resistance of transistor Q7 when the collector current is Ic / 2.

As is apparent from Equation (4), when the AC current amplification factor h _fe is large, the AC output amplitude ΔVout (Ac) becomes large. Also, as is clear from equation (5), only the term (h _fe / h _FE ) is reduced for the AC output amplitude? Vout (AC). The second term of equation (5) is divided into h _fe . Therefore, the effective value R (AC) can be greatly reduced compared to the load resistance value RL of the conventional ECL circuit. Thus, the effective value of the load resistance is reduced. This reduces collector response time and improves performance throughout the ECL circuit in terms of speed. With this structure, the circuit gain becomes nonlinear in the switching response, so that the output signal can be distorted. However, in an application as a logic operation rather than an analog operation, designing a circuit to receive the output signal differentially can eliminate this problem.

Current through constant current source (Ic) is 0.5 mA, DC amplification factor (h _FE ) is 100, AC current amplification factor (h _fe ) is 20, resistance value (R) of resistors (R3 and R4) is 30 mA, and emitter Given that a concrete example is given by the resistance re (250 kV) of 104 kW, equations (3) and (5) are calculated by the following equations (3) 'and (5)', respectively:

ΔVout (DC) = 26 mV × ln (100) + 30 ㏀ × 0.5 mA / 100

= 270 mV ... (3) '

RL (AC) = 20/100 × (104 + 30 ㏀ / 20)

= 320 Ω ... (5) '

Α used in equation (5) is 1 in experience.

Meanwhile, the effective load resistance value of the conventional ECL circuit can be calculated as ΔVout (Dc) / Ic. Based on Formula (3) ', (DELTA) Vout (DC) / Ic = 270 mV / 0.5mA = 540 mA. Comparing this value with the result of equation (5) ', it is clear that the effective load resistance value R (AC) of the ECL circuit according to the present invention is 40% smaller than the effective load resistance value of the conventional ECL circuit.

The switching response of the ECL circuit according to the invention follows the process as described above. However, assuming that τf = 10 pS, rbb = 1㏀, Cjc = 10 fF, Cjs = 50 fF, and CL = 100 fF, typical values of the standard process, the transistor's switching response time (τf) and base response time (G0). × rbb × Cjc), and the collector response time (RL × Cjs + RL × CL) is given by

1) Transistor Switching Response Time (τf): 10 pS

2) Base response time (G0 × rbb × Cjc): 2.6 × 1 ㏀ × 10 fF = 26 Ps, where G0 = ΔVout (DC) / (4kT / q) = 270 mV / (4 × 26mV) = 2.6 Is calculated.

3) Collector response time (RL × Cjs + RL × CL): 320 Ω × (50fF + 100fF) = 48 pS, calculated using RL (AC) in equation (5) '. In a conventional ECL circuit, the collector response time is 80 pS. On the other hand, performance in terms of speed is improved by 40% in relation to the 40% reduction in the effective load resistance value R (AC), compared to the conventional ECL circuit.

The calculation results provide a total switching time of 84 pS (10 pS + 26 pS + 48 pS). On the other hand, the total switching time obtained in the conventional ECL circuit is 116 pS (10 pS + 26 pS + 80 pS). Thus, this embodiment improves the total switching time by 28% (84/116 = 0.72) compared to the conventional ECL circuit. As the device size is further reduced, collector response time accounts for a higher percentage of the total switching time. Therefore, the operation as a whole of the ECL circuit becomes faster.

Referring to Fig. 4, an ECL circuit according to a second embodiment of the present invention is described. In FIG. 4, the ECL circuit includes a master flip-flop 30 and a slave flip-flop 40. The master flip-flop 30 is provided between the differential transistors Q10 and Q11, the transistors Q6 and Q7 connected between the respective collectors of the transistors Q10 and Q11 and the power supply, and the respective bases and power supplies of the transistors Q6 and Q7. Resistors R3 and R4 connected to it, and a transistor Q12 connected between the common emitter of the transistors Q10 and Q11 and the constant current source CIS. The clock input terminal In6 is connected to the base of the transistor Q12. The bases of the differential transistors Q10 and Q11 are connected to the data input terminal In4 and the inverted data input terminal In5, respectively.

Slave flip-flop 40 includes differential transistors Q14 and Q15, a transistor Q13 connected between the common emitter of these transistors Q14 and Q15 and a constant current source CIS. The base of the transistor Q13 is connected to the inverted clock input terminal In7. The collectors of the differential transistors Q14 and Q15 have an output terminal (Q) and an inverted output terminal ( Respectively). The ECL circuit according to the second embodiment can be applied to a frequency division circuit that reduces the frequency of the high frequency signal to a level that can be processed by the digital signal processing circuit. Transistors Q6 and Q7 are connected between the power supply and the collector of differential transistors Q10 and Q11 as in the OR circuit 100 of FIG. Resistors R3 and R4 are connected between each base of transistors Q6 and Q7 and the power supply. With this configuration, the output response (Q) and the inversion output terminal (from the data input terminal In4 and the inverted data input terminal In5, respectively, are reduced by reducing not only the base response time but also the collector response time. It is possible to provide a high speed ECL circuit which further reduces the total switching time up to. In addition, it is possible to provide an ECL circuit in which the circuit gain is increased to increase the output amplitude of the ECL circuit to the highest level which is not a problem in practical use.

As described above, the ECL circuit of the present invention can reduce the effective load resistance value and increase the ECL circuit operation speed by using the transistors forming the output load of the circuit and the resistors connected to the base and the power supply of the transistor, respectively. Further, when switching to a high frequency signal, the execution of the circuit in terms of speed can be greatly improved by reducing the transistor alternating current amplification factor hfe and performing gain correction.

Claims (5)

Differential bipolar transistors each having a base for receiving different input signals; Load transistors each connected to a collector of the differential bipolar transistor; And And a resistor coupled to each base and power source of said load transistor. The method of claim 1, A base of the differential bipolar transistor receives an input signal and a signal obtained by inverting the input signal as an inverted input signal, respectively, and an output signal is generated from a collector of the differential bipolar transistor, And a bipolar transistor having a collector connected to the emitter of each differential bipolar transistor and a base adapted to receive a clock signal. 2. The emitter coupled logic circuit of claim 1 wherein the differential bipolar transistor and the load transistor are both NPN transistors. A differential bipolar transistor circuit comprising a first transistor having a base adapted to receive a first input signal and a collector for generating an output signal, and a second transistor having a base to which a reference voltage is applied; A third transistor having an emitter and a collector commonly connected to the emitter and the collector of the first transistor, and a base adapted to receive a second input signal; Load transistors connected to collectors of the first and second transistors, respectively; And And a resistor coupled to each base and power source of said load transistor. 5. The emitter coupling logic of claim 4 wherein both of the first to third transistors and the load transistors are NPN transistors.