CN1213224A - Emitter coupled logic circuit capable of operating at higher speed - Google Patents
Emitter coupled logic circuit capable of operating at higher speed Download PDFInfo
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- CN1213224A CN1213224A CN98118598A CN98118598A CN1213224A CN 1213224 A CN1213224 A CN 1213224A CN 98118598 A CN98118598 A CN 98118598A CN 98118598 A CN98118598 A CN 98118598A CN 1213224 A CN1213224 A CN 1213224A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
- H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element
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Abstract
The invention relates to a emitter coupled logic circuit comprising a differential bipolar transistor, each transistor is provided with a base for receiving different input signal, a load transistor connected to a collector of the differential bipolar transistor, and a resistance connected separately with the base of the load transistor and power source.
Description
The present invention relates to emitter coupled logic circuit (hereinafter referred to as ECL), more particularly, relate to improvement, it can be worked under more speed the ECL circuit.
With regard to operating rate, the performance of general ECL circuit depend on the transistorized switching response that constitutes the ECL circuit and output resistance and the total capacitance of the load that links to each other with output resistance between time constant.Total capacitance is the summation of the load capacitance that links to each other with output resistance and the parasitic capacitance relevant with resistance with lead-in wire.In order to improve the operating rate of ECL circuit, need improve its switching speed by dwindling transistorized size, optimized current and yield value, so that reduce the resistance value of output loading, and the problem of considering to reduce parasitic capacitance when carrying out global design.
Transistorized switching speed mainly is subjected to following factor affecting: transistorized switching response time, base stage response time and collector electrode response time.In the ECL of routine circuit, transistorized switching response time and base stage response time can shorten, but it is but very difficult to shorten the collector electrode response time.
Therefore, an object of the present invention is by not only shortening the base stage response time, but also shorten the collector electrode response time, a kind of ECL circuit that can work under more speed is provided.
Another object of the present invention provides a kind of like this ECL circuit, and in fact the output amplitude of this circuit is enhanced can accomplish and can not produce an amplitude of any problem, and can not reduce circuit gain.
According to an aspect of the present invention, provide a kind of emitter coupled logic (ECL) circuit, having comprised: the differential bipolar transistor npn npn, each transistor all has base stage, and the base stage of differential bipolar transistor npn npn receives mutually different input signal; The load transistor that links to each other with the collector electrode of differential bipolar transistor npn npn respectively; And the resistance that links to each other with power supply with the base stage of load transistor respectively.
According to a further aspect in the invention, a kind of emitter coupled logic (ECL) circuit is provided, comprise: differential bipolar transistor npn npn circuit, this circuit comprises the first transistor, its base stage is used for receiving first input signal and collector electrode produces output signal, and comprise that transistor seconds, its base stage apply a reference voltage; The 3rd transistor, its emitting stage links to each other with collector electrode with the emitting stage of the first transistor jointly with collector electrode, and base stage is used for receiving second input signal; The load transistor that links to each other with the first and second transistorized collector electrodes respectively; And the resistance that links to each other with power supply with the base stage of load transistor respectively.
Fig. 1 is emitter coupled (ECL) logic OR circuit of the conventional ohmic load type of expression;
Fig. 2 is ECL or the circuit that expression has the routine of cascade structure;
Fig. 3 is the ECL circuit of the expression first embodiment of the present invention; And
Fig. 4 is the ECL circuit of the expression second embodiment of the present invention.
For the ease of understanding the present invention, with reference to Fig. 1 conventional ECL circuit is described earlier.In Fig. 1, or circuit 10 is made of the ECL circuit of routine.Level 20 AND circuit 10 in back link to each other.Or circuit 10 comprises input transistors Q1 and Q2.The base stage of input transistors Q1 and Q2 links to each other with In2 with input In1 respectively.ECL circuit 10 also comprises additional input transistor Q3, and its base stage links to each other with additional input end In3.The emitting stage of transistor Q1, Q2 and Q3 links to each other with public constant-current source CIS1.Like this, formed a differential amplifier by input transistors Q1 and Q2 and additional input transistor Q3.The collector electrode of input transistors Q1 and Q2 links to each other with load resistance R1 as output loading, and the collector electrode of additional input transistor Q3 links to each other as the load resistance R2 of output loading.Input transistors Q1 also links to each other with reversed-phase output/Out1 (/ expression is anti-phase) with Q2, and the collector electrode of additional input transistor Q3 also links to each other with output Out1.Capacitor C 1 and C2 represent ground GND and with the parasitic capacitance between output Out1, reversed-phase output/Out1 and the lead that the circuit input of back level 20 links to each other.
Or circuit 10 in, when the input signal that is applied to additional input end In3 and is in the ECL level when reference potential is applied to input In1 and In2, the logic add of input signal (or) offer output Out1 and reversed-phase output/Out1.
Fig. 1's or circuit 10 and general ECL circuit operating rate depends on the transistorized switching response that constitutes the ECL circuit, and the time constant between the total capacitance of output resistance and the load that links to each other with output resistance.Total capacitance is the summation of the load capacitance that links to each other with output resistance and the parasitic capacitance relevant with resistance with lead-in wire.In order to improve the operating rate of ECL circuit, need improve its switching speed by dwindling transistorized size, optimized current and yield value, so that reduce the resistance value of output loading, and the problem of considering to reduce parasitic capacitance when carrying out global design.
The following describes the factor of the switching speed that influences the ECL circuit.Specifically, these factors comprise:
1) the transistorized switching response time of formation ECL circuit
The switching response time can be expressed as preceding bound-time τ f.Preceding bound-time τ f can shorten by reducing size of devices.
2) the base stage response time (image response time)
The base stage response time can be expressed as GO * rbb * Cjc, and wherein GO is a circuit gain, and rbb is the resistance value of base resistance, and Cjc is the capacitance of base collector junction capacitance.Value rbb and Cjc can reduce by reducing size of devices.Yet circuit gain GO is constant, and this is determined by circuit structure.Therefore, need reduce circuit gain GO and shorten the base stage response time.
3) the collector electrode response time (ohmic load response time)
The collector electrode response time can be expressed as RL * Cjs+RL * CL, and wherein RL is the load resistance value, and Cjs is the value of collector electrode Semiconductor substrate junction capacitance, and CL is the value of load capacitance.Value Cjs and CL can reduce by reducing size of devices.Yet load resistance value RL is constant, and this is determined by circuit structure, as schemes above-mentioned factor 2) in circuit gain GO.Therefore, need design circuit, reduce load resistance value RL and shorten the collector electrode response time.
With reference to Fig. 2, the above-mentioned factor 2 of having improved is described) in the base stage response time or circuit 11.In Fig. 2, the emitting stage of transistor Q1, Q2 and Q3 is same as in figure 1, links to each other with public constant-current source CIS1.Differential amplifier is made of input transistors Q1 and Q2 and additional input transistor Q3.The collector electrode of input transistors Q1 and Q2 and transistor Q4 cascade.Equally, the collector electrode of additional input transistor Q3 and transistor Q5 cascade.More particularly, the basis set electrode of input transistors Q1 and Q2 links to each other with the emitting stage of transistor Q4.The collector electrode of additional input transistor Q3 links to each other with the emitting stage of transistor Q5.The collector electrode of transistor Q4 and Q5 links to each other with R2 with load resistance R1 respectively.The base stage of transistor Q4 and Q5 links to each other with offset side In4.So constant biasing is applied on the base stage of transistor Q4 and Q5.
Circuit 11 to Fig. 1's or the operation principle of circuit 10 similar.When the input signal that is applied to additional input end In3 and is in the ECL level when reference potential is applied to input In1 and In2, the logic add of input signal (or) output Out2 and reversed-phase output/Out2 offered.Or circuit 11 in, be the situation of Vcc for supply voltage from input In1 and In2, the circuit gain logical calculated is 1.Therefore, owing to shortened base stage response time, 2) shown in the circuit gain GO of base stage response time GO * rbb * Cjc become than Fig. 1's or the circuit gain of circuit 10 little.Various analogue tests show, or the switching response time ratio of circuit 11 Fig. 1's or circuit 10 switching response time shortens 5-6%.
By the input transistors of cascade and the size of reduction of device, the ECL circuit of above-mentioned routine can shorten the response time and the base stage response time of switching transistor.Yet it but is very difficult shortening the collector electrode response time.More particularly, need to keep a certain amount of at least load resistance value RL, so that guarantee circuit gain GO.On the other hand, load resistance value RL is big more, and the collector electrode response speed is also slow more.
With reference to Fig. 3, be described in or circuit in adopted the ECL circuit of the first embodiment of the present invention.In Fig. 3, with the similar parts of Fig. 1 with identical reference number and symbolic representation.Or circuit 100 comprises input transistors Q1 and Q2 and additional input transistor Q3.The base stage of transistor Q1, Q2 and Q3 links to each other with In2 with input In1 respectively.The emitting stage of transistor Q1, Q2 and Q3 links to each other with public constant-current source CIS1.Like this, formed a differential amplifier by input transistors Q1 and Q2 and additional input transistor Q3.The collector electrode of transistor Q1, Q2 and Q3 links to each other with output loading.Output loading comprises transistor Q6 and Q7, is connected to base stage and resistance R between the power Vcc 3 and the R4 of transistor Q6 and Q7.Resistance R 3 and R4 are made of the little material of parasitic capacitance, as polysilicon and film resistor.The circuit of back level 20 comprises transistor Q8 and Q9, and constant-current source CIS2.As in conjunction with the accompanying drawings 1 described, capacitor C 1 and C2 represent ground GND and will or output Out3, the reversed-phase output/Out3 of circuit 100 and lead that the circuit input of back level 20 links to each other between parasitic capacitance.
Describe below or the basic functional principle of circuit 100.When the input signal that is applied to additional input end In3 and is in the ECL level when reference potential is applied to input In1 and In2, the logic add of input signal (or) output Out3 and reversed-phase output/Out3 offered.When input In1 and In2 receive the ECL low level, additional input transistor Q3 conducting, and input transistors Q1 and Q2 remain off.As a result, output Out3 has low level, and reversed-phase output/Out3 has high level.This makes the transistor Q8 conducting in the circuit 20 of back level and transistor Q9 is ended.When input In1 and In2 received the ECL high level, additional input transistor Q3 ended, and at least one or two conductings among input transistors Q1 and the Q2.As a result, output Out3 has high level, and reversed-phase output/Out3 has low level.This make in the circuit 20 of back level transistor Q8 by and make transistor Q9 conducting.
Make direct current high potential and the low potential of output Out3 be respectively Vout (H) and Vout (L), they can obtain by following formula so:
Vout (H)=Vcc-(kT/q) * ln (I2/Is) ... (1) and
Vout(L)=Vcc-(kT/q)×ln(I1/Is)-R×I1/h
FF……(2)
Wherein, Vcc is a supply voltage, k is the Hall constant, T is an absolute temperature, and q is the quantity of electric charge of electronics, and Is is anti-phase saturation current, I1 is the emitting stage electric current of transistor Q7 of flowing through when transistor Q3 conducting, I2 be when transistor Q3 by and the base current of the transistor Q9 that flows through during transistor Q9 conducting, R is the resistance value of resistance R 3 and R4, and hFE is the direct current multiplication factor of transistor Q7.
Therefore, according to formula (1) and (2), can obtain the direct current output amplitude Δ Vout (Dc) of output Out3:
ΔVout(Dc)=Vout(H)-Vout(L)
=(kT/q)×ln(I1/I2)+R×I1/h
FE
=(kT/q)×lnh
FE+R×Ic/h
FE……(3)
Wherein, Ic is the electric current of constant-current source of flowing through.Suppose direct current multiplication factor h
FFBe between transistor Q7 and the Q9, and adopt following relational expression: I1=Ic and I2=I1/h
FE
Can be clear that from equation (3) the alternating current output amplitude Δ Vout (Ac) that receives the output Out3 of alternating current can be obtained by following equation (4):
ΔVout(Ac)=(kT/q)×lnh
fe+R×I1/h
fc……(4)
Wherein, h
FcIt is the interchange multiplication factor of transistor Q7.Pay(useful) load resistance R (AC) when receiving ac current signal can be obtained by following formula (5):
R(AC)=α×(h
fe/h
FE)×{re(Ic/2)+R/h
fe} ……(5)
Wherein, α is a constant, and re (Ic/2) is the emitting stage resistance of the transistor Q7 when collector current is Ic/2.
Can clearly be seen that from equation (4), exchange multiplication factor h
FeBig more, alternating current output amplitude Δ Vout (Ac) is also big more.In addition, can clearly be seen that, to have only (h to alternating current output amplitude Δ Vout (Ac) from equation (5)
Fe/ h
FE) this reduces.Second quilt of equation (5) is divided by h
FeTherefore, compare with the ECL circuit of routine, effective value R (AC) can restrictedly descend.So the effective value of load resistance descends.This has shortened the collector electrode response time, and from the viewpoint of speed, has improved the overall performance of ECL circuit.Utilize this structure, it is non-linear that circuit gain can become switching response, and this has caused the distortion of output signal.Yet under the situation of utilizing logical operation rather than simulation trial, design circuit receives output signal in a different manner and can address this problem.
Provide a concrete example now, the electric current I c of the constant-current source of wherein flowing through is 0.5mA, direct current multiplication factor h
FEBe 100, alternating current multiplication factor h
FeBe 20, the resistance value R of resistance R 3 and R4 is 30k Ω, and emitting stage resistance re (250 μ A) is 104k Ω, and computing formula (3) and (5) become following formula (3) respectively so ' and (5) ':
ΔVout(Dc)=26mV×ln(100)+30kΩ×0.5mA/100
=270mV……(3)’
RL(AC)=20/100×(104+30kΩ/20)
=320Ω……(5)’
Wherein, the α in the formula (5) rule of thumb gets 1.
On the other hand, the pay(useful) load resistance value of Chang Gui ECL circuit may be calculated Δ Vout (Dc)/Ic.According to formula (3) ', Δ Vout (Dc)/Ic=270mA/0.5mA=540 Ω.With equation (5) ' product compare, obviously, the pay(useful) load resistance value R (AC) of ECL circuit of the present invention is littler by 40% than the pay(useful) load resistance value of conventional ECL circuit.
Switching response according to ECL circuit of the present invention depends on above-mentioned situation.Yet, suppose τ f=l0pS, rbb=1k Ω, Cjc=10fF, Cjs=50fF, CL=100fF, these all are the representative values of normal conditions, so transistorized switching response time τ f, base stage response time GO * rbb * Cjc, collector electrode response time (RL * Cjs+RL * CL) can be expressed as follows:
1) transistorized switching response time τ f:10pS
2) base stage response time GO * rbb * Cjc:2.6 * 1k Ω * 10fF=26pS, this is (to calculate under 4 * 26mV)=2.6 the situation at GO=Δ Vout (Dc)/(4kT/q)=270mV/.
3) (RL * Cjs+RL * CL): the RL (AC) in adopting formula (5) is when calculating, 320 Ω * (50fF+100fF)=48ps between seasonable for collector electrode.In the ECL of routine circuit, collector electrode is 80ps between seasonable.On the other hand, compare with the ECL circuit of routine, under the situation of pay(useful) load resistance value R (AC) little 40%, from the viewpoint of speed, performance improvement 40%.
Above result calculated is to be 84pS (10pS+26pS+48pS) total switching response time.On the other hand, in the ECL of routine circuit, total switching response time is 116pS (10pS+26pS+80pS).Like this, compare with the ECL circuit of routine, total switching response time of present embodiment has been improved 28% (84/116=0.72).By the size of reduction of device to greatest extent, the collector electrode response time will be bigger than the ratio that total switching response time shortens.Therefore, the overall operating rate of ECL circuit will be faster.
With reference to Fig. 4, the ECL circuit of the second embodiment of the present invention is described.In Fig. 4, the ECL circuit comprises master flip-flop 30 and slave flipflop 40.Master flip-flop 30 comprises difference transistor Q10 and Q11, be connected to the collector electrode of transistor Q10, Q11 and transistor Q6 and Q7 between the power supply, be connected to base stage and resistance R between the power supply 3 and the R4 of transistor Q6, Q7, be connected the common issue level of transistor Q10, Q11 and the transistor Q12 between the constant-current source CIS in addition.Input end of clock In6 links to each other with the base stage of transistor Q12.The base stage of difference transistor Q10 and Q11 links to each other with oppisite phase data input In5 with data input pin In4 respectively.
As mentioned above, by adopting respectively transistor and the resistance that links to each other with power supply with transistorized base stage, ECL circuit of the present invention can reduce the pay(useful) load resistance value and improve the speed of ECL circuit, so that the output loading of formation circuit.In addition, reduce transistorized alternating current multiplication factor h simultaneously by gain calibration
Fe, when switching high-frequency signal,, can significantly improve the performance of circuit from the viewpoint of speed.
Claims (5)
1. an emitter coupled logic (ECL) circuit comprises:
The differential bipolar transistor npn npn, each transistor all has base stage, and the base stage of differential bipolar transistor npn npn receives mutually different input signal;
The load transistor that links to each other with the collector electrode of described differential bipolar transistor npn npn respectively; And
The resistance that links to each other with power supply with the base stage of described load transistor respectively.
2. according to emitter coupled logic (ECL) circuit of claim 1, wherein said differential bipolar transistor npn npn receive respectively an input signal and one as rp input signal with the anti-phase signal that obtains of input signal, and produce output signal from the collector electrode of described differential bipolar transistor npn npn, described emitter coupled logic circuit also comprises a bipolar transistor, this transistorized collector electrode links to each other with the emitting stage of each described differential bipolar transistor npn npn, and base stage is used for the receive clock signal.
3. according to emitter coupled logic (ECL) circuit of claim 1, wherein said differential bipolar transistor npn npn and described load transistor all are NPN transistor.
4. an emitter coupled logic (ECL) circuit comprises:
Differential bipolar transistor npn npn circuit, this circuit comprises the first transistor, and its base stage is used for receiving first input signal and collector electrode produces output signal, and comprises transistor seconds, and its base stage applies a reference voltage;
The 3rd transistor, its emitting stage links to each other with collector electrode with the emitting stage of described the first transistor jointly with collector electrode, and base stage is used for receiving second input signal;
The load transistor that links to each other with the described first and second transistorized collector electrodes respectively; And
The resistance that links to each other with power supply with the base stage of described load transistor respectively.
5. according to emitter coupled logic (ECL) circuit of claim 4, wherein said first to the 3rd transistor and described load transistor all are NPN transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP238627/97 | 1997-09-03 | ||
| JP9238627A JPH1188148A (en) | 1997-09-03 | 1997-09-03 | Ecl logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1213224A true CN1213224A (en) | 1999-04-07 |
Family
ID=17032964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98118598A Pending CN1213224A (en) | 1997-09-03 | 1998-09-03 | Emitter coupled logic circuit capable of operating at higher speed |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH1188148A (en) |
| KR (1) | KR19990029445A (en) |
| CN (1) | CN1213224A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829087B (en) * | 2005-02-14 | 2010-09-01 | 半导体元件工业有限责任公司 | Delay circuit and method therefor |
| CN113472339A (en) * | 2021-07-07 | 2021-10-01 | 弘大芯源(深圳)半导体有限公司 | Transistor logic circuit with stable performance under continuous radiation irradiation |
-
1997
- 1997-09-03 JP JP9238627A patent/JPH1188148A/en active Pending
-
1998
- 1998-09-02 KR KR1019980036057A patent/KR19990029445A/en not_active Application Discontinuation
- 1998-09-03 CN CN98118598A patent/CN1213224A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1829087B (en) * | 2005-02-14 | 2010-09-01 | 半导体元件工业有限责任公司 | Delay circuit and method therefor |
| CN113472339A (en) * | 2021-07-07 | 2021-10-01 | 弘大芯源(深圳)半导体有限公司 | Transistor logic circuit with stable performance under continuous radiation irradiation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1188148A (en) | 1999-03-30 |
| KR19990029445A (en) | 1999-04-26 |
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