KR19990026117A - Nonvolatile Memory Device with Ferroelectric Memory Cells - Google Patents

Abstract

The ferroelectric RAM (FRAM) device according to the present invention provides an array of reference cells having a ferroelectric capacitor having a different area than the ferroelectric capacitor of the memory cell. The ferroelectric capacitors of the respective reference cells allow the amount of charge corresponding to the reference level to be obtained in the non-switching region. This improves the endurance of the reference cell.

Description

NON-VOLATILE MEMORY DEVICE HAVING FERROELECTRIC MEMORY CELL

The present invention relates to a nonvolatile memory device, and more particularly, to a nonvolatile memory device having a ferroelectric capacitor.

Recently, nonvolatile memory having the ability to retain data even at power off has been realized through the use of ferroelectric materials, such as PZT, which exhibit a hysteresis characteristic. By using such ferroelectric materials in the memory cell, the nonvolatile memory can be implemented with a simple structure. Ferroelectric Random Access Memory (FRAM) is non-volatile, and high-speed, low-voltage operation is drawing attention and competition from many memory chip makers.

A memory cell composed of a ferroelectric capacitor and a switching transistor stores a logical state ('1' or '0') of data according to an electrical polarization state of a ferroelectric capacitor (C _F ). When a voltage is applied across the ferroelectric capacitor C _F , the ferroelectric material is polarized according to the direction of the electric field, and a forced voltage is applied to a switching threshold voltage at which the polarization state changes. It is called (coercive voltage). In order to read the data stored in the memory cell, a voltage difference between both electrodes of the ferroelectric capacitor is applied to detect a state of the data stored in the memory cell due to a change in the amount of charge excited on the bit line.

1 shows a 1T / 1C ferroelectric memory cell. The memory cell MC is composed of one switching transistor Tr and one ferroelectric capacitor C _F (one transistor per 1 bit and 1 capacitor 1T / 1C). The switching transistor Tr has two main electrodes connected to one electrode of the ferroelectric capacitor C _F and the bit line BL, that is, a drain electrode and a source electrode, and a gate electrode connected to the word line WL. Has The other electrode of the ferroelectric capacitor C _F is connected to the plate line PL.

2 is a graph showing hysteresis characteristics of a ferroelectric capacitor. 3 shows an operation timing diagram of a ferroelectric RAM device according to the prior art. Referring again to FIG. 2, the abscissa of the graph represents the potential difference between two electrodes of the capacitor, that is, the voltages across the capacitor, and the ordinate represents the spontaneous polarization of the ferroelectric material. Depending on the amount of charge induced on its surface, that is, the degree of polarization (μC / cm ² ).

If a voltage of 0 V is applied so that no electric field is applied to the ferroelectric material, the polarization domains are generally non-uniform and no polarization occurs. When the voltage across the capacitor increases in the positive direction, the polarization degree (or amount of charge) increases from zero to point A in the positive polarization region. At point A, all domains are polarized in one direction, and the degree of polarization at point A reaches a maximum. At this time, the polarization degree, that is, the amount of charge retained by the ferroelectric material is represented by Q _S , and the magnitude of the voltage applied across the capacitor is the operating voltage Vcc. Thereafter, even if the voltage across the capacitor drops back to 0V, the polarization degree does not decrease to 0 but remains at point B. According to such residual polarization, the amount of charge possessed by the ferroelectric material, that is, the residual polarization degree, is represented by Qr. Next, as the voltage across the capacitor increases in the negative direction, the polarization degree changes from point B to point C in the negative charge polarization region (curve 21 in FIG. 2). At point C, all domains of the ferroelectric material are polarized in a direction opposite to the direction of polarization at point A. In this case, the polarization degree is represented by -Q _S , and the magnitude of the voltage applied across the capacitor is -Vcc. Then, even if the voltage across the capacitor drops back to 0V, the polarization value does not drop to 0 but remains at point D. Residual polarization degree at this time is represented by -Qr. When the magnitude of the voltage across the capacitor once again increases in the positive direction, the polarization of the ferroelectric material changes from point D to point A.

As described above, when a voltage for generating an electric field is applied once to a ferroelectric capacitor having a ferroelectric material inserted between two electrodes, the polarization direction according to spontaneous polarization is maintained even after the electrodes are set to a floating state. do. The surface charge of the ferroelectric material due to spontaneous polarization is not naturally lost by leakage or the like. If no voltage is applied in the opposite direction such that the polarization degree is zero, the polarization direction is maintained as it is.

Next, writing / reading of the FRAM is performed by polarization inversion as described above. Thus, the operating speed of the FRAM is determined by the polarization inversion time. The polarization inversion rate of the ferroelectric capacitor is determined according to the area of the capacitor, the thickness of the ferroelectric thin film, the applied voltage and the like, but is usually in the unit of ns. This means that it can run much faster compared to EEPROM or flash memory with read / write times in μs.

Referring back to FIG. 2, assume that data '1' is stored in the ferroelectric capacitor C _F having the polarization state at point B. As the high voltage level (here, the power supply voltage: Vcc) is applied to the word line WL, the switching transistor Tr is conducted, and the negative voltage (-Vcc) is connected to the bit line BL and the plate line PL. through change of a ferroelectric capacitor (C _F), when applied to the ferroelectric capacitor (C _F) polarization (P) is the state that (B) state point (D) via the state point (C) in the. The charge dQ1 corresponding to this state transition is transferred between the bit line BL and the ferroelectric capacitor C _F through the switching transistor Tr. Charge transfer is detected by the sense circuit (see FIG. 4) connected with the bit line BL, which means that the data value '1' has been read from the memory cell MC. After reading data '1' from the memory cell MC, the same data '1' on the bit line BL is written back to the memory cell MC by lowering the voltage of the plate line PL. . This write result involves reverse state transient from state point D to state point A. FIG.

On the other hand, if the data '0' is stored in the ferroelectric capacitor C _F with the polarization state at point D, as in the previous assumption, the high voltage level (here, the supply voltage Vcc) goes to the word line WL. When applied, the switching transistor Tr conducts (ON) and when a negative voltage is applied to the ferroelectric capacitor C _F via the bit line BL and the plate line PL, its polarization P is in a state Change from point (D) to status point (C) and then return to status point (D) again. The charge dQ0 corresponding to this state transition is transferred between the bit line BL and the ferroelectric capacitor C _F through the switching transistor Tr. The charge transfer is detected by the sense circuit (see FIG. 4) connected with the bit line BL, which means that the data value '0' is read out from the memory cell MC.

In the above-described ferroelectric RAM (FRAM) device of 1T / 1C structure, a reference cell corresponding to one bit line performs a switch operation together with memory cells related to the bit line. For example, assume that there are 100 memory cells associated with one bit line. In this case, when a write / read operation is performed on 100 memory cells corresponding to one bit line, one reference cell associated with one bit line for providing a reference level to the sensing circuit (see FIG. 4) is 100. Double switching operation is required. As a result, the endurance of the ferroelectric capacitor of the reference cell is degraded.

Accordingly, an object of the present invention is to provide a ferroelectric ram device having a reference cell with improved durability.

1 is an equivalent circuit diagram of a 1T / 1C ferroelectric memory cell;

2 is a graph showing hysteresis characteristics of a typical ferroelectric capacitor;

3 is a timing diagram of pulses for driving plate lines of a memory cell and a reference cell according to the prior art;

4 is a block diagram showing the configuration of a ferroelectric RAM device;

5 is a timing diagram of pulses for driving plate lines of a memory cell and a reference cell according to the present invention;

* Explanation of symbols for main parts of the drawings

10: memory cell array 20: row decoder circuit

30: sensing circuit 40: sensing drive level generating circuit

50: reference cell array 60: column decoder circuit

70: column selection circuit

According to one aspect of the present invention for achieving the above object, in a ferroelectric RAM device: word lines, bit lines, plate lines corresponding to the word lines, and each of the ferroelectric capacitor and switching transistor And one electrode of the ferroelectric capacitor is connected to a corresponding bit line through a corresponding switching transistor, the other electrode thereof is connected to a corresponding plate line, and the control electrode of the switching transistor is connected to a corresponding word line. A memory cell array of memory cells connected; A reference cell array having reference bit lines respectively corresponding to the bit lines, reference word lines, reference plate lines corresponding to the reference word lines, and reference cells respectively corresponding to the reference bit lines; Select signals for selecting one of the word lines and the reference word line of the word lines of the memory cell array and unselected signals for unselected word lines, and for driving the selected word lines and reference word lines. A row decoder for generating a pulse signal; A level of the selected data bit by accepting a reference level having a level corresponding to data bits of a selected memory cell among the memory cells, and an average level of levels corresponding to data bits, respectively, from a reference cell corresponding to the selected memory cell; It includes a sensing unit for sensing the; Each reference cell is configured to be different from the area of the ferroelectric capacitor of the memory cells associated with the corresponding bit line.

In this embodiment, the reference level supplied to the sensing unit is provided by a non-switching operation of each reference cell.

In this embodiment, the pulse signal applied to the reference cell array is applied so as not to overlap with the pulse signal applied to the memory cell array.

With such a device, a reference level can be obtained by a non-switching operation rather than a switching operation of the ferroelectric capacitor of the reference cell.

A block diagram showing the configuration of a ferroelectric ram device according to a preferred embodiment of the present invention is shown in FIG. And, the operation timing diagram according to the present invention is shown in FIG. Referring to FIG. 4, m word lines WL1 to WLm and m plate lines PL1 to PLm along rows corresponding to the cell array region 10 on the substrate defining the rows and columns. ) Elongate respectively. Further, n bit lines BL1 to BLn extend along the corresponding columns. m x n ferroelectric memory cells are formed in a matrix form at points where m word lines WL1 to WLm and n bit lines BL1 to BLn intersect.

Each memory cell is composed of one switching transistor Trij (where i = 1 to m, j = 1 to n) and a ferroelectric capacitor C _F ij. A ferroelectric material is inserted between the two electrodes of the capacitor C _F ij. The current path of the switching transistor Trij, i.e., the drain-source channel, is connected between one electrode of the corresponding ferroelectric capacitor C _F ij and the corresponding bit line BLj. The gate of the switching transistor Trij is connected to the corresponding word line WLi. For example, in the memory cell MC11, the current path of the switching transistor T11 is connected between one electrode of the ferroelectric capacitor C11 and the bit line BL1, and its gate is connected to the word line WL1. Connected. The other electrode of the ferroelectric capacitor C11 is also connected to the corresponding plate line PL1.

Referring again to FIG. 4, the word lines WL1 to WLm and the plate lines PL1 to PLm are connected to the row decoder circuit 20. The row decoder circuit 20 selects one word line and applies a pulse signal of a voltage level such that all polarization domains of the ferroelectric material are completely polarized in a predetermined direction onto the plate line corresponding to the selected word line. do.

One end of each of the bit lines BL1 to BLn is connected to the latch sensing circuit 30, and the other end is connected to the column select circuit 70. The sense circuit 30 includes two sense drive lines SAP and SAN from the sense drive level generation circuit 40 and n reference bit lines connected to the reference cell array 50 as shown. Although connected to RBL1)-(RBLn) and not shown in the figure, it is well known to those skilled in the art that the sense circuit 30 consists of n latch sense amplifiers.

A reference cell array 50, as is generally well known, is provided with the sense circuit 30 through bit lines corresponding to a reference level of data '1' or '0' stored in a selected memory cell. Latch sense amplifiers. And, the column select circuit 80 is provided with n NMOS transistors (not shown), as is well known to those skilled in the art. The current path of each of the select transistors is connected between a corresponding bit line BLj and a corresponding data line DLy (where y = 1 to k). Each of these transistors is turned on / off by respective column select signals Y1 to Yn from the column decoder circuit 70.

Typically, 1T / 1C FRAM uses a switching region for data '1' and a non-switching region for data '0' to store data in memory cells. do. In addition, the FRAM requires a reference level for sensing stored data. As shown in FIG. 4, there are m memory cells corresponding to one bit line, and although not shown in the drawing, in general, reference cells corresponding to one bit line are configured as one. Therefore, when reading data of each memory cell corresponding to one bit line every time, the reference cell always performs a switching operation. As a result, the reference cell corresponding to one bit line is vulnerable to fatigue proportional to the number of switching. As is well known, fatigue is a phenomenon that occurs during the switching operation of all domains of a ferroelectric capacitor, and this phenomenon does not occur when using a non-switching operation.

Therefore, the ferroelectric capacitor of each reference cell constituting the reference cell array according to the present invention is configured to have an area capable of generating an average charge amount of the charge amount changed during the switching operation and the charge amount changed during the non-switching operation. For example, for a 64k FRAM, a 9μm ² reference cell capacitor induces a charge of 6.12pC for switching and 2.61pC for de-switching. In order to obtain a reference level, a conventional FRAM is used by averaging polarizations generated by switching and unswitching operations of a reference cell, that is, voltages corresponding to a changed amount of charge. As a result, when using a 9 μm ² reference cell capacitor, as described above, since the charge of 6.12 pC during switching and 2.61 pC during non-switching occurs, each reference cell according to the present invention has an average value of 4.365 during switching and non-switching. It consists of a ferroelectric capacitor with an area of 15 μm ² that can be induced when unswitched pC. In addition, as shown in FIG. 5, pulse signals applied to the plate line corresponding to the memory cell and the reference cell are applied not to overlap each other. Therefore, since the switching operation of the reference cell is not used, a write back operation for the reference cell is not required. As a result, as shown in FIG. 5, the plate line corresponding to the reference cell is activated at the time of sensing. It is driven by the pulse signal of.

As described above, by providing the reference cell using only the non-switching region, the fatigue phenomenon of the reference cell can be reduced, and the reliability of the ferroelectric ram device is improved.

Claims (3)

In ferroelectric ram devices: Word lines, bit lines, plate lines corresponding to the word lines, each having a ferroelectric capacitor and a switching transistor, wherein one electrode of the ferroelectric capacitor is connected to the corresponding bit line through a corresponding switching transistor A memory cell array of memory cells whose other electrodes are connected to corresponding plate lines and whose control electrodes of the switching transistors are connected to corresponding word lines; A reference cell array having reference bit lines respectively corresponding to the bit lines, reference word lines, reference plate lines corresponding to the reference word lines, and reference cells respectively corresponding to the reference bit lines; Select signals for selecting one of the word lines and the reference word line of the word lines of the memory cell array and unselected signals for unselected word lines, and for driving the selected word lines and reference word lines. A row decoder for generating a pulse signal; A level of the selected data bit by accepting a reference level having a level corresponding to data bits of a selected memory cell among the memory cells, and an average level of levels corresponding to data bits, respectively, from a reference cell corresponding to the selected memory cell; It includes a sensing unit for sensing the; Wherein each reference cell is configured differently from an area of a ferroelectric capacitor of memory cells associated with a corresponding bit line. The method of claim 1, And the reference level supplied to the sensing unit is provided by a non-switching operation of each reference cell. The method of claim 1, And the pulse signal applied to the reference cell array is applied so as not to overlap with the pulse signal applied to the memory cell array.