KR100319757B1 - Ferroelectric memory device having single ferroelectric fet - Google Patents

Abstract

According to the present invention, when unit memory cells are programmed in a 'first state' or 'second state', one unit memory cell may be independently selected and programmed, and a write disturb phenomenon may be prevented during a program operation on a unit memory cell. In order to provide a ferroelectric memory device having a single ferroelectric transistor, a plurality of unit memories in which a plurality of word lines in a row direction and a plurality of bit lines and source lines in a column direction cross each other and are arranged in a matrix form are provided. 10. A ferroelectric memory device having a cell, each of the unit memory cells having a single ferroelectric transistor connected between the source line and the bit line and having a gate connected to the word line, and well of the single ferroelectric transistor Are connected to one common well line in the column direction, but And it is electrically isolated to each other and a common straw in a column, a source or a drain of the single transistor ferroelectric is configured to be connected in common to one of the bit line or the source line in the column direction.

Description

FERROELECTRIC MEMORY DEVICE HAVING SINGLE FERROELECTRIC FET}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the construction of semiconductor devices and memory implementations, and more particularly to a technique for integrating ferroelectric devices and metal-oxide-semiconductor (MOS) transistors.

In general, the MOS transistor uses an SiO ₂ oxide film as a gate thin film, and its operation is controlled by a change in the threshold voltage in response to the gate voltage. In contrast, a single ferroelectric transistor uses a ferroelectric material such as lead zirconium titanium oxide (Pb (Zr, Ti) O ₃ ) (PZT), strontium bismuthstantalum oxide (SrBi ₂ Ta ₂ O ₉ ) (SBT) as a gate thin film, The operation is controlled in accordance with the polarization characteristics of the ferroelectric material.

A nonvolatile ferroelectric memory device stores data by using hysteresis between voltage and storage charge of a ferroelectric element in which polarization charges are preserved even without a power supply, and a unit storage unit stores one transistor and one ferroelectric capacitor or one. There are those consisting of dog ferroelectric transistors.

1 is a hysteresis characteristic versus charge-voltage of a typical ferroelectric device.

Referring to FIG. 1, when the voltage applied to the ferroelectric element is '0 V', the charge amount has two different values C and E, so that the ferroelectric element may have different polarization states 'first state' or 'first'. 2 state. That is, the polarization state of the ferroelectric element is disposed in a predetermined direction according to the voltage applied between the thin films to become a 'first state' or 'second state'.

FIG. 2 is a view for explaining the principle of operation of an N-channel single ferroelectric transistor. When the voltage between the gate and P-Si of the N-channel single ferroelectric transistor is positive (+ V), charges are induced on the silicon surface and negative (- V), no charge is induced.

3 is a hysteresis characteristic of the drain current versus the gate voltage of a single ferroelectric transistor, and it can be seen from the drawing that the drain current Id is different when the gate voltage Vg increases and decreases. .

Next, FIG. 4 illustrates a memory cell arrangement of a ferroelectric memory device having a single ferroelectric transistor according to the related art, and includes a plurality of word lines WL1 to WLn and a plurality of bit lines on a common well. BL1 to BLm and the source lines SL1 to SLn cross each other and include a plurality of unit memory cells configured in a matrix form, wherein the unit memory cells are disposed between the source lines SL1 to SLn and the bit lines BL1 to BLm. And a single ferroelectric transistor FM1, FMm, FMn FMn + m, whose gate is connected to the word lines WL1 through WLn.

In order to program any selected unit memory cell in a first cell in a memory cell of the ferroelectric memory device configured as shown in FIG. 4, a supply voltage Vdd (hereinafter, referred to as Vdd) is applied to a corresponding word line of the unit memory cell. ) And a ground voltage GND (hereinafter referred to as GND) to the corresponding bit line, source line, and common well line WELL. In order to prevent the remaining unselected unit memory cells from being programmed to the 'first state', GND is applied to the corresponding word line and Vdd is applied to the source line, the bit line, and the common well line. At this time, as shown in FIG. 4B, a write disturb phenomenon occurs in a non-selection unit memory cell in which GND is applied to a gate of a single ferroelectric transistor and Vdd is applied to a source, a drain, and a common well line. That is, the 'first state' is incorrectly programmed in the non-selection unit memory cell.

As described above, when the write disturb phenomenon occurs, not only the wrong data is programmed in the non-selection unit memory cell, but, for example, the normal memory cells programmed in the 'first state' are not displayed in the 'first state' due to the write disturb phenomenon. The normal information programmed as is changed to the 'second state', causing the data to be destroyed.

Meanwhile, in order to program the selected unit memory cell to the second state, GND is applied to the corresponding word line, and Vdd is applied to the corresponding bit line, the source line, and the common well line. In this case, since a specific memory cell cannot be selected among the plurality of unit memory cells, a voltage is commonly applied to all the ferroelectric transistors arranged.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and when a unit memory cell is programmed to a 'first state' or 'second state', a single ferroelectric can be independently selected and programmed. It is an object of the present invention to provide a ferroelectric memory device having a transistor.

Another object of the present invention is to provide a ferroelectric memory device having a single ferroelectric transistor, which prevents a disturb phenomenon during a program operation on a unit memory cell.

1 is a hysteresis plot of charge-voltage of a ferroelectric device.

2 is a view for explaining the principle of operation of the N-channel single transistor ferroelectric element.

3 is a hysteresis plot of drain current-gate voltage of a single ferroelectric transistor.

4 is a memory cell arrangement diagram of a ferroelectric memory device having a single ferroelectric transistor according to the prior art.

5 shows the structure and symbols of a typical single ferroelectric transistor;

6 is a memory cell arrangement diagram of a ferroelectric memory device having a single ferroelectric transistor in accordance with one embodiment of the present invention.

FIG. 7 is a 2x2 memory cell arrangement diagram of a ferroelectric memory device according to one embodiment of the present invention; FIG.

8 is a circuit diagram of a 4x4 memory cell arrangement and decoder of a ferroelectric memory device according to one embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

FM: ferroelectric transistor

WL: wordline

WLn: nth word line

BL: Bitline

BLm: mth bit line

SL: Source Line

SLm: mth source line

Vdd: Supply Voltage

SUMMARY OF THE INVENTION The present invention provides a ferroelectric memory device including a plurality of unit memory cells in which a plurality of word lines in a row direction and a plurality of bit lines and a source line in a column direction cross each other and are arranged in a matrix form. Each of the unit memory cells has a single ferroelectric transistor connected between the source line and the bit line, and has a gate connected to the word line, and the well of the single ferroelectric transistor has one common well line in a column direction. The first ferroelectric transistor is connected to the common well line of another adjacent column, and the source or the drain of the single ferroelectric transistor is configured to be commonly connected to the bit line or the source line in the column direction.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

5 is a diagram showing the structure and symbols of a typical single ferroelectric transistor.

Referring to FIG. 5A, in the structure of a single ferroelectric transistor, the conductivity types of the well and the substrate are opposite to each other, and the conductivity types of the source and drain are opposite to the wells. The ferroelectric thin film of the gate is preferably a ferroelectric such as PZT, SBT, etc., but other ferroelectric characteristics may be used.

In addition, in order to program data into a 'first state' or 'second state' of a memory cell having a single ferroelectric transistor shown in FIG. 5B or to read stored data, an operation appropriate for a gate, a source, and a drain may be performed. A bias voltage must be applied. Memory cells with a single ferroelectric transistor are basically programmed when the gate and well voltages are positive and not when they are negative.

FIG. 6 is a memory cell arrangement diagram of a ferroelectric memory device having a single ferroelectric transistor according to an embodiment of the present invention, and includes a plurality of word lines WL1 to WLn, a plurality of bit lines BL1 to BLm, and a source line. SL1 to SLm cross each other and have a plurality of unit memory cells formed in a matrix form, wherein the unit memory cells are connected between source lines SL1 to SLm and bit lines BL1 to BLm, and gates are word lines. A source of a single ferroelectric transistor having a single ferroelectric transistor connected to (WL1 to WLn), wherein the wells of the single ferroelectric transistors arranged in the column direction are connected to the heat common well lines (WELL1 to WELLm) and arranged in the column direction. Alternatively, the drain is commonly connected to the bit lines BL1 to BLm or the source lines SL1 to SLm.

The memory array of the ferroelectric memory device configured as described above uses a source line and a drain line as a column line, and a well line as a column line to isolate the wells with the column line. That is, since the heat common well lines WELL1 to WELLm of different adjacent columns are not directly connected to each other, a potential may be selectively applied to the wells of any row through the heat common well lines WELL1 to WELLm.

Referring to FIG. 6, a program operation for an arbitrary unit memory cell 10 having a single ferroelectric transistor will be described.

First, the ferroelectric memory device maintains the word line at GND in the reset state, maintains the column common well line at Vdd, and initializes polarization with a negative voltage difference between the gate and the well of the single ferroelectric transistor.

In order to program the unit memory cell 10 to the 'first state', the Vdd voltage is applied to the corresponding word line WL1 connected to the gate of the single ferroelectric transistor, and the GND voltage is applied to the thermal common well line WELL1. do. Thus, the voltage difference between the gate and the well of the single ferroelectric transistor is positively programmed.

At this time, among the unselected unit memory cells, Vdd is applied to the well of the single ferroelectric transistor, and Vdd is applied to the gate of the memory cells 20 and 30 which are commonly connected to the word line WL1 of the selected unit memory cell 10. The initial polarization state is maintained as it is, and the remaining non-selected unit memory cells 40 to 60 are applied with Vdd to the well of the single ferroelectric transistor and GND to the gate to maintain the initial polarization state, thereby preventing the write disturb phenomenon.

Next, GND is applied to the corresponding word line WL1 connected to the gate of the single ferroelectric transistor and Vdd is applied to the column common well line WELL1 in order to program the corresponding unit memory cell 10 to the 'second state'. . As a result, the voltage difference between the gate and the well of the single ferroelectric transistor becomes negative and is programmed to an unprogrammed state, that is, a 'second state'.

At this time, among the non-selected unit memory cells, the memory cells 20 and 30 commonly connected to the word line WL1 of the selected unit memory cell 10 have GND applied to the well of the single ferroelectric transistor and GND applied to the gate thereof. The initial polarization state is maintained and the remaining non-selected unit memory cells 40 to 60 are applied with GND and Vdd to the well of the single ferroelectric transistor to maintain the initial polarization state.

The program operation for the unit memory cell as described above is because the single ferroelectric transistor presented in the embodiment of the present invention is N-channel, and when the P-channel single ferroelectric transistor is employed, the 'first state' and 'second state' Program behavior is different.

As described above, when performing a program operation on a unit memory cell by applying a DC bias voltage to both the gate and the well of a single ferroelectric capacitor, a bipolar one pulse for driving a single ferroelectric memory device is easily generated. And decoder implementation is very easy.

FIG. 7 is a diagram illustrating a 2 × 2 memory cell arrangement for explaining in detail selecting and programming a specific cell from a memory cell array of a ferroelectric memory device according to an embodiment of the present invention.

Referring to the drawings, in order to select a specific cell 100 from a 2 x 2 memory cell, the common word line WL1 of the specific cell 100 is shifted and driven from GND to Vdd, and the thermal common well of the specific cell 100 is driven. The phosphorus (WELL2) is driven to transition from Vdd to GND. At this time, since the word line WL2 of the remaining non-selected cells maintains GND and the column common well line WELL1 maintains Vdd, the voltage difference between the gate and the well of the specific cell 100 is Vdd, and the unselected remaining The voltage difference between the gate and the well of the cells is -Vdd or '0' (for a cell in which a specific cell 100 and word line WL1 are commonly connected). Therefore, selective program operation for a specific cell 100 is possible.

FIG. 8 is a circuit diagram of a 4 × 4 memory cell array and a decoder of a ferroelectric memory device according to an embodiment of the present invention. The memory cell array 200 is configured in the same way as the arrays of FIGS. 6 and 7. A source line and a column common well line of a single ferroelectric transistor of memory cells arranged in a column are configured to be commonly connected to the decoded output signal output from the decoder 220.

Referring to the figure, the decoder 220 decodes the address signals a2 and a3 input from the outside to selectively drive any one word line among the plurality of word lines WL1 to WLn. And a second decoding unit 222 for selectively driving any one of the plurality of thermal common welllines WELL1 to WELLm by decoding the address signals a0 and a1 input from the outside. . The structure of the decoder 220 has the same configuration as in the related art, but has a configuration difference in which the decoding output signal from the second decoding unit 222 is connected to the thermal common well line.

On the other hand, in general, the threshold voltage of a programmed single ferroelectric transistor is increased, whereas the threshold voltage of an unprogrammed single ferroelectric transistor is the same as that of a general MOS transistor.

In order to read the storage information of the selected memory cell at an arbitrary position, a read voltage is applied to the common word line of the selected memory cell, and a sensing voltage is applied between the bit line and the source line. For example, when the memory cell to be read is a programmed cell, the read voltage applied to the gate of the single ferroelectric transistor is lower than the threshold voltage so that the single ferroelectric transistor is turned off so that the current hardly flows, and vice versa. If the cell is an unprogrammed cell, the read voltage applied to the gate of the single ferroelectric transistor is higher than the threshold voltage so that the single ferroelectric transistor is turned on and current flows. Subsequently, a sense current (not shown) connected to the bit line senses a current difference to read information stored in the selected memory cell.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, a DC bias voltage is applied to both the gate and the well of a single ferroelectric transistor in a unit memory cell of a ferroelectric memory device having a single ferroelectric transistor, thereby allowing the unit memory cell to be 'first state' or 'second'. When programming to 'state', one unit memory cell can be independently selected and programmed, and an excellent effect of preventing write disturb when a program operation is performed on a unit memory cell without a separate circuit can be realized.

In addition, the ferroelectric memory device of the present invention can be driven only by general power levels Vdd and GND without supplying a high power voltage.

Claims (6)

A ferroelectric memory device having a plurality of unit memory cells in which a plurality of word lines in a row direction and a plurality of bit lines and a source line in a column direction cross each other and are arranged in a matrix form. Each of the unit memory cells includes a single ferroelectric transistor connected between the source line and the bit line and having a gate connected to the word line, Wells of the single ferroelectric transistor are connected to one common well line in the column direction, and are electrically connected to each other and to the common well lines of other adjacent columns. The source or drain of the single ferroelectric transistor is configured to be commonly connected to one of the bit line or the source line in the column direction. The method of claim 1, wherein the program unit is configured to program any one unit memory cell of the plurality of unit memory cells to an arbitrary 'first state'. The first unit voltage is applied to a corresponding word line connected to the gate of the single ferroelectric transistor of the selected unit memory cell, and the second unit voltage is applied to the common well line, thereby selecting the selected unit memory cell. Program it to "first state," Maintains an initial polarization state by applying a voltage of the first level to a common well line of the single ferroelectric transistor provided in a unit memory cell commonly connected to a word line of the selected unit memory cell among the unselected unit memory cells, The first level voltage is applied to a common well line of the single ferroelectric transistor included in the remaining unselected unit memory cells among the unselected unit memory cells, and the voltage of the second level is applied to a corresponding word line connected to a gate. A ferroelectric memory device for maintaining an initial polarization state by applying a. The method of claim 2, wherein the program unit is configured to program any one unit memory cell of the plurality of unit memory cells to an arbitrary 'second state'. The selected unit memory cell is applied by applying a voltage of the second level to a corresponding word line connected to a gate of the single ferroelectric transistor of the selected unit memory cell and applying the voltage of the first level to a corresponding common well line. Program the above 'second state', Maintains an initial polarization state by applying a voltage of the second level to a common well line of the single ferroelectric transistor provided in a unit memory cell commonly connected to a word line of the selected unit memory cell among the unselected unit memory cells, The voltage of the first level is applied to a corresponding word line connected to a gate of the single ferroelectric transistor provided in the remaining unselected unit memory cells among the unselected unit memory cells, and the voltage of the second level is applied to the common well line. A ferroelectric memory device for applying a voltage to maintain an initial polarization state. The method of claim 2 or 3, The voltage of the first level is, A supply voltage applied to the ferroelectric memory device, The voltage of the second level is A ferroelectric memory device, characterized in that the ground voltage. The method of claim 1, wherein the common well line of the single ferroelectric transistor arranged in the same column, And a decoded output signal output from decoding means for decoding an address signal input from the outside. The method of claim 5, wherein the decoding means, A first decoding circuit unit for selectively driving any one of the plurality of word lines by decoding the address signal input from the outside; And And a second decoding circuit unit configured to decode the address signal input from the outside to selectively drive one column common well line among the plurality of common well lines. The decoding output signal of the second decoding circuit unit is And a common well line of the single ferroelectric transistor arranged in the same column.