JP3483210B2 - Ferroelectric nonvolatile memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of using a ferroelectric non-volatile memory, and more particularly to a method of preventing mispolarization.

[0002]

2. Description of the Related Art FIG. 8 shows a nonvolatile memory 41 using a ferroelectric transistor disclosed in Japanese Patent Laid-Open No. 2-64993. In the non-volatile memory 41, an N-type well region 122 is formed on a part of the surface of a P-type substrate 121. A ferroelectric film 123 made of a ferroelectric material is provided in a predetermined region on the well region 122. A gate electrode 124 made of a conductive material is formed on the ferroelectric film 123. A source region 125 and a drain region 126 made of a high-concentration P-type impurity diffusion layer are formed on both sides of the well region 122 below the gate film 123. The electrode region (high-concentration N-type impurity diffusion layer) 127 of the well region 122 is connected to the source region 125.

Next, the operation principle of the non-volatile memory 41 having the ferroelectric gate film 123 will be described with reference to the ferroelectric substance E- of FIG.
This will be described with reference to the P hysteresis loop. In the figure, the vertical axis represents the polarization P and the horizontal axis represents the electric field E.

When writing to the nonvolatile memory 41 shown in FIG. 8, a ground potential is applied to the gate electrode 124 and a program voltage sufficiently higher than the coercive voltage is applied to the N well 122. The coercive voltage is a voltage for obtaining an electric field Ec required to remove the remanent polarization of the ferroelectric substance. At this time, the electric field generated between the gate electrode 124 and the N well 122 causes the ferroelectric film 123 to be polarized in a direction substantially the same as the direction of the generated electric field (see R1 in FIG. 3). That is, as shown in FIG. 8C, the ferroelectric film 123 has a gate electrode 124.
The side is polarized positive and the side of the N well 122 is polarized negative.

Due to such a polarization state, the gate electrode 1
Positive charges composed of inversion layer charges and depletion layer charges are induced on the semiconductor surface under 24. If the remanent polarization is sufficiently large, an inversion layer is formed, and the source region 125 and the drain region 126 are electrically connected (hereinafter referred to as an on state). This state is hereinafter referred to as a writing state. Even if the program voltage is cut off, the polarization state remains almost unchanged (S1 in FIG. 3). On the other hand, in the case of erasing, the ground potential is applied to the N well 122 and the program voltage sufficiently higher than the coercive voltage is applied to the gate electrode 124, contrary to the time of writing. At this time, the gate electrode 124 and the N well 1
An electric field in the opposite direction to that at the time of writing is generated between 22. Therefore, the polarization state of the ferroelectric film 123 is reversed by this electric field (P1 in FIG. 3). That is, the ferroelectric film 123
8B, the gate electrode 124 side is negatively polarized and the N well 122 side is positively polarized (Q in FIG. 3).
1).

Therefore, the inversion layer under the gate electrode 124 disappears, negative charges are formed as an accumulation layer, and the source region 125 and the drain region 126 are electrically insulated (hereinafter referred to as an off state). This state is called a non-writing state. Even if the program voltage is cut off, the polarization state remains almost unchanged.

Next, the read operation of the non-volatile memory 41 will be described. When the ferroelectric film 123 is in the written state, the channel formation region 130 is in the on state, and the drain 12
By making the potential of 5 higher than that of the source 126, a current flows between the drain 125 and the source 126.

On the other hand, when the ferroelectric film 123 is in the non-written state, the channel forming region 130 is in the off state. Therefore, the potential of the drain 125 is changed to the source 126
Higher than the potential of the drain 125 and the source 126
No current flows between them.

As described above, once the nonvolatile memory 41 is put in the written state, the written state is maintained even if the voltage supply to the gate electrode 124 is stopped. Also,
Whether it is written or not depends on the source 126 and the drain 1.
It can be determined by whether or not a current flows during 25.

The non-volatile memory 41 is used as an SRAM (static RAM). An equivalent circuit 15 of a circuit in which a plurality of nonvolatile memories 41 are combined is shown in FIG. As shown in the figure, the non-volatile memory 41 is used by providing one selection transistor on each side. This is to prevent writing or reading to a memory other than the memory to which writing or reading is desired (hereinafter referred to as a selected cell).

Writing is performed as follows.
The first word line WL1 is set to Vcc potential to turn on the transistor T1, and the second word line WL2 is set to Vss potential (ground potential) to turn off the transistor T2. In addition, the gate electrode of the nonvolatile memory 41 is set to Vcc / 2 potential. Further, the data from the bit line BL is applied to the source / substrate of the nonvolatile memory 41. As a result, in the non-volatile memory 41, the Vcc / 2 potential is applied between the gate and the substrate, the ferroelectric film 123 (see FIG. 8) is brought into a predetermined polarization state, and data can be written.

On the other hand, in the read operation, the second word line WL2 is set to the Vcc potential to turn on the transistor T2, and the first word line WL1 is set to the Vcc potential to turn on the transistor T1. Here, the bit lines BL ... Are previously set to Vcc / 2 by the precharge circuit PR.
Precharge to the above potential. As a result, if the non-volatile memory 41 is in the write state, a current flows, and the potential of the bit line BL connected to the non-volatile memory 41 decreases. On the other hand, if the non-volatile memory 41 is in the non-writing state, no current flows, so the potential of the bit line BL to which the non-volatile memory 41 is connected does not change. Thus, the potential of the bit line BL changes depending on whether the nonvolatile memory 41 is in the written state or the non-written state. Data can be read by detecting and amplifying this potential change by the corresponding sense amplifier SA.

As described above, in the nonvolatile memory 41 using the ferroelectric film, when a plurality of combinations are used,
Two types of transistors T1 and T2 are provided to prevent erroneous reading and erroneous writing.

[0014]

However, the method of using the ferroelectric non-volatile memory as described above has the following problems. Generally, a ferroelectric substance has a property that polarization reversal occurs even if there is a slight electric field change. Therefore, there is a problem that the unselected cell is erroneously written.

It is an object of the present invention to solve the above problems and to provide a method of using a ferroelectric non-volatile memory which can more surely prevent erroneous writing to non-selected cells. To do.

[0016]

Means for Solving the Problems 1) A ferroelectric nonvolatile memory device according to the present invention is a ferroelectric nonvolatile memory device in which cells having ferroelectric transistors are arranged in a matrix. When writing, a write voltage larger than the coercive voltage is applied to the ferroelectric film of the cell to be written, and the write prevention voltage is applied to the ferroelectric film of the cell whose writing is to be prevented below the ferroelectric film. By applying the write voltage to the ferroelectric film of the cell by applying the voltage to the substrate region, in the ferroelectric nonvolatile memory device in which information is written only in the cell to be written, the ferroelectric transistor of the ferroelectric transistor The threshold voltage for forming an electric path in the substrate region below the ferroelectric film is set lower than the coercive voltage of the ferroelectric film, and Then, in the cell in which the writing is to be prevented , an inversion layer is formed in the substrate region below the ferroelectric film of the cell before the voltage corresponding to the coercive electric field is applied to the ferroelectric film, and the inversion layer is used for writing. It is configured so that a voltage whose value increases with the elapse of time, such as a preventive voltage is applied to the substrate region under the ferroelectric film. 2 ) A ferroelectric non-volatile memory device according to the present invention comprises a ferroelectric transistor portion having a ferroelectric film and a selection transistor portion for interrupting a write protection voltage to the ferroelectric transistor portion. In the ferroelectric non-volatile memory device in which the cells arranged in a matrix are arranged, the cells located in the column direction among the cells arranged in the matrix have the same control gate electrode of the ferroelectric transistor part. Among the cells arranged in the matrix, the drain region of the ferroelectric transistor portion is connected to the line and the gate electrode of the selection transistor portion is connected to the same word line. When connected to the same bit line and writing data, apply the following voltage and write voltage In a ferroelectric non-volatile memory device that writes information only to the cell to be written so that 1 is not applied to the ferroelectric film of the cell, 1) the word line to which the control gate electrode of the cell to be written is connected A write voltage higher than the coercive voltage, 2) a write protection voltage to bit lines other than the bit line to which the write-scheduled cell is connected, and 3) a select transistor to a word line to which the gate electrode of the write-scheduled cell is connected. 4) has a voltage applying means for applying a voltage for turning on, and 4) the threshold voltage for forming an electric path in the substrate region below the ferroelectric film of the ferroelectric transistor is the resistance of the ferroelectric film. It is set lower than the voltage, 5) the voltage applying means, to the word line to which the control gate electrode of the cell to be written is connected, An inversion layer is formed in the substrate region below the ferroelectric film of the cell not to be written, and the write prevention voltage applied to a bit line other than the bit line to which the cell to be written is connected is ferroelectric by the inversion layer. The passage of time such that the coercive voltage is reached after being applied to the substrate region under the body membrane
A voltage having a waveform whose value increases with the application of the voltage is applied .

[0017]

1) In the ferroelectric non-volatile memory device according to the present invention, the threshold voltage for forming an electric path in the substrate region below the ferroelectric film of the ferroelectric transistor has the above-mentioned threshold voltage. The voltage is set lower than the coercive voltage of the ferroelectric film, and the write voltage is set to prevent the write .
For the cell to be stopped , an inversion layer is formed in the substrate region below the ferroelectric film of the cell before the voltage corresponding to the coercive electric field is applied to the ferroelectric film. It is configured so that a voltage whose value increases with the elapse of time, such as is applied to the substrate region below the film. Therefore, the write protection voltage can be reliably applied to cells that are not to be written. As a result, it is possible to more reliably prevent erroneous writing to the non-selected cells. 2 ) A ferroelectric non-volatile memory device according to the present invention comprises a ferroelectric transistor portion having a ferroelectric film and a selection transistor portion for interrupting a write protection voltage to the ferroelectric transistor portion. In the ferroelectric non-volatile memory device in which the cells arranged in a matrix are arranged, the cells located in the column direction among the cells arranged in the matrix have the same control gate electrode of the ferroelectric transistor section. Among the cells arranged in the matrix, the drain region of the ferroelectric transistor portion is connected to the line and the gate electrode of the selection transistor portion is connected to the same word line. When connected to the same bit line and writing data, apply the following voltage and write voltage In the ferroelectric non-volatile memory device for writing information only to the cell to be written, by preventing the voltage from being applied to the ferroelectric film of the cell, 1) the word line to which the control gate electrode of the cell to be written is connected A write voltage higher than the coercive voltage, 2) a write protection voltage to bit lines other than the bit line to which the write-scheduled cell is connected, and 3) a select transistor to a word line to which the gate electrode of the write-scheduled cell is connected. Has a voltage applying means for applying a voltage for turning on, and the threshold voltage for forming an electric path in the substrate region below the ferroelectric film of the ferroelectric transistor is higher than the coercive voltage of the ferroelectric film. It is set to a low level, and the voltage applying means is connected to the word line to which the control gate electrode of the cell to be written is connected. An inversion layer is formed in the substrate region below the ferroelectric film of a cell not to be written, and the inversion layer applies a write prevention voltage applied to a bit line other than the bit line to which the cell to be written is connected. As time passes so that the coercive voltage is reached after being applied to the substrate region under the film.
A voltage having a waveform whose value becomes higher is applied . in this way,
In the cells not to be written, an inversion layer is formed in the substrate region below the ferroelectric film, and the inversion layer applies a write protection voltage to the substrate region below the ferroelectric film, which corresponds to a coercive electric field. No voltage is applied to the ferroelectric film.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, the ferroelectric non-volatile memory 31
In the P well 2, a source 4 which is a first region and a drain 3 which is a second region are formed in the P well 2. Both the drain 3 and the source 4 are n ⁺ layers. Drain 3, source 4
Channel forming regions 10a, 10b, and 10c are located between them.

A control gate electrode 5 which is a polarization control electrode is provided on the channel forming region 10b. Channel forming region 10b which is an electric path formable region
A ferroelectric film 6 made of PbTiO ₃ which is a ferroelectric material is provided between the control gate electrode 5 and the control gate electrode 5. The channel formation region 10a is covered with an insulating film 8a, and the source gate electrode 7 is provided on the insulating film 8a. Similar to the channel forming region 10a, the channel forming region 10c is also covered with the insulating film 8c, and the drain gate electrode 9 is provided thereon.

N ^{+ type} regions 11a and 11b are provided between the channel forming regions 10a and 10b and between the channel forming regions 10b and 10c, respectively.

The threshold voltage (Vth) for forming a channel (inversion layer) in the channel forming region 10b.
Is set lower than the coercive voltage of the ferroelectric film.

An equivalent circuit 15 of a matrix circuit in which a plurality of ferroelectric non-volatile memories 31 are combined is shown in FIG. 2A.
Here, when they are combined in a matrix as shown in the figure, each control gate electrode 5 is arranged in the row direction and the column direction.
The drain gate electrode 9, the source gate electrode 7, the source 4, and the drain 3 are connected. Since the connection is made in this manner, there is a possibility that data may be written or read in a memory other than the memory in which writing or reading is desired (hereinafter referred to as a selected cell). Therefore, in the equivalent circuit 15, the selected cell can be surely selected as described below (other than the selected cell is hereinafter referred to as a non-selected cell).

FIG. 3B shows an example of voltage applied at the time of writing and reading when the cell C11 is the selected cell.
When writing first, word lines WL1-1, WL
1-2, 5V for bit line BL2, 0 for others
Apply V. The word line WL1- 2, such as shown in FIG. 1B, a voltage obtained by the rise waveform gently.

Returning to FIG. 2A, a potential higher than the potential of the P well 2 by 5 V is applied to the control gate electrode 5 of the selected cell C11. As a result, an electric field is generated between the control gate electrode 5 and the P well 2. As a result, the ferroelectric film 6 is polarized as shown in FIG. 1C (hereinafter referred to as the minus direction), and the cell C11 is in the written state. On the other hand, with respect to the cell C12 which is a non-selected cell, since 5 V is applied to the drain gate 9, a channel is formed in the channel formation region 10c (called an ON state). Furthermore, since 5V is applied to the drain 3,
The channel formation region 10b is turned on. Therefore, 5V is transferred to the channel formation region 10b.

Here, in the control gate electrode 5,
From the word line WL1- 2, gently on the polarization voltage of the rising waveform (see FIG. 1B) is given.

Generally, the ferroelectric film 6 is rapidly polarized when a voltage higher than the voltage corresponding to the coercive electric field is applied,
If the voltage does not correspond to the coercive electric field, it has a property that polarization hardly occurs in a short time (see the E-P hysteresis loop of the ferroelectric film in FIG. 3). On the other hand, when a voltage higher than the threshold voltage (Vth) is applied to the control gate electrode 5, a channel is immediately formed.
Therefore, electrons are rapidly supplied from the drain 3 through the inversion layer of the adjacent channel formation region 10c.
As a result, the inversion layer is formed in the channel formation region 10b. The potential of this portion is equal to the drain potential. Therefore, substantially no voltage corresponding to the coercive electric field is applied to the ferroelectric film 6.

As described above, the threshold voltage (Vt) for forming the channel (inversion layer) in the channel forming region 10b is obtained.
h) is set lower than the coercive voltage of the ferroelectric film,
By applying to the control gate electrode 5 of the non-selected cell a voltage having a smooth rising waveform as shown in FIG. 1B, it is possible to more completely prevent the ferroelectric film 6 of the non-selected cell from being erroneously brought into a written state. can do.

Since 0 V is applied to the control gate electrode 5 and the P well 2 of the cell C14 which is another non-selected cell, the polarization state of the ferroelectric film 6 does not change, and the ferroelectric film 6 is in the written state. I won't. Also, the channel formation region
Since both 10a and 10c are off, erroneous erasure can be prevented.

In order to prevent writing to non-selected cells, the source-gate electrodes 7 of the cells C11 to C14 are turned off for the write-inhibition voltage of 5 V applied to the bit line BL2. It is also held in the channel formation region 10b below the gate electrode 5.

For reading, word line WL1
−1, 5V is applied to WL1-3, a sense amplifier is connected to the bit line BL1, and 0V is applied to the others.

Looking at the selected cell C11, by applying 5V to the word lines WL1-1 and WL1-3, both the channel forming regions 10a and 10c are turned on. If, (1 see D Figure) strength and dielectric film 6 is polarized in the positive direction, the channel formation region 10b is in the OFF state. Therefore, no current flows between the bit line BL1 and the source line S1.

On the other hand, when the ferroelectric film 6 is polarized in the negative direction (see FIG. 1C), the channel forming region 1
0b is turned on, and eventually all the gates are turned on. Therefore, a current flows between the bit line BL1 and the source line S1. That is, when the cell C11 is in the write state, current flows and the potential of the bit line BL1 drops, but in the non-write state, no current flows and no potential drop occurs. By amplifying this difference by the sense amplifier, the state (writing or non-writing) of the cell C11 can be read.

On the other hand, regarding the non-selected cell C12, the channel formation regions 10a and 10c are turned on by applying 5V to the word lines WL1-1 and WL1-3. However, since the potential difference between the bit line BL2 and the source line S1 is 0, the bit line BL2
Current does not flow between the source line S1 and the source line S1. For the other non-selected cells C13 and C14, the word line WL2
Since −1 and WL2-3 are 0 V, both channel formation regions 10a and 10c are in the off state. Therefore,
No current flows between the source line S1 and the bit line BL2 and between the source line S1 and the bit line BL1.

As described above, even when the cells are connected in a matrix, by applying a voltage as shown in FIG. 2B, it is possible to surely write and read only the selected cell.

At the time of erasing, the word line WL1-
2, -5V is applied to WL2-2, and 0V is applied to others. Regarding the selected cells C11 and C12, 0V is applied to the P well PW and the word lines WL1-2 and WL2-.
Will applying -5V to 2, the ferroelectric film 6 by an electric field effect is polarized in the positive direction (see FIG. 1 D), the write state is released.

[Structure of Ferroelectric Nonvolatile Memory 1] A case where another ferroelectric nonvolatile memory is used will be described with reference to FIGS. 4 and 5. In the ferroelectric non-volatile memory 1 shown in FIG. 4, a source 4 as a first region and a drain 3 as a second region are formed in a P well 2. Both the drain 3 and the source 4 are n ⁺ layers. Between the drain 3 and the source 4, an offset region 20a which is a first electric path formable region, a channel forming region 10b which is a second electric path formable region, and a channel forming region which is a third electric path formable region. 10c is formed.

The channel forming region 10c is covered with an insulating film 8, and a select gate electrode 9 which is a control electrode for forming an electric path is provided on the insulating film 8. The channel forming region 10b is covered with an insulating film 26 made of a material having a high relative dielectric constant. The insulating film 26 also covers a part of the select gate electrode 9. Further, the insulating film 26 is covered with the ferroelectric film 6 made of PZT which is a ferroelectric material. A control gate electrode 5 serving as a polarization control electrode is provided on the ferroelectric film 6 and on the channel forming region 10b and the select gate electrode 9.

An insulating sidewall 23, which is an insulating sidewall, is provided on the offset region 20a. The control gate electrode 5 and the insulating sidewall 23 are adjacent to each other as shown in FIG.

The insulating sidewall 23, the control gate electrode 5, and the select gate electrode 9 are covered with an interlayer film 24 which is a protective film. A bit line 29, which is an aluminum film, is provided on the interlayer film 24.
Each drain 3 required for matrix connection is connected.

The principle of writing and erasing operations of the ferroelectric non-volatile memory 1 will be described. When writing to the ferroelectric non-volatile memory 1, a ground potential is applied to the P well 2 and a program voltage sufficiently higher than the coercive voltage is applied to the control gate electrode 5. At this time, the electric field generated between the control gate electrode 5 and the P well 2 polarizes the ferroelectric film 6 in the same direction as the direction of the generated electric field. The lower part of the control gate electrode 5 is depleted depending on the polarization state. Hereinafter, this state is referred to as a writing state. Even if the program voltage is cut off, the polarization state remains almost unchanged.

On the other hand, in the case of erasing, the ground potential is applied to the control gate electrode 5 and the program voltage sufficiently higher than the coercive voltage is applied to the P well 2, contrary to the writing operation. At this time, an electric field in the opposite direction to that at the time of writing is generated between the control gate electrode 5 and the P well 2. Therefore, the polarization state of the ferroelectric film 6 is reversed by this electric field. Even if the program voltage is cut off, the reversed polarization state is maintained.

Next, the read operation of the ferroelectric non-volatile memory 1 will be described. A voltage exceeding the threshold value is applied to the select gate electrode 9. Thereby, the selection gate electrode 9
An inversion layer is formed underneath. Further, a read voltage higher than that of the P well 2 is applied to the source 4. This allows
The depletion layer between the source 4 and the P well 2 expands. A ground voltage is applied to the P well 2 and the drain 3.

Here, if the ferroelectric film 6 is polarized as shown in FIG. 1C (hereinafter referred to as negative polarization),
The lower part of the control gate electrode 5 is depleted. Therefore, the depletion layer between the source 4 and the P well 2, the depletion layer under the control gate electrode 5, and the depletion layer under the select gate electrode 9 are connected, and all the offset regions 20a and the channel formation regions 10b, 10c are turned on. . Here, since the potential of the source 4 is higher than the potential of the drain 3,
A current flows between the source 4 and the drain 3.

As described above, by applying the read voltage to the source 4 when reading, the offset region 20
As the depletion layer of a expands, this voltage can be used as a detection voltage for checking whether or not there is a written state.

On the other hand, when the ferroelectric film 6 is polarized as shown in FIG. 1D (hereinafter referred to as positive polarization), the lower part of the control gate electrode 5 is not depleted. Therefore, the depletion layer between the source 4 and the P well 2 and the depletion layer below the selection gate electrode 9 are not connected, and even if the potential of the source 4 is higher than the potential of the drain 3, a current flows between the source 4 and the drain 3. Not flowing.

A voltage capable of connecting the depletion layer between the source 4 and the P well 2 and the depletion layer under the control gate electrode 5 is called a read voltage.

Thus, the ferroelectric nonvolatile memory 1
Once the write state is set, the write state is maintained even if the supply of the voltage to the control gate electrode 5 is stopped. Whether or not the data has been written is determined by turning on the channel formation region 10c and turning on the source 4
It is possible to judge whether or not the current flows between the source 4 and the drain 3 by turning on the offset region 20a by applying the read voltage to the.

In the case of erasing, a higher potential than the control gate electrode 5 is applied to the P well 2. Accordingly, the ferroelectric film 6 is polarized in the positive direction (see FIG. 1 D), the write state is released.

[Operation of Ferroelectric Nonvolatile Memory 1 Connected in Matrix] The above ferroelectric nonvolatile memory 1 is used by being connected in a matrix. FIG. 5A shows an equivalent circuit 21 of a matrix circuit in which a plurality of ferroelectric non-volatile memories 1 are combined. Here, when combined in a matrix as shown in the figure, the control gate electrodes 5, the selection gate electrodes 9, and the drains 3 are connected in the row direction and the column direction, respectively, and all the sources 4 are connected.
Are connected. Therefore, there is a possibility that data may be written in or read from the non-selected cells. Therefore, in the equivalent circuit 21, as described below,
The selected cell and the non-selected cell can be surely distinguished.

FIG. 9B shows an example of voltage applied at the time of writing and reading when the cell C11 is the selected cell. First, in the case of writing, batch erasing is performed and the direction of polarization is set to the non-writing state. Next, Vc is applied to the word lines WL1n and WL2n and the bit line BLn + 1.
c, and 0V is applied to the others. It should be noted that the word line WL2n is supplied with a polarization voltage (see FIG. 1B) having a smooth rising waveform.

Looking at the selected cell C11, by applying Vcc to the word line WL2n, as shown in FIG.
As shown in, the control gate electrode 5 is applied with a potential higher than the P well 2 by Vcc. Therefore,
An electric field is generated between the control gate electrode 5 and the P well 2, and the ferroelectric film 6 is polarized in the negative direction (see FIG. 6B).

On the other hand, regarding the cell C12 which is a non-selected cell, when Vcc is applied to the word line WL1n, Vcc is also applied to the selection gate electrode 9 of the cell C12 as shown in FIG. 6C. . Therefore, the channel forming region 10c is turned on. Further, since Vcc is applied to the drain 3, the channel forming region 10b is turned on, and the channel forming region 10b is turned on.
Vcc is transferred to b. Therefore, even if Vcc is applied to the control gate electrode 5, no potential difference occurs between the control gate electrode 5 and the P well 2. Therefore, the ferroelectric film 6 is not polarized and is not in a written state.

By the way, to the control gate electrode 5 of the cell C12, a polarization voltage having a gentle rising waveform (see FIG. 1B) is applied from the word line WL2n.

As described above, the ferroelectric film 6 is rapidly polarized when a voltage equal to or higher than the voltage corresponding to the coercive electric field is applied, and if the voltage is not equivalent to the coercive electric field, the ferroelectric film 6 is short-timed. Has a property that almost no polarization occurs (see the E-P hysteresis loop of the ferroelectric film in FIG. 3). On the other hand, when a voltage higher than the threshold voltage (Vth) is applied to the control gate electrode 5, a channel is immediately formed. Therefore, electrons are rapidly supplied from the drain 3 through the inversion layer of the adjacent channel formation region 10c, and the inversion layer is formed in the channel formation region 10b. The potential of this portion is equal to the drain potential. Therefore, substantially no voltage corresponding to the coercive electric field is applied to the ferroelectric film 6.

As described above, the threshold voltage (Vt) for forming the channel (inversion layer) in the channel forming region 10b is obtained.
h) is set lower than the coercive voltage of the ferroelectric film,
By applying to the control gate electrode 5 of the non-selected cell a voltage having a smooth rising waveform as shown in FIG. 1B, it is possible to more completely prevent the ferroelectric film 6 of the non-selected cell from being erroneously brought into a written state. can do.

The write inhibit voltage Vcc applied to the bit line BLn + 1 in order to prevent writing.
Regarding (see FIG. 5B), since the offset regions 20a of the cells C11 to C14 are in the off state, they are also held in the channel formation region 10b below the control gate electrode 5.

Reading is performed as follows. As shown in FIG. 5B, Vc is applied to the word line WL1n.
c, Vcc (read voltage) is applied to the source line SL, and 0 V is applied to the others, and a sense amplifier is connected to the bit line BLn.

In the selected cell C11, by applying Vcc as a read voltage to the source line SL, the depletion layer expands as shown in FIG. 7A, and the offset region 20a is turned on. Also, the word line WL1
By applying Vcc to n, Vc is applied to the select gate 9.
c is applied, and the channel formation region 10c is turned on. Here, when the ferroelectric film 6 is polarized in the negative direction (see FIG. 1C), the channel forming region 10b is turned on. That is, both the offset region 20a and the channel forming regions 10b and 10c are turned on.
Therefore, a current flows through the source line SL and the bit line BLn, and this current can be detected by the sense amplifier.

On the other hand, when the ferroelectric film 6 is polarized in the positive direction (see FIG. 1D), the channel forming region 10b is not turned on as shown in FIG. 7B. Therefore, no current flows between the source line SL and the bit line BLn even when the offset region 20a and the channel formation region 10c are in the ON state.

With respect to the non-selected cell C12, even if the offset region 20a and the channel forming regions 10b and 10c are both in the ON state, the sense amplifier is connected to the bit line BLn, so that it is erroneously read. It will not be done. The same applies when the bit line BLn + 1 is opened.

Looking at the other non-selected cells C13 and C14, both of the channel forming regions 10c are in the off state because 0 V is applied to the word line WL2n. Therefore, between the source line SL and the bit line BLn, between the source line SL and the bit line BL.
No current flows between n + 1.

As described above, even when the ferroelectric non-volatile memories 1 are connected in a matrix, a voltage as shown in FIG. 5B is applied and a channel (inversion layer) is formed in the channel formation region 10b. Threshold voltage (V
th) is set to be lower than the coercive voltage of the ferroelectric film 6 and the rising voltage is smoothed (see FIG. 1B).
By applying, it becomes possible to surely write and read only the selected cell.

When erasing, the word line WL2
-Vcc is applied to n and WL2n + 1, and 0V is applied to the others. As a result, the ferroelectric film 6 is polarized in the positive direction (see FIG. 1D) and can be erased at once.

As described above, the ferroelectric non-volatile memory 1 forms the offset region 20a by providing the insulating sidewall 23. Then, at the time of reading, by applying a read voltage to the source 4, the depletion layer is expanded, a channel is formed in the offset region 20a, and this voltage can be used as a detection voltage for checking the presence or absence of the written state. .

Further, a threshold voltage (Vth) for forming a channel (inversion layer) in the channel forming region 10b.
Is set to be lower than the coercive voltage of the ferroelectric film 6 and a polarization voltage having a smooth rising waveform is applied to the control gate electrode 5, so that a voltage corresponding to the coercive electric field is applied to the ferroelectric film 6. An inversion layer can be formed under the control gate electrode 5. Therefore, erroneous writing can be prevented more reliably.

In this embodiment, PZT (lead zirconate titanate) was used as the ferroelectric substance.
iO ₃ , barium titanate, bismuth titanate, PLZ
Other substances may be used as long as they show a ferroelectric property such as T. Further, in order to avoid the problem of soft writing, it is desirable to use a material having a large activation electric field and to form so that the activation electric field becomes large.

Here, the soft write means that the polarization state of the ferroelectric film 6 on the channel forming region 10b is gradually inverted every time a program voltage is applied to the control gate electrode 5 of the non-selected cell during writing. It means to do. When soft writing is repeated, the polarization state may finally be completely inverted, and the data in that cell may become incorrect.

However, when the polarization state of the ferroelectric film 6 is reversed in the non-selected cells by adjusting the threshold voltage and applying a voltage with a smooth rising waveform, the channel forming region 10b is inverted. By forming an inversion layer on the substrate, erroneous writing and soft writing can be prevented more reliably.

In each of the above embodiments, the N-channel transistor is explained, but it may be adopted as a P-channel transistor.

[0070]

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a ferroelectric nonvolatile memory 31, a waveform of a voltage applied to a polarization control electrode, and a polarization state of a ferroelectric film 6.

FIG. 2 is a usage state diagram of a ferroelectric non-volatile memory 31. A is an equivalent circuit diagram combined in a matrix, and B is an example showing the voltage in each operation.

FIG. 3 is a diagram showing a hysteresis loop of a ferroelectric film 6.

FIG. 4 is a diagram showing a structure of a ferroelectric nonvolatile memory 1.

FIG. 5 is a usage state diagram of the ferroelectric nonvolatile memory 1. A is an equivalent circuit diagram combined in a matrix, and B is an example showing the voltage in each operation.

FIG. 6 is a diagram showing the ferroelectric non-volatile memory 1 at the time of writing. 8A and 8B are diagrams showing states of a depletion layer in a written state. A indicates a selected cell and C indicates a non-selected cell. Also,
B and D are diagrams showing the polarization state of the ferroelectric film 6, where B is the polarization in the minus direction and D is the polarization in the plus direction.

FIG. 7 is a ferroelectric non-volatile memory 1 at the time of reading.
It is a figure which shows the state of the depletion layer. When A is a writing state, B is a non-writing state.

FIG. 8 is a diagram showing a structure of a conventional nonvolatile memory 41 and a polarization state of a ferroelectric film 6.

FIG. 9 is a diagram showing an equivalent circuit in which a plurality of conventional nonvolatile memories 41 are combined.

[Explanation of symbols]

3 ... drain 4 ... sauce 5 ... Control gate electrode 6 ... Ferroelectric film 9 ... Select gate electrode 10b, 10c ... Channel forming region 20a ... Offset area 23 ... Insulating sidewall

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/792

Claims (2)

(57) [Claims] 1. A ferroelectric non-volatile memory device in which cells having ferroelectric transistors are arranged in a matrix, and when data is written, a ferroelectric film of a cell to be written is written with a voltage larger than a coercive voltage. In addition to applying a voltage to the ferroelectric film of the cell in which writing is desired to be prevented, a write-inhibiting voltage is applied to the substrate region below the ferroelectric film so that the write voltage is the ferroelectric film of the cell. In a ferroelectric non-volatile memory device that writes information only in the cell to be written so that it is not applied to the memory cell, the threshold voltage for forming an electric path in the substrate region below the ferroelectric film of the ferroelectric transistor. It is set lower than the coercive voltage of the ferroelectric film, as the write voltage, the cell <br/> Le want to prevent the write phase to the coercive field Before the voltage is applied to the ferroelectric film, an inversion layer is formed in the substrate region below the ferroelectric film of the cell, and the write protection voltage is applied to the substrate region below the ferroelectric film by this inversion layer. Do, that it is adapted to be supplied with a voltage value is increased with the lapse of time, the ferroelectric non-volatile memory device according to claim. 2. A ferroelectric non-volatile memory device in which cells are arranged in a matrix, wherein each cell has a ferroelectric transistor portion having a ferroelectric film, and writing prevention to the ferroelectric transistor portion. In the cell arranged in the column direction among the cells arranged in a matrix, the control gate electrode of the ferroelectric transistor section is connected to the same word line. And the gate electrodes of the select transistor portions are connected to the same word line, and among the cells arranged in the matrix, the cells located in the row direction have the drain regions of the ferroelectric transistor portions connected to the same bit line. When writing data, the following voltage is applied and the write voltage is the ferroelectric substance of the cell. In a ferroelectric non-volatile memory device that writes information only to cells to be written so that it is not applied to the film, 1) Write voltage greater than the coercive voltage to the word line to which the control gate electrode of the cells to be written is connected. 2) write-protection voltage is applied to the bit lines other than the bit line to which the write-scheduled cell is connected, and 3) voltage to turn on the select transistor is applied to the word-line to which the gate electrode of the write-scheduled cell is connected. A threshold voltage for forming an electric path in the substrate region under the ferroelectric film of the ferroelectric transistor is set lower than the coercive voltage of the ferroelectric film, The voltage applying means does not write to the word line to which the control gate electrode of the write-scheduled cell is connected. An inversion layer is formed in the substrate region below the ferroelectric film of the cell, and the write prevention voltage applied to the bit line other than the bit line connected to the write-scheduled cell by the inversion layer is applied to the lower part of the ferroelectric film. The time required to reach the coercive voltage after being applied to the substrate area
It is possible to apply a voltage with a waveform whose value increases with the passage of
And a ferroelectric non-volatile memory device.