KR20000018679A - Non-volatile memory device having ferroelectrics capacitor - Google Patents

Abstract

PURPOSE: A non-volatile memory device is provided, which uses a ferroelectrics capacitor. CONSTITUTION: A non-volatile memory device comprises: an array of a memory cell(MC) having a ferroelectrics capacitor and a switching transistor; a sense amplifier (10) to be connected to the array of the memory cell (MC) and for sensing a voltage difference of a voltage corresponding to data stored in the memory cell (MC) and a reference voltage to amplify the voltage difference; and a reference voltage supplying unit to be connected to the sense amplifier (10) and for providing the reference voltage, including a plurality of first ferroelectrics capacitors to be connected in parallel order each other, a first switching transistor to be connected between reference plate lines; a plurality of second ferroelectrics capacitors to be connected in serial order each other, and a second switching transistor to be connected between reference plate lines. Thereby, it is possible to prevent a depolarization generated by a secondary phase.

Description

NONVOLATILE MEMORY DEVICE WITH FERROELECTRIC CAPACITOR

The present invention relates to a nonvolatile memory device, and more particularly, to a ferroelectric memory device using a ferroelectric capacitor.

Recently, nonvolatile memories having the ability to retain data even at power off have been realized through the use of ferroelectric materials, such as PZTs, which exhibit hysteresis characteristics. By using such ferroelectric materials in the memory cell, the nonvolatile memory can be implemented with a simple structure. Ferroelectric Random Access Memory (FRAM) is non-volatile, and high-speed, low-voltage operation is drawing attention and competition from many memory chip makers.

A memory cell composed of a ferroelectric capacitor and a switching transistor stores a logical state ('1' or '0') of data according to an electrical polarization state of a ferroelectric capacitor (C _F ). When a voltage is applied across the ferroelectric capacitor C _F , the ferroelectric material is polarized according to the direction of the electric field, and a forced voltage is applied to a switching threshold voltage at which the polarization state changes. It is called (coercive voltage). In order to read the data stored in the memory cell, a voltage difference between the positive electrodes of the ferroelectric capacitor is applied to change the amount of charge excited on the bit line, thereby detecting the state of the data stored in the memory cell. Some examples of such applications are described in Japanese Patent NOs. 63-201998 and 1-158691, and in the paper "A 256 Kb Non-volatile Ferroelectric Memory at 3 V and 100 ns" (ISSCC, Digest of Technical Papers, pp.268-269, 1994, February).

1 shows a 1T / 1C ferroelectric memory cell. The memory cell MC is composed of one switching transistor Tr and one ferroelectric capacitor C _F (1 transistor and 1 capacitor per 1 bit: 1T / 1C). The switching transistor Tr has two main electrodes connected to one electrode of the ferroelectric capacitor C _F and the bit line BL, that is, a drain electrode and a source electrode, and a gate electrode connected to the word line WL. Has The other electrode of the ferroelectric capacitor C _F is connected to the plate line PL.

2 is a graph showing hysteresis characteristics of a ferroelectric capacitor. The abscissa of the graph represents the potential difference between the two electrodes of the capacitor, i.e. the voltages across the capacitor, and the ordinate is organic to its surface according to the spontaneous polarization of the ferroelectric material. The amount of charge to be made, that is, the degree of polarization (μC / cm ² )

If a voltage of 0 V is applied so that no electric field is applied to the ferroelectric material, the polarization domains are generally non-uniform and no polarization occurs. When the voltage across the capacitor increases in the positive direction, the polarization degree (or amount of charge) increases from zero to point A in the positive polarization region. At point A, all domains are polarized in one direction and the degree of polarization at point A reaches a maximum. At this time, the polarization degree, that is, the amount of charge retained by the ferroelectric material is represented by Q _S , and the magnitude of the voltage applied across the capacitor is the operating voltage Vcc. Thereafter, even if the voltage across the capacitor drops back to 0V, the polarization degree does not decrease to 0 but remains at point B. According to such residual polarization, the amount of charge possessed by the ferroelectric material, that is, the residual polarization degree, is represented by Qr. Next, as the voltage across the capacitor increases in the negative direction, the polarization degree changes from point B to point C in the negative charge polarization region (curve 21 in FIG. 2). At point C, all domains of the ferroelectric material are polarized in a direction opposite to the direction of polarization at point A. In this case, the polarization degree is represented by -Q _S , and the magnitude of the voltage applied across the capacitor is -Vcc. Then, even if the voltage across the capacitor drops back to 0V, the polarization value does not drop to 0 but remains at point D. Residual polarization degree at this time is represented by -Qr. When the magnitude of the voltage across the capacitor once again increases in the positive direction, the polarization of the ferroelectric material changes from point D to point A.

As described above, when a voltage for generating an electric field is applied once to a ferroelectric capacitor having a ferroelectric material inserted between two electrodes, the polarization direction according to spontaneous polarization is maintained even after the electrodes are set to a floating state. do. The surface charge of the ferroelectric material due to spontaneous polarization is not naturally lost by leakage or the like. If no voltage is applied in the opposite direction such that the polarization degree is zero, the polarization direction is maintained as it is.

Next, writing / reading of the FRAM is performed by polarization inversion as described above. Thus, the operating speed of the FRAM is determined by the polarization inversion time. The polarization inversion rate of the ferroelectric capacitor is determined according to the area of the capacitor, the thickness of the ferroelectric thin film, the applied voltage, and the like, but is usually in the unit of ns. This means that it can run much faster than EEPROM or flash memory with read / write times in milliseconds.

Referring back to FIG. 2, assume that data '1' is stored in the ferroelectric capacitor C _F having the polarization state at point B. As the high voltage level (here, the power supply voltage: Vcc) is applied to the word line WL, the switching transistor Tr is conducted, and the negative voltage (-Vcc) is connected to the bit line BL and the plate line PL. through change of a ferroelectric capacitor (C _F), when applied to the ferroelectric capacitor (C _F) polarization (P) is the state that (B) state point (D) via the state point (C) in the. The charge dQ1 corresponding to this state transition is transferred between the bit line BL and the ferroelectric capacitor C _F through the switching transistor Tr. Charge transfer is detected by the sense amplifier (see FIG. 3) connected with the bit line BL, which means that the data value '1' has been read from the memory cell MC. After reading data '1' from the memory cell MC, the same data '1' on the bit line BL is written back to the memory cell MC by lowering the voltage of the plate line PL. . This write result involves reverse state transient from state point D to state point A. FIG.

On the other hand, if the data '0' is stored in the ferroelectric capacitor C _F with the polarization state at point D, as in the previous assumption, the high voltage level (here, the supply voltage Vcc) goes to the word line WL. When applied, the switching transistor Tr conducts (ON) and when a negative voltage is applied to the ferroelectric capacitor C _F via the bit line BL and the plate line PL, its polarization P is in a state Change from point (D) to status point (C) and then return to status point (D) again. The charge dQ0 corresponding to this state transition is transferred between the bit line BL and the ferroelectric capacitor C _F through the switching transistor Tr. The charge transfer is detected by the sense amplifier (see FIG. 3) connected with the bit line BL, which means that the data value '0' is read out from the memory cell MC.

As is well known to those skilled in the art, the 2T / 2C scheme is inadequate for highly integrated ferroelectric memory devices because reference cells corresponding to the number of memory cells are required. On the other hand, the above-described 1T / 1C scheme is suitable for highly integrated ferroelectric memory devices because only one reference cell corresponding to a plurality of memory cells is required. Here, the reference cell, as shown in Figure 3, is composed of a ferroelectric capacitor and a switching transistor having the same characteristics as the memory cell.

According to the conventional reference cell structure configured as shown in FIG. 3, the following problems may be caused.

1. If the characteristic of the reference cell is weak, the corresponding columns, i.e., bit lines (e.g., BL1 and BL2), are also weak.

2. Because the reference cell is distributed at the edge of the cell layer, there can always be secondary phase and process problems due to step differences.

3. The high and low address pins constantly change the fatigue characteristics of the reference cell, affecting device reliability.

4. If an abnormality occurs in the imprint and coercive voltage of the reference cell, it affects the corresponding memory cell.

Accordingly, an object of the present invention is to provide a nonvolatile memory device having improved reliability.

1 is a circuit diagram showing a memory cell of a basic 1T / 1C structure;

2 shows the hysteresis characteristics of ferroelectric materials;

3 is a block diagram showing a configuration of a nonvolatile memory device according to the prior art;

4 is a block diagram showing a configuration of a nonvolatile memory device according to the present invention; And

5 is a diagram illustrating a secondary phase according to a step.

* Explanation of symbols on the main parts of the drawings

MC: memory cell 10: sense amplifier

(Configuration)

According to an aspect of the present invention for achieving the above object, a ferroelectric memory device comprising: an array of memory cells each consisting of a ferroelectric capacitor and a switching transistor; A sense amplifier coupled to the array for sensing and amplifying a voltage difference between a voltage corresponding to data stored in one selected memory cell and a predetermined reference voltage; A reference voltage supply coupled to the sense amplifier, the reference voltage supply providing the reference voltage; The reference voltage supply unit includes a plurality of first ferroelectric capacitors connected in series, a first switching transistor connected between a first reference bit line and a reference plate line through the first ferroelectric capacitors, and a plurality of second connected in series. And a second switching transistor connected between the ferroelectric capacitors and the reference plate line through the second reference bit line and the second ferroelectric capacitors.

In this embodiment, the first and second switching transistors of the reference voltage supply are switched on / off at the same time by the reference word line.

In this embodiment, it is characterized in that it further comprises equalization means connected between the first and second reference bit lines, the equalizing means for causing each potential of the reference bit lines to be equal in response to an equalization signal. .

(Action)

By such a device, it is possible to implement a ferroelectric memory device with improved reliability.

(Example)

Hereinafter will be described in detail based on the reference drawings in accordance with an embodiment of the present invention.

In the following description, specific and specific examples are set forth in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the foregoing description without these details.

4 is a block diagram illustrating a configuration of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the memory cell MC is composed of one switching transistor Tr and one ferroelectric capacitor C _F , and its connection relationship is the same as that of FIG. 1. Therefore, the description thereof is omitted here. The sense amplifier circuit 10 is connected to the bit line BL connected to the memory cell MC. Although not shown in the figure, the sense amplifier circuit 10 is composed of a P-latch sense amplifier and an N-latch sense amplifier, an example of which is described in US Pat. No. 5,751,626, entitled "FERROELECTRIC MEMORY USING FERROELECTRIC REFERENCE CELLS."

As shown in FIG. 4, between the first reference bit line RBL1 and the reference plate line RPL, a plurality of series-connected ferroelectric capacitors CF ₁₁ through a switching transistor Tr connected to the line RWL. -(CF _1X ) is connected in series. Each ferroelectric capacitor CF _11- (CF _1X ) has a different polarization amount when polarized. Between the second reference bit line RBL2 and the reference plate line RPL, a plurality of series-connected ferroelectric capacitors CF _1- (CF _0X ) are connected through a switching transistor Tr connected to the line RWL. It is connected in series. Each ferroelectric capacitor CF _1- (CF _0X ) has a different amount of polarization when polarized. An equalization NMOS transistor TEQ connected to the line REQ is connected between the first and second reference bit lines RBL1 and RBL2.

According to this configuration, a plurality of reference cells are commonly tied to cancel a poor ferroelectric capacitor with a good ferroelectric capacitor, which is maintained at a DC level using a generator in a standby state, so that the fatigue characteristics of the reference cell are always optimized. Can be kept in the state of. In addition, the dummy cell may be used to prevent the inhibitory element that inhibits the characteristics of the ferroelectric capacitor generated at the imprint or the edge portion of the memory cell and the reference cells.

When the ferroelectric capacitors are bundled and used as shown in Fig. 4, the capacitor capacity reduction in each domain derived by the voltage drop due to the secondary phase such as the crystal and the fitting of the capacitor due to the secondary phase (splitability) It is possible to recover the capacitor itself with respect to the phenomenon. In order to drive this, when two or more dummy cells are configured in rows and columns on the mat edge where secondary phases are formed, secondary phases entering the memory cell are prevented.

The operation method is as follows. The bias is applied in the standby state and the reference cell is biased by the internal clock. In the pair of reference cells next to the dummy cell, data "1" is simultaneously written by the pulse of the line RRP, and the opposite reference cells are simultaneously written into the data "0" by the pulse of the line RRP. do. These voltages have a value of (ΔQ ₁₁ + ,, + ΔQ _1X + ΔQ ₁ + ,, + ΔQ _0X ) / 2 by the equalization transistor TEQ.

The current level by the equalizing transistor (TEQ) has a current level for half levels of CdV ₁ / dt and CdV ₀ / dt. This level becomes the reference level of the memory cell and always has a constant level through the circuit 12. At power off, the voltage applied to the reference cell is changed by an internal timer (not shown) to prevent the reference cell from fitting to one side.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to cover all such modifications and similar constructions.

Using this reference scheme, you can achieve the following effects: First, it is possible to prevent deterioration of the capacitor capacity and the fatigue characteristics of the reference cell with respect to the pulse of the plate line. That is, since the internal pulse is affected regardless of the pulse applied to the memory cell, the pulse is affected only once for the device operation. Second, the device's activity is increased by securing a free space for the secondary phase generated in the PZT by the dummy cell. Third, depolarization caused by the secondary phase can be prevented.

Claims (3)

In ferroelectric memory devices: An array of memory cells each comprised of a ferroelectric capacitor and a switching transistor; A sense amplifier coupled to the array for sensing and amplifying a voltage difference between a voltage corresponding to data stored in one selected memory cell and a predetermined reference voltage; A reference voltage supply coupled to the sense amplifier, the reference voltage supply providing the reference voltage; The reference voltage supply unit includes a plurality of first ferroelectric capacitors connected in series, a first switching transistor connected between a first reference bit line and a reference plate line through the first ferroelectric capacitors, and a plurality of second connected in series. And a second switching transistor connected between the ferroelectric capacitors and the reference plate line through the second reference bit line and the second ferroelectric capacitors. The method of claim 1, And the first and second switching transistors of the reference voltage supply unit are simultaneously switched on / off by a reference word line. The method of claim 1, And equalization means connected between the first and second reference bit lines, the equalizing means for causing the respective potentials of the reference bit lines to be equal in response to an equalization signal.