KR101043385B1 - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to prevent the generation of a interference phenomenon between cells while the writing or reading operation of the cells by verifying the storing state of cell data. CONSTITUTION: A channel region(10) is formed on a semiconductor substrate and is in connection with a bit-line(BL). A drain region(11) and a source region(12) are in connection with both sides of the channel region. A ferroelectric layer(13) is formed on the upper side of the channel region. A word-line(14) is formed on the upper side of the ferroelectric layer. An insulating layer is formed between the channel region and the ferroelectric layer.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and is a technique for reducing interference between cells in a nonvolatile memory device such as a ferroelectric memory.

In general, a cache memory device that is a high-speed memory device that temporarily stores a part of data in order to improve the speed of data may include DRAM, SRAM, and FeRAM. Also, nonvolatile memory devices that maintain a stored state of input information even when the power is cut off may include a PRAM, an MRAM, a FeRAM, and a flash memory.

The above-mentioned nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about dynamic random access memory (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure similar to that of a DRAM, and uses a ferroelectric material as a capacitor material, and uses a high residual polarization characteristic of the ferroelectric material. This residual polarization does not erase the data even when the electric field is removed.

The 1T1C (1-Transistor 1-Capacitor) unit cell of the conventional nonvolatile ferroelectric memory device includes a switching element for switching a bit line and a nonvolatile ferroelectric capacitor by switching according to a state of a word line, and a switching element. And a nonvolatile ferroelectric capacitor connected between one end of the plate line and the plate line. Here, the switching element of the conventional nonvolatile ferroelectric memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

1A and 1B are cross-sectional views of a cell of a semiconductor memory device according to the prior art.

The conventional 1-T (FET) field effect transistor (FET) type unit cell has a P-type channel region 2, an N-type drain region 3, and an N-type source region 4 on the semiconductor substrate 1. ) Is formed.

Here, the N-type drain region 3 is connected to the bit line BL on the cell array. In addition, a bias of the semiconductor substrate 1 is commonly applied to silicon of the P-type channel region 2.

In addition, a ferroelectric layer 5 is formed on the channel region 2. In addition, a word line 6 that is a control gate is formed on the ferroelectric layer 5.

In addition, the unit cell illustrated in FIG. 1B indicates that an insulation layer 5 is formed between the P-type channel region 2 and the ferroelectric layer 5.

A conventional semiconductor memory device having such a configuration reads / writes data using a characteristic in which a channel resistance of a memory cell varies depending on a polarization state of the ferroelectric layer 5.

That is, when the polarity of the ferroelectric layer 5 induces positive charge in the channel region 2, the memory cell is turned off due to a high resistance state. On the contrary, when the polarity of the ferroelectric layer 5 induces negative charge in the channel region 2, the memory cell is turned into a low resistance state.

However, in such a conventional semiconductor memory device, when the cell size becomes small, data retention characteristics are deteriorated, so that normal cell operation becomes difficult. That is, when a cell read operation, voltage is applied to an adjacent cell, and data is destroyed, thereby causing interface noise between cells. In addition, since a write voltage is applied to an unselected cell during the write operation of the cell, data of the unselected cells is destroyed, making it difficult to perform a random access operation.

The present invention has the following object.

First, an object of the present invention is to connect a channel region of a cell with a bit line so that a program voltage can be applied by a channel bias voltage.

Second, an object of the present invention is to apply a program voltage by a channel bias voltage and to grasp a storage state of cell data so as to prevent interference between cells during a write or read operation of the cell.

A semiconductor memory device of the present invention for achieving the above object, the channel region formed on the semiconductor substrate and connected to the bit line; A drain region and a source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region and having a polarization state changed according to a voltage applied from the bit line; And a word line formed on the ferroelectric layer, and a read or write operation of data is performed according to a voltage applied from the bit line to the channel region and a voltage applied to the word line.

In addition, the semiconductor memory device of the present invention includes a read write bit line; A unit cell in which data read or write operations are performed according to a voltage applied from a bit line to a channel region; A selection switch connected between one end of the unit cell and the read write bit line and controlled by the word line; And a source line connected to the other end of the unit cell, wherein the unit cell is formed on the semiconductor substrate and connected to the bit line; A drain region and a source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region and having a polarization state changed according to a voltage applied from the bit line; And a word line formed on the ferroelectric layer, and a read or write operation of data is performed according to a voltage applied from the bit line to the channel region and a voltage applied to the word line.

In addition, the present invention is a lead write bit line; A select switch connected to the read write bit line and controlled by the word line; A plurality of unit cells connected in series between one end of the selection switch and the source line and controlled by a word line, and configured to read or write data according to voltages applied to respective channel regions from the plurality of bit lines; And a source line connected to the other end of the plurality of unit cells, each of the plurality of unit cells being formed on a semiconductor substrate and connected to a bit line; A drain region and a source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region and having a polarization state changed according to a voltage applied from the bit line; And a word line formed on the ferroelectric layer.

The present invention has the following effects.

First, the present invention reduces the interface noise generated between cells by connecting a channel region of a cell to a bit line and applying a program voltage by a channel bias voltage.

Second, the present invention provides an effect of applying the program voltage by the channel bias voltage and grasping the storage state of the cell data to prevent interference between cells during the write or read operation of the cell.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such configuration changes, etc. It should be seen as belonging to a range.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are cross-sectional views of cells of a semiconductor memory device according to the present invention.

The 1-T (FET) field effect transistor (FET) type unit cell according to the present invention includes a P-type channel region 10, an N-type drain region 11, and an N-type source region 12 on a semiconductor substrate. Is formed.

Here, the P-type channel region 10 is connected to the bit line BL on the cell array. In addition, silicon of the P-type channel region 10 is connected in a column direction and used as a line for transmitting a signal of the bit line BL.

A ferroelectric layer 13 is formed on the channel region 10, and a word line 14, which is a control gate, is formed on the ferroelectric layer 13.

In addition, the unit cell illustrated in FIG. 2B indicates that an insulation layer 15 is formed between the P-type channel region 10 and the ferroelectric layer 13.

The present invention having such a configuration reads and writes data using the characteristic that the channel resistance of the memory cell varies depending on the polarization state of the ferroelectric layer 13.

That is, when the polarity of the ferroelectric layer 13 induces positive charge in the channel region 10, the memory cell is turned off due to a high resistance state. On the contrary, when the polarity of the ferroelectric layer 13 induces a negative charge in the channel region 10, the memory cell is turned into a low resistance state.

3 is a block diagram illustrating a cell array of a semiconductor memory device according to the present invention.

In the cell array of the present invention, a plurality of word lines WL0 to WL2 are arranged in the row direction. Then, the read write bit lines RWBL, the plurality of bit lines BL0 to BLn, and the source line SL are arranged in the column direction.

A plurality of unit cells C are formed in an area where the plurality of word lines WL0 to WL2 and the plurality of bit lines BL0 to BLn intersect. Here, the unit cell C has the cell cross-sectional structure of FIG. 2A or 2B. The select switch T is formed in an area where the read write bit line RWBL and the plurality of word lines WL0 to WL2 intersect.

In addition, the sense amplifier SA is connected to the read write bit line RWBL to sense and amplify cell data applied from the read write bit line RWBL. Accordingly, the cell data '1' and the data '0' can be distinguished.

The plurality of write drivers WD are connected in one-to-one correspondence with the plurality of bit lines BL0 to BLn. When the data write unit WD writes data to the memory cell, the write driver WD generates a driving voltage according to the write data and supplies it to the bit line BL.

Here, the select switch T is connected between the lead write bit line RWBL and the drain terminal 11 of the unit cell C so that the gate terminal is connected to the word line WL.

In the unit cell C, a plurality of unit cells C are connected in series between one end of the selection switch T and the source line SL. That is, the drain region 11, the channel region 10, and the source region 12 of each unit cell C may be connected in series in the row direction. Gate terminals of the plurality of unit cells C are connected to the word line WL. The channel regions 10 of the plurality of unit cells C are connected to the bit line BL.

The plurality of unit cells C arranged in the column direction are connected to the same bit line BL (eg, bit line BL0). The plurality of unit cells C arranged in the row direction are connected to bit lines BL (for example, bit lines BL0 to BLn) having different channel regions.

4 illustrates a structure of a polysilicon layer in a semiconductor memory device according to the present invention.

In the cell array of the present invention, a plurality of word lines WL0 to WL4 are arranged in the row direction. A plurality of bit lines BL0 to BL3 are arranged in the column direction.

Here, the silicon region of the P-type channel region 10 is connected in the column direction and is used as a line for transmitting a signal of the bit line BL. The P-type channel region 10 is connected to only the P-type channel regions 10 arranged in the column direction, and the P-type channel regions 10 in the row direction are separated from each other.

The silicon regions of the N-type drain region 11 and the N-type source region 12 are connected in the row direction, and are separated from each other in the column direction from the other N-type drain region 11 and the N-type source region 12. do.

5 is a view for explaining an operation characteristic of a cell in a semiconductor memory device according to the present invention.

When the voltage of the bit line BL is 0V, the threshold voltages Vt of the unit cells all have negative voltages. That is, the threshold voltage Vt0 of the data '0' and the threshold voltage Vt1 of the data '1' are both negative voltage values.

In particular, the threshold voltage Vt1 of the data '1' is set to have a voltage value smaller than the threshold voltage Vt0 of the data '0'. Therefore, in order to satisfy the condition of the reference threshold voltage Vtref, which is a reference threshold voltage Vt, in the read operation mode, the voltage of the bit line BL should be set to a negative read voltage -Vread value.

That is, when a bias voltage is applied as a negative voltage to the P-type channel region 10 in the unit cell C, as the negative absolute voltage value (for example, the voltage -VBL) increases, the threshold voltage of the unit cell ( Vt) is increased.

Accordingly, when the negative voltage -VBL is applied, the threshold voltage Vt of the unit cell is increased, so that all of the unit cells C storing the data '0' or the data '1' are kept turned off.

In addition, when a positive pass voltage Vpass is applied to the bit line BL, the threshold voltage Vt0 of the data '0' and the threshold voltage Vt1 of the data '1' are both negative voltage values. Make it turn on.

In the conventional unit cell, the bias voltage applied to the P-type channel region 2 is fixed, and the on / off characteristic of the cell is adjusted using the gate voltage applied to the word line 8.

However, according to the present invention, the bias voltage applied to the word line 16 is fixed, and the on / off characteristic of the cell is adjusted using the voltage applied to the channel region 10.

FIG. 6 is a diagram illustrating characteristics of a cell current according to a bit line voltage in a semiconductor memory device according to the present invention.

In the read operation mode, a negative read voltage -Vread is applied to the channel region 10 in order to satisfy the condition of the reference threshold voltage Vtref, which is a reference voltage for determining data. In this case, since the bit line BL is connected to the P-type channel region 10, the bit line BL voltage should be applied in the negative voltage region.

That is, when a negative read voltage -Vread is applied to the bit line BL, which is the channel region 10, the cell current of the data '1' becomes larger than the cell current of the data '0'. In addition, when a positive pass voltage Vpass is applied to the bit line BL, the threshold voltage Vt0 of the data '0' and the threshold voltage Vt1 of the data '1' are both negative voltage values. Make it turn on.

An operation process of the present invention having such a configuration and operation characteristics will be described with reference to the timing diagrams of FIGS. 7 and 8 as follows.

First, FIG. 7 is an operation timing diagram in the write operation mode of the semiconductor memory device according to the present invention.

During the write operation of data '1', the read write bit line RWBL maintains the ground voltage GND state. Then, the voltage level of the word line WL transitions to the positive program voltage + VPgm from the ground voltage GND level.

Then, the select switch T is turned on and a positive program voltage + VPgm is applied to the word line WL of the unit cell C.

Then, the voltage level of the bit line BL transitions from the ground voltage GND level to the negative program voltage -VPgm. Then, a negative program voltage -Vpgm is applied to the channel region 10 of the unit cell C. In this case, negative charge is induced in the channel region 10 according to the polarity of the ferroelectric layer 13. As a result, the memory cell is in a low resistance state, so that the channel region 10 is turned on so that the data '1' can be written.

On the other hand, during the write operation of data '0', the read write bit line RWBL maintains the ground voltage GND state. Then, the voltage level of the word line WL transitions from the ground voltage GND level to the negative program voltage -VPgm.

Herein, it is preferable that the negative program voltage -Vpgm is set at a level such that charge can escape from the ferroelectric layer 13. In addition, the negative program voltage -Vgmgm supplied to the word line WL is preferably controlled by the word line driver.

Then, the selector switch T is turned off and a negative program voltage -Vpgm is applied to the word line WL of the unit cell C.

Then, the voltage level of the bit line BL transitions from the ground voltage GND level to the positive program voltage + VPgm. Here, the positive program voltage + VPgm preferably has a word line WL voltage and a voltage level higher than the pass voltage Vpss. The positive program voltage + VPgm supplied to the bit line BL is preferably controlled by the write driver WD.

Then, a positive program voltage + VPgm is applied to the channel region 10 of the unit cell C. In this case, positive charge is induced in the channel region 10 according to the polarity of the ferroelectric layer 13. Accordingly, the memory cell is in a high resistance state and the channel region 10 is turned off so that the data '0' can be written.

8 is an operation timing diagram in a read operation mode of a semiconductor memory device according to the present invention.

During the data read operation, the read write bit line RWBL transitions to the sensing voltage + Vsense level. Here, the sensing voltage + Vsense represents a voltage flowing from the source terminal of the unit cell C to the drain terminal. The sensing voltage + Vsense supplied to the read bit line RWBL is preferably controlled by the sense amplifier SA. At this time, the source line SL maintains the ground voltage GND level.

The word line WL then transitions to a positive switching voltage Vsw level. Here, the switching voltage Vsw is preferably set to a voltage level that is smaller than the high voltage level and the switching element T connected to the word line WL is turned on. The switching voltage Vsw supplied to the word line WL is preferably controlled by the word line driver.

The selected bit line BL transitions to the negative read voltage -Vread at the ground voltage GND level. The unselected bit line BL transitions to the positive pass voltage Vpass at the ground voltage GND level. Here, the pass voltage Vpass has a low voltage level such that no data is programmed in the unit cell.

That is, to determine what data is stored in the selected unit cell C, a negative read voltage -Vread is applied to the selected bit line BL, and a positive pass voltage Vpass is applied to the unselected bit line BL. Then, the unselected unit cells C are turned on. Accordingly, the data stored in the selected unit cell C can be read according to the current flowing through the read write bit line RLBL.

9A and 9B show another embodiment of a semiconductor memory device according to the present invention.

9A and 9B, the unit cell C of the present invention having the structure as shown in FIG. 2A or 2B is formed in a stack structure. An insulating layer 20 is formed between each unit cell C to insulate each unit cell C from each other. Accordingly, the semiconductor memory device of the present invention according to the exemplary embodiment of FIGS. 9A and 9B may read or write data of multi-level.

1A and 1B are cross-sectional views of unit cells of a conventional semiconductor memory device.

2A and 2B are cross-sectional views of unit cells of a semiconductor memory device according to the present invention.

3 is a cell array of a semiconductor memory device according to the present invention;

4 illustrates a polysilicon layer of a semiconductor memory device according to the present invention.

5 and 6 illustrate cell operating characteristics of a semiconductor memory device according to the present invention;

7 and 8 are timing diagrams of write and read operations of a semiconductor memory device according to the present invention;

9A and 9B illustrate another embodiment of a semiconductor memory device according to the present invention.

Claims (30)

A channel region formed on the semiconductor substrate and connected to the bit line; A drain region and a source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region and having a polarization state changed according to a voltage applied from the bit line; And A word line formed on the ferroelectric layer, And a read or write operation of data according to a voltage applied from the bit line to the channel region and a voltage applied to the word line. Claim 2 has been abandoned due to the setting registration fee. The semiconductor memory device of claim 1, further comprising an insulating layer formed between the channel region and the ferroelectric layer. Claim 3 was abandoned when the setup registration fee was paid. The semiconductor memory device of claim 1, wherein the channel region is a P-type region. Claim 4 was abandoned when the registration fee was paid. The semiconductor memory device of claim 1, wherein the drain region and the source region are N-type regions. Lead light bitlines; A unit cell in which data read or write operations are performed according to a voltage applied from a bit line to a channel region; A selection switch connected between one end of the unit cell and the read bit line and controlled by a word line; And A source line connected to the other end of the unit cell, The unit cell is A channel region formed on a semiconductor substrate and connected to the bit line; A drain region and a source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region and having a polarization state changed according to a voltage applied from the bit line; And A word line formed on the ferroelectric layer, And a read or write operation of data according to a voltage applied from the bit line to the channel region and a voltage applied to the word line. Claim 6 was abandoned when the registration fee was paid. 6. The semiconductor memory device of claim 5, further comprising a first insulating layer formed between the channel region and the ferroelectric layer. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 5, And a write driver for supplying a driving voltage to the bit line. Claim 8 was abandoned when the registration fee was paid. The semiconductor memory device as claimed in claim 5, wherein the read write bit line, the bit line, and the source line are arranged in a column direction, and the word line is arranged in a row direction. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 5, wherein the unit cell And the read write bit line, the bit line, and the source line and the word line intersect each other. Claim 10 was abandoned upon payment of a setup registration fee. The semiconductor memory device of claim 5, wherein the threshold voltage of the unit cell has a negative voltage when the voltage of the bit line is 0V. Claim 11 was abandoned upon payment of a setup registration fee. 6. The semiconductor memory device of claim 5, wherein the data has a threshold voltage lower than that of data '0' when the data is '1'. Claim 12 was abandoned upon payment of a registration fee. The semiconductor memory device of claim 5, wherein when a negative voltage is applied to the bit line, the threshold voltage of the data increases as the absolute value of the negative voltage increases. Claim 13 was abandoned upon payment of a registration fee. 6. The semiconductor memory device of claim 5, wherein the cell current of data '1' is greater than the cell current of data '0' when a negative read voltage is applied to the bit line. Claim 14 was abandoned when the registration fee was paid. The method of claim 5, wherein when data '1' is written in the unit cell And applying a positive program voltage to the word line and a negative program voltage to the bit line. Claim 15 was abandoned upon payment of a registration fee. 15. The semiconductor memory device of claim 14, wherein a ground voltage is applied to the read bit line. Claim 16 was abandoned upon payment of a setup registration fee. 15. The semiconductor memory device of claim 14, wherein the positive program voltage has a level higher than a ground voltage. Claim 17 has been abandoned due to the setting registration fee. The method of claim 5, wherein when data '0' is written in each of the unit cells And applying a negative program voltage to the word line and a positive program voltage to the bit line. Claim 18 was abandoned upon payment of a set-up fee. 18. The semiconductor memory device of claim 17, wherein a ground voltage is applied to the read bit line. Claim 19 was abandoned upon payment of a registration fee. The method of claim 5, wherein the data of the unit cell is read. And applying a negative read voltage to the bit line. Claim 20 was abandoned upon payment of a registration fee. 20. The semiconductor memory device of claim 19, wherein a positive switching voltage is supplied to the word line and a ground voltage is supplied to the source line. Claim 21 has been abandoned due to the setting registration fee. 20. The semiconductor memory device according to claim 19, wherein a positive sensing voltage is applied to the read bit line. Claim 22 is abandoned in setting registration fee. The semiconductor memory device of claim 5, further comprising a plurality of unit cells stacked on the unit cells. Claim 23 was abandoned upon payment of a set-up fee. The semiconductor memory device of claim 22, wherein the plurality of unit cells are insulated by a second insulating layer. Lead light bitlines; A select switch connected to the read bit line and controlled by a word line; A plurality of unit cells connected in series between one end of the selection switch and a source line, controlled by a word line, and configured to read or write data according to voltages applied to respective channel regions from the plurality of bit lines; And A source line connected to the other ends of the plurality of unit cells, Each of the plurality of unit cells A channel region formed on the semiconductor substrate and connected to the bit line; A drain region and a source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region and having a polarization state changed according to a voltage applied from the bit line; And And the word line formed on the ferroelectric layer. Claim 25 is abandoned in setting registration fee. The method of claim 24, A sense amplifier configured to sense and amplify cell data applied from the read bit line; And And a plurality of write drivers configured to supply driving voltages to the plurality of bit lines. Claim 26 is abandoned in setting registration fee. 25. The method of claim 24, wherein when data '1' is written in a selected unit cell of the plurality of unit cells And applying a positive program voltage to the word line and a negative program voltage to the selected bit line. Claim 27 was abandoned upon payment of a registration fee. 25. The method of claim 24, wherein when data '0' is written in a selected unit cell of the plurality of unit cells And applying a negative program voltage to the word line and a positive program voltage to the selected bit line. Claim 28 has been abandoned due to the set registration fee. 25. The method of claim 24, wherein the data of the plurality of unit cells is read. And applying a negative read voltage to a selected bit line among the plurality of bit lines, and applying a positive pass voltage to an unselected bit line. Claim 29 has been abandoned due to the setting registration fee. 29. The semiconductor memory device of claim 28, wherein a positive switching voltage is applied to the word line and a ground voltage is supplied to the source line. Claim 30 has been abandoned due to the set registration fee. 29. The semiconductor memory device of claim 28, wherein a positive sensing voltage is applied to the read bit line.

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