KR20060117793A - Non-volatile ferroelectric memory device - Google Patents

Abstract

A nonvolatile ferroelectric memory device is provided to enhance the reliability in a low voltage operation of a nano-scale ferroelectric cell and to improve a read operation rate. An insulating layer(11) is formed on a bottom word line(10). A floating channel layer(15) is formed on the insulating layer. The floating channel layer is composed of an N type channel region(12) and P type source/drain regions(13,14) on both sides of the channel region. A ferroelectric film(16) is formed on the channel region of the floating channel layer. A word line(17) is formed on the ferroelectric film. Data read/write operations are controlled by introducing different channel resistances to the channel region according to a polarization state of the ferroelectric film.

Description

Non-volatile ferroelectric memory device

1 is a cross-sectional view of a cell of a nonvolatile ferroelectric memory device according to the prior art.

2A and 2B are cell cross-sectional views of a nonvolatile ferroelectric memory device in accordance with the present invention.

3A and 3B are diagrams for explaining low data write / read operations of a nonvolatile ferroelectric memory device according to the present invention;

4A and 4B are diagrams for explaining a high data write / read operation of a nonvolatile ferroelectric memory device according to the present invention;

5A and 5B illustrate a row data retention operation of a nonvolatile ferroelectric memory device according to the present invention.

6 is a layout cross-sectional view of a nonvolatile ferroelectric memory device according to the present invention;

7A and 7B are cross-sectional views of a nonvolatile ferroelectric memory device in accordance with the present invention.

8 is a cross-sectional view of a nonvolatile ferroelectric memory device according to the present invention having a multilayer structure.

9 is another embodiment of a nonvolatile ferroelectric memory device in accordance with the present invention.

10A and 10B are cross-sectional views of a nonvolatile ferroelectric memory device according to the embodiment of FIG. 9.

11 is a cross-sectional view of a nonvolatile ferroelectric memory device having a multilayer structure according to the embodiment of FIG. 9.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory device, which controls read / write operations of a nonvolatile memory cell by using a characteristic in which channel resistance of the memory cell is changed according to the polarization state of the ferroelectric in a nanoscale memory device. Technology.

In general, the nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device due to its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a memory device having a structure almost similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FeRAM has been disclosed in Korean Patent Application No. 2001-57275 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FeRAM and its operation will be omitted.

The unit cell of the conventional nonvolatile ferroelectric memory device includes one switching element connecting a sub bit line and a nonvolatile ferroelectric capacitor by switching according to a state of a word line, and one connected between one end of the switching element and a plate line. Of nonvolatile ferroelectric capacitors.

Here, the switching element of the conventional nonvolatile ferroelectric memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

1 is a cross-sectional view of a cell of a nonvolatile ferroelectric memory device according to the prior art.

In a conventional 1-T (FET) field effect transistor (FET) type cell, an N-type drain region 2 and an N-type source region 3 are formed on a P-type region substrate 1. A ferroelectric layer 4 is formed on the channel region, and a word line 5 is formed on the ferroelectric layer 4.

A conventional nonvolatile ferroelectric memory device having such a configuration reads / writes data using a characteristic in which the channel resistance of the memory cell varies depending on the polarization state of the ferroelectric layer 4. That is, when the polarity of the ferroelectric layer 4 induces a positive charge in the channel, the memory cell is turned off due to a high resistance state. In contrast, when the polarity of the ferroelectric layer 4 induces a negative charge to the channel, the memory cell is turned into a low resistance state.

However, in such a conventional nonvolatile ferroelectric memory device, when the cell size becomes small, the data retention characteristic is deteriorated, which makes normal cell operation difficult. In other words, when a cell read operation, voltage is applied to an adjacent cell, and data is destroyed, thereby causing interface noise between cells. In addition, since a write voltage is applied to an unselected cell during the write operation of the cell, data of the unselected cells is destroyed, thereby making it difficult to perform a random access operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and forms a floating channel layer consisting of a P-type drain region, an N-type channel region, and a P-type source region between a word line and a bottom word line to read / write a memory cell. The purpose is to improve the reliability of the cell by controlling the write operation and to reduce the overall size of the cell.

A nonvolatile ferroelectric memory device of the present invention for achieving the above object, the insulating layer formed on the upper word line; A floating channel layer formed on the insulating layer to maintain a floating state, and a floating channel layer having a P-type drain region and a P-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And a word line formed on an upper portion of the ferroelectric layer, wherein data is read / controlled by inducing different channel resistances in the channel region according to the polarity of the ferroelectric layer.

In addition, the present invention includes a plurality of bottom word lines; A plurality of insulating layers formed on top of the plurality of bottom word lines, respectively; A floating channel layer including a plurality of N-type channel regions disposed on the plurality of insulating layers, and a plurality of P-type drain and source regions alternately connected in series with the plurality of N-type channel regions; A plurality of ferroelectric layers respectively formed on the plurality of N-type channel regions of the floating channel layer; And a unit cell array having a plurality of word lines respectively formed on the plurality of ferroelectric layers, wherein the unit cell array induces different channel resistances in the plurality of N-type channel regions according to the polarity of the plurality of ferroelectric layers. And read / write control of a plurality of data.

In addition, the present invention is a single word line; A plurality of insulating layers formed on top of the bottom word line; A floating channel layer including a plurality of N-type channel regions disposed on the plurality of insulating layers, and a plurality of P-type drain and source regions alternately connected in series with the plurality of N-type channel regions; A plurality of ferroelectric layers respectively formed on the plurality of N-type channel regions of the floating channel layer; And a unit cell array having a plurality of word lines respectively formed on the plurality of ferroelectric layers, wherein the unit cell array induces different channel resistances in the plurality of N-type channel regions according to the polarity of the plurality of ferroelectric layers. And read / write control of a plurality of data.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A and 2B are cross-sectional views of unit cells of a nonvolatile ferroelectric memory device according to the present invention.

2A is a cross-sectional view of a unit cell viewed in a direction parallel to a word line.

First, the bottom word line 10 formed in the lowermost layer and the word line 17 formed in the uppermost layer are arranged in parallel. Here, the bottom word line 10 and the word line 17 are selectively driven by the same row address decoder (not shown). In addition, an insulating layer 11 is formed on the bottom word line 10, and a floating channel layer 15 formed of an N-type channel region 12 is formed on the insulating layer 11. Is formed.

In addition, a ferroelectric layer 16 is formed on the floating channel layer 15, and a word line 17 is formed on the ferroelectric layer 16.

2B is a cross-sectional view of the unit cell viewed in a direction perpendicular to the word line.

First, the insulating layer 11 is formed on the bottom word line 10. In addition, a floating channel layer 15 is formed on the insulating layer 11. Here, the drain region 13 and the source region 14 of the floating channel layer 15 are made of P type, and the channel region 12 is made of N type to be in a floating state.

In addition, as the semiconductor of the floating channel layer 15, a material such as carbon nanotube, silicon, or Ge (germanium) may be used. In addition, a ferroelectric layer 16 is formed on the N-type channel region 12 of the floating channel layer 15, and a word line 17 is formed on the ferroelectric layer 16.

The present invention having such a configuration reads and writes data using the characteristic that the channel resistance of the floating channel layer 15 varies depending on the polarization state of the ferroelectric layer 16. That is, when the polarity of the ferroelectric layer 16 induces negative charge to the channel region 12, the memory cell is in a high resistance state and the channel is turned off. In contrast, when the polarity of the ferroelectric layer 16 induces a positive charge in the channel region 12, the memory cell is in a low resistance state and the channel is turned on.

3A and 3B illustrate a low data write / read operation of a nonvolatile ferroelectric memory device according to the present invention.

First, referring to FIG. 3A, in the write operation mode of data "0", a negative voltage <-V> is applied to the bottom word line 10 and a positive voltage <+ V> is applied to the word line 17. do. At this time, the drain region 13 and the source region 14 are in a ground voltage <GND> state.

In this case, a voltage is applied between the ferroelectric layer 16 and the N-type channel region 12 of the floating channel layer 15 by the voltage distribution of the capacitor between the ferroelectric layer 16 and the insulating layer 11.

Accordingly, negative charge is induced in the channel region 12 depending on the polarity of the ferroelectric layer 16, resulting in a high resistance state of the memory cell. At this time, the negative charge is induced in the channel region 12, and the drain region 13 and the source region 14 are in a ground state, so the channel region 12 remains in an off state. Accordingly, data "0" can be written to all cells in the memory in the write operation mode.

3B, the positive voltage <+ V> is applied to the bottom word line 10 and the ground voltage <GND> is applied to the word line 17 in the read operation mode of the data “0”. Here, the negative charge is induced in the channel region 12, and the drain region 13 and the source region 14 are in a ground state, so the channel region 12 remains in an off state.

Accordingly, data "0" stored in the memory cell can be read in the read operation mode. At this time, even if a slight voltage difference is applied to the drain region 13 and the source region 14, a small current flows because the channel region 12 is turned off.

4A and 4B are diagrams for describing a high data write / read operation of a nonvolatile ferroelectric memory device according to the present invention.

First, referring to FIG. 4A, a negative voltage <-V> is applied to the bottom word line 10 and the word line 17 in the write operation mode of the data "1". At this time, the drain region 13 and the source region 14 are in a ground voltage <GND> state.

In this case, positive charge is induced in the channel region 12, and the drain region 13 and the source region 14 are in a ground state, and thus the channel region 12 remains in a turned on state. As a result, the channel region 12 is turned on so that the ground voltage flows.

A high voltage is formed between the ground voltage formed in the channel region 12 and the negative voltage <-V> applied from the word line 17. Accordingly, positive charge is induced in the channel region 12 depending on the polarity of the ferroelectric layer 16, resulting in a low resistance state of the memory cell. Accordingly, data "1" can be written to the memory cell in the write operation mode.

On the other hand, in FIG. 4B, the positive voltage <+ V> is applied to the bottom word line 10 and the ground voltage <GND> is applied to the word line 17 in the read operation mode of the data “1”. At this time, even if a slight voltage difference is applied between the drain region 13 and the source region 14, a large current flows because the channel region 12 is turned on. Accordingly, data "1" stored in the memory cell can be read in the read operation mode.

In particular, a memory cell of a nanoscale level ferroelectric structure has a problem in that data cannot be maintained because its characteristics deteriorate even when a low voltage stress is applied. However, in the present invention, since the word line 17 is controlled to the ground in the read operation mode, the voltage stress is not applied to the ferroelectric layer 16, so that the data retention characteristic of the cell can be improved and the low voltage operation can be performed.

5A and 5B illustrate a row data retention operation of a nonvolatile ferroelectric memory device according to the present invention.

First, referring to FIG. 5A, when data "0" is stored and stored therein, a negative voltage <-V> is applied to the bottom word line 10 and the word line 17. At this time, when a negative voltage <-V> is applied to the drain region 13 and the source region 14, the channel region 12 is turned off.

In this case, a voltage difference does not occur between the negative voltage of the channel region 12 in the floating state and the negative voltage <-V> of the word line 17. As a result, the polarity change of the ferroelectric layer 16 does not occur and the previous polarity state can be maintained to preserve the data " 0 ".

6 is a layout cross-sectional view of a nonvolatile ferroelectric memory device according to the present invention.

In the present invention, the word line WL and the bottom word line BWL are arranged in parallel in the same direction and provided in plural in the column direction. A plurality of bit lines BL are provided in a direction perpendicular to the word line WL. In addition, a plurality of unit cells C are positioned in an area where a plurality of word lines WL, a plurality of bottom word lines BWL, and a plurality of bit lines BL intersect.

7A and 7B are cross-sectional views of a cell array of a nonvolatile ferroelectric memory device according to the present invention.

FIG. 7A illustrates a cell array cross-sectional structure in the direction (A) parallel to the word line WL in the layout cross-sectional view of FIG. 6.

In the cell array of the present invention, a plurality of insulating layers 11 are formed on the bottom word line 10, and a plurality of N-type channel regions 12 are formed on the plurality of insulating layers 11. The plurality of ferroelectric layers 16 are formed on the plurality of channel regions 12, and the word lines 17 are formed on the plurality of ferroelectric layers 16 in parallel with the bottom word lines 10. Thus, a plurality of cells are connected between one word line WL_1 and one bottom word line BWL_1.

In addition, FIG. 7B illustrates a cell array cross-sectional structure in a direction (B) perpendicular to the word line WL in the layout cross-sectional view of FIG. 6.

In the cell array of the present invention, an insulating layer 11 is formed on each of the bottom word lines BWL_1, BWL_2, and BWL_3. In addition, the floating channel layer 15 having the P-type drain region 13, the N-type channel region 12, and the P-type source region 14 connected in series is formed on the insulating layer 11.

Here, the P-type drain region 13 may be used as a source region in an adjacent cell, and the P-type source region 14 may be used as a drain region in an adjacent cell. That is, the P-type region is commonly used as a drain region and a source region in adjacent cells.

In addition, a ferroelectric layer 16 is formed on each channel region 12 of the floating channel layer 15, and word lines WL_1, WL_2, and WL_3 are formed on the ferroelectric layer 16.

8 is a cross-sectional view of a nonvolatile ferroelectric memory device having a multilayer structure according to the present invention.

In the present invention having the multilayer structure shown in FIG. 8, the unit cell array of the present invention having the configuration as shown in FIG. 7B is stacked in a multilayer structure. Each unit cell array is separated from each other through the insulating layer 18.

9 is another embodiment of a nonvolatile ferroelectric memory device according to the present invention.

In the present invention, the bottom word line 10 is commonly used in a predetermined cell array. The plurality of word lines WL are provided in the column direction, and the plurality of bit lines BL are provided in the row direction. In addition, a plurality of unit cells C are positioned in an area where a plurality of word lines WL and a plurality of bit lines BL intersect.

10A and 10B are cross-sectional views of a cell array of a nonvolatile ferroelectric memory device according to the embodiment of FIG. 9.

FIG. 10A illustrates a cell array cross-sectional structure in the direction (C) parallel to the word line WL in the layout cross-sectional view of FIG. 9.

In the cell array of the present invention, a plurality of insulating layers 11 are formed on the bottom word line 10, and a plurality of N-type channel regions 12 are formed on the plurality of insulating layers 11. The plurality of ferroelectric layers 16 are formed on the plurality of channel regions 12, and the word lines 17 are formed on the plurality of ferroelectric layers 16 in parallel with the bottom word lines 10. Therefore, a plurality of cells are connected between one word line WL_1 and one bottom word line BWL_1.

10B illustrates a cell array cross-sectional structure in the direction (D) perpendicular to the word line WL in the layout cross-sectional view of FIG. 9.

In the cell array of the present invention, the insulating layer 11 is formed on the bottom word lines BWL_1, BWL_2, and BWL_3 commonly connected. In addition, the floating channel layer 15 having the P-type drain region 13, the N-type channel region 12, and the P-type source region 14 connected in series is formed on the insulating layer 11. In addition, a ferroelectric layer 16 is formed on each channel region 12 of the floating channel layer 15, and word lines WL_1, WL_2, and WL_3 are formed on the ferroelectric layer 16.

11 is a cross-sectional view of a nonvolatile ferroelectric memory device having a multilayer structure according to the present invention.

In the present invention having the multilayer structure shown in FIG. 11, the unit cell array of the present invention having the configuration as shown in FIG. 10B is stacked in a multilayer structure. Each unit cell array is separated from each other through the insulating layer 18.

In the present invention, the floating channel layer 15 is composed of the P-type drain region 13, the N-type channel region 12 and the P-type source region 14 in the embodiment, but the present invention is not limited thereto. The floating channel layer 15 may be formed of an N-type drain region, an N-type channel region, and an N-type source region.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.

As described above, the present invention does not destroy the data of the cell during the read operation using the Non Destructive Read Out (NDRO) method. Accordingly, the present invention can improve the reliability of the cell during the low voltage operation of the nano-scale ferroelectric cell and improve the read operation speed. In addition, by stacking a plurality of ferroelectric unit cell array to improve the integrated capacity of the cell provides an effect that can reduce the overall size of the cell.

Claims (21)

An insulation layer formed on the bottom word line; A floating channel layer formed on the insulating layer and having an N-type channel region maintaining a floating state, and a P-type drain region and a P-type source region connected to both sides of the channel region; A ferroelectric layer formed on the channel region of the floating channel layer; And A word line formed on the ferroelectric layer, And a read / write control of data by inducing different channel resistances in the channel region according to the polarity of the ferroelectric layer. The nonvolatile ferroelectric memory device of claim 1, wherein the floating channel layer is formed of at least one of carbon nanotubes, silicon, and germanium. The nonvolatile ferroelectric memory device of claim 1, wherein the floating channel layer is turned off when the polarity of the ferroelectric layer induces a negative charge in the channel region, resulting in a high resistance state. 4. The nonvolatile ferroelectric memory device of claim 3, wherein the floating channel layer is turned on when the polarity of the ferroelectric layer induces positive charge in the channel region, resulting in a low resistance state. 2. The negative terminal of claim 1, wherein a negative voltage is applied to the bottom word line, a positive voltage is applied to the word line, and a ground voltage is applied to the drain region and the source region. A nonvolatile ferroelectric memory device, wherein charge is induced to write low data. 6. The nonvolatile ferroelectric of claim 5, wherein when a negative voltage is applied to the drain region and the source region while a negative voltage is applied to the bottom word line and the word line, the nonvolatile ferroelectric is maintained. Memory device. 2. The nonvolatile ferroelectric memory of claim 1, wherein a low voltage is applied to the bottom word line and a ground voltage is applied to the word line to read low data while the channel of the floating channel layer is turned off. Device. The method of claim 1, wherein a positive charge is induced in the channel region while a negative voltage is applied to the bottom word line and the word line, and a ground voltage is applied to the drain region and the source region. Non-volatile ferroelectric memory device characterized in that the writing. The nonvolatile ferroelectric memory of claim 1, wherein a high voltage is read while a positive voltage is applied to the bottom word line and a ground voltage is applied to the word line to turn on the high data while the channel of the floating channel layer is turned on. Device. A plurality of bottom word lines; A plurality of insulating layers formed on the plurality of bottom word lines, respectively; A floating channel layer including a plurality of N-type channel regions disposed on the plurality of insulating layers, and a plurality of P-type drain and source regions alternately connected in series with the plurality of N-type channel regions; A plurality of ferroelectric layers respectively formed on the plurality of N-type channel regions of the floating channel layer; And A unit cell array having a plurality of word lines formed on the plurality of ferroelectric layers, respectively; And the unit cell array is configured to read / write a plurality of data by inducing different channel resistances to the plurality of N-type channel regions according to polarity of the plurality of ferroelectric layers. The nonvolatile ferroelectric memory device of claim 10, wherein the unit cell arrays are stacked in a plurality of layers to form a multi-layer structure, and the unit cell arrays are separated from each other by an insulating layer. The nonvolatile ferroelectric memory device of claim 10, wherein the floating channel layer is formed of at least one of carbon nanotubes, silicon, and germanium. The nonvolatile ferroelectric memory of claim 10, wherein the floating channel layer is turned off when the polarity of the plurality of ferroelectric layers induces negative charge in the plurality of N-type channel regions, resulting in a high resistance state. Device. 12. The nonvolatile ferroelectric memory of claim 10, wherein the floating channel layer is turned into a low resistance state when the polarities of the plurality of ferroelectric layers induce positive charge in the plurality of N-type channel regions. Device. The N-type channel of claim 10, wherein a negative voltage is applied to the plurality of bottom word lines and the plurality of word lines, and ground voltages are applied to the plurality of P-type drain and source regions. A nonvolatile ferroelectric memory device, characterized in that a positive charge is induced in a region to write high data. 12. The method of claim 10, wherein a high voltage is applied to the plurality of bottom word lines and a ground voltage is applied to the plurality of word lines to read high data while the channel of the floating channel layer is turned on. Nonvolatile ferroelectric memory device. The method of claim 10, wherein a negative voltage is applied to the plurality of bottom word lines, a positive voltage is applied to the plurality of word lines, and ground voltages are applied to the plurality of P-type drain and source regions. A nonvolatile ferroelectric memory device, characterized in that a negative charge is induced in the plurality of N-type channel regions to write low data. 18. The method of claim 17, wherein when a negative voltage is applied to the plurality of P-type drain and source regions while a negative voltage is applied to the plurality of bottom word lines and the plurality of word lines, the previous data is maintained. A nonvolatile ferroelectric memory device. 12. The method of claim 10, wherein a low voltage is applied to the plurality of bottom word lines and a ground voltage is applied to the plurality of word lines to read low data while the channel of the floating channel layer is turned off. Nonvolatile ferroelectric memory device. One bottom word line; A plurality of insulating layers formed on the bottom word lines, respectively; A floating channel layer including a plurality of N-type channel regions disposed on the plurality of insulating layers, and a plurality of P-type drain and source regions alternately connected in series with the plurality of N-type channel regions; A plurality of ferroelectric layers respectively formed on the plurality of N-type channel regions of the floating channel layer; And A unit cell array having a plurality of word lines formed on the plurality of ferroelectric layers, respectively; And the unit cell array is configured to read / write a plurality of data by inducing different channel resistances to the plurality of N-type channel regions according to polarity of the plurality of ferroelectric layers. 21. The nonvolatile ferroelectric memory device of claim 20, wherein the unit cell arrays are stacked in a plurality of layers to form a multi-layer structure, and the unit cell arrays are separated from each other by an insulating layer.

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