KR20080061234A - Semiconductor memory device using ferroelectric device and method for refresh thereof - Google Patents

Abstract

A semiconductor memory device using a ferroelectric device and a refresh method thereof are provided to reduce cell area by storing dual-bit in one unit cell through applying a 1T-FET type(1 Transistor-Field Effect Transistor Type) ferroelectric memory cell to a DRAM. A semiconductor memory device includes a channel region formed on a substrate(1), a drain region and a source region formed on both ends of the channel region, a ferroelectric layer(4) formed on the channel region and a word line formed on the ferroelectric layer. The semiconductor memory device includes a 1-T(One-Transistor) FET(Field Effect Transistor) type memory cell inducing different channel resistance in the channel region according to polarity state of the ferroelectric layer. A left-bit storing part(10) stores left-bit data applied through a first drain/source region. A right-bit storing part(20) stores right-bit data applied through a second drain/source region. Read operation of dual-bit data is performed by sensing a cell sensing current value varying according to polarity state of the ferroelectric layer when a read voltage is applied to the word line and a sensing bias voltage is applied to one of the first and the second drain/source region. Write operation of dual-bit data is performed by changing polarity of the ferroelectric layer according to the voltage applied to the word line and the first and the second drain/source region.

Description

Semiconductor memory device using ferroelectric device and refreshing method {Semiconductor memory device using ferroelectric device and method for refresh}

1 is a cross-sectional view of a cell of a semiconductor memory device according to the present invention.

2 is a view for explaining a data storage location of a semiconductor memory device according to the present invention;

3 is a view for explaining a data write operation of a semiconductor memory device according to the present invention;

4 is a view for explaining a data '01' write operation of a semiconductor memory device according to the present invention;

5 is a view for explaining a data '10' write operation of a semiconductor memory device according to the present invention;

6 is a view for explaining a data '11' write operation of a semiconductor memory device according to the present invention;

7 is a view for explaining a read operation of left-bit data of a semiconductor memory device according to the present invention;

8 is a view for explaining a read operation of right-bit data of the semiconductor memory device according to the present invention;

9A and 9B are graphs showing bit line currents in a read mode of a semiconductor memory device according to the present invention;

10 is a timing diagram of a write cycle operation of the semiconductor memory device according to the present invention.

11 is a refresh cycle operation timing diagram of a semiconductor memory device according to the present invention;

12 is an overall configuration diagram of a semiconductor memory device according to the present invention.

13 is a graph for explaining data retention characteristics of a semiconductor memory device according to the present invention;

14 is a plan view of a cell array of a semiconductor memory device according to the present invention;

15 illustrates a cell array structure and a write-bit data read operation of the semiconductor memory device according to the present invention;

16 is a view for explaining a cell array structure and left-bit data read operation of a semiconductor memory device according to the present invention;

17 is a view for explaining a '0000 ...' write operation of a semiconductor memory device according to the present invention;

18 is a view for explaining a '0101 ...' write operation of a semiconductor memory device according to the present invention;

19 is a view for explaining a '1010 ...' write operation of a semiconductor memory device according to the present invention.

20 is a view for explaining a '1111 ...' write operation of the semiconductor memory device according to the present invention.

21 is a timing diagram related to a read operation of the semiconductor memory device according to the present invention.

Fig. 22 is a timing diagram relating to the write operation of the semiconductor memory device according to the present invention.

23 is another embodiment of a cell array of a semiconductor memory device according to the present invention;

24 is a block diagram illustrating a cell array structure, a write driver, and a sense amplifier of a semiconductor memory device according to the present invention.

25 is a circuit diagram of a row decoder of a semiconductor memory device according to the present invention.

FIG. 26 is an operational waveform diagram relating to the row decoder of FIG. 25;

FIG. 27 is a detailed circuit diagram of the write driver and the sense amplifier of FIG. 24; FIG.

28 is an operational waveform diagram of the write driver and the sense amplifier of FIG. 27;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device employing a ferroelectric element and a refresh method thereof, and discloses a technique of applying a 1T-FET ferroelectric memory cell having a nonvolatile characteristic to a DRAM.

In general, DRAM is a volatile memory, and power supply is required to store data. If power is lost momentarily, data held in RAM can be lost. This is because DRAM memory cells are designed around small chargers that hold the charged power. These chargers are like very small rechargeable batteries that don't continue to be recharged and lose precharged power.

A refresh operation refers to a process of recharging a memory cell in such a memory chip, and a row of memory cells may be charged in each refresh cycle. This refresh operation is performed by the memory control of the system, but some chips are designed to perform a self refresh operation.

For example, a DRAM chip has a self-refreshing circuit, and thus a technology for autonomous refreshing without intervention of a central processing unit (CPU) or an external refresh circuit has been disclosed. This self-refreshing method significantly reduces power consumption and is often used in portable computers.

Since the conventional DRAM is volatile and has a short refresh period, the refresh operation is frequently performed. Accordingly, power consumption due to the refresh operation is large and operation performance is lowered.

On the other hand, nonvolatile ferroelectric memory, that is, FeRAM (Ferroelectric Random Access Memory) has a data processing speed as much as DRAM (DRAM) and is a next-generation memory device because of the characteristic that data is preserved even when the power is turned off. It is attracting attention.

The FeRAM is a memory device having a structure similar to that of a DRAM, and uses a ferroelectric material as a capacitor material, and uses a high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

The 1T1C (1-Transistor 1-Capacitor) unit cell of the conventional nonvolatile ferroelectric memory device includes a switching element for switching a bit line and a nonvolatile ferroelectric capacitor by switching according to a state of a word line, and a switching element. And a nonvolatile ferroelectric capacitor connected between one end of the plate line and the plate line. Here, the switching element of the conventional nonvolatile ferroelectric memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

According to the present invention, a 1T-FET ferroelectric memory cell having a nonvolatile characteristic is applied to a DRAM, thereby saving a cell area by storing a dual-bit in one unit cell. The purpose is to reduce it.

In addition, the present invention can improve data retention characteristics without losing refresh information even when the power supply is turned off in a DRAM to which a 1T-FET ferroelectric memory cell having a nonvolatile characteristic is applied. The purpose is to make it.

In addition, an object of the present invention is to maintain the refresh information even when the power supply is off by performing the refresh operation according to the parameter information stored in the nonvolatile register when the power supply is off.

In addition, since the present invention has a nonvolatile characteristic, the on / off time of the power supply is set as the total data retention time, so that the refresh operation is not frequently performed, thereby reducing power consumption and improving operation performance. There is this.

A semiconductor memory device employing the ferroelectric element of the present invention for achieving the above object comprises a channel region formed on a substrate; A drain region and a source region formed at both ends of the channel region; A ferroelectric layer formed on the channel region; And a 1-T (One-Transistor) field effect transistor (FET) type memory cell including a word line formed on the ferroelectric layer, wherein different channel resistances are induced in the channel region according to the polarity of the ferroelectric layer. A semiconductor memory device, comprising: a left-bit storage unit for storing left-bit data applied through a first drain / source region; And a write-bit storage unit for storing write-bit data applied through the second drain / source region, wherein a read voltage is applied to the word line and one of the first drain / source region and the second drain / source region In the state where the sensing bias voltage is applied to the region of the cell, a read operation of the double-bit data is performed by sensing a cell sensing current value that varies according to the polarity state of the ferroelectric layer. The polarity of the ferroelectric layer is changed according to the voltage applied to the drain / source region, and the write operation of the double-bit data is performed.

In addition, the present invention includes a channel region, a drain region and a source region formed on the substrate; A ferroelectric layer formed on the channel region; A semiconductor comprising a word line formed on top of a ferroelectric layer and including a 1-T (One-Transistor) field effect transistor (FET) type memory cell in which different channel resistances are induced in a channel region according to the polarity of the ferroelectric layer. A memory device, comprising: a plurality of word lines arranged in a row direction; A plurality of even bit lines arranged in a direction perpendicular to the plurality of word lines; And a plurality of odd bit lines arranged in a direction perpendicular to the plurality of word lines and alternately arranged with the plurality of even bit lines, wherein the memory cells are adjacent to each other among the plurality of even bit lines and the plurality of odd bit lines. The polarity of the ferroelectric layer is changed according to respective voltages applied to the word line and the even / odd bit line pairs to read / write dual-bit data.

In addition, the present invention includes a channel region, a drain region and a source region formed on the substrate; A ferroelectric layer formed on the channel region; A 1-T (One-Transistor) field effect transistor (FET) type memory cell including a word line formed on the ferroelectric layer, and having different channel resistances induced in the channel region according to the polarity of the ferroelectric layer; A plurality of word lines arranged in a row direction; A plurality of even bit lines arranged in a direction perpendicular to the plurality of word lines; A plurality of odd bit lines arranged in a direction perpendicular to the plurality of word lines and alternately arranged with the plurality of even bit lines; And refresh control means for performing a refresh operation at a specific refresh cycle to improve a retention characteristic of data stored in the memory cell, wherein the memory cell is an even / odd bit line adjacent to each other among a plurality of even bit lines and a plurality of odd bit lines. Coupled between the pairs, the polarity of the ferroelectric layer is changed according to respective voltages applied to the word line and the even / odd bit line pairs, thereby performing read / write of the double-bit data.

The refresh method of the semiconductor memory device to which the ferroelectric element of the present invention is applied includes: a plurality of word lines arranged in a row direction; A plurality of even bit lines arranged in a direction perpendicular to the plurality of word lines; A plurality of odd bit lines arranged in a direction perpendicular to the plurality of word lines and alternately arranged with the plurality of even bit lines; A channel region, a drain region, and a source region formed on the substrate; A ferroelectric layer formed on the channel region; 1-T including a word line formed on an upper portion of the ferroelectric layer and connected between adjacent bit line pairs among the plurality of bit lines to change the polarity of the ferroelectric layer according to a voltage applied to the word line and the bit line pair. A transistor includes a field effect transistor (FET) type memory cell, and the memory cell is connected between an even / odd bit line pair adjacent to each other among a plurality of even bit lines and a plurality of odd bit lines. In a semiconductor memory device in which the polarity of the ferroelectric layer is changed according to each voltage applied to a pair of bit lines to read / write double-bit data, different channel resistances are induced in the channel region of a 1T-FET type memory cell. Reading / writing data; And refreshing the data of the memory cells at specific refresh cycles to improve the retention characteristics of the data stored in the memory cells.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a cross-sectional view of a cell of a semiconductor memory device according to the present invention.

The 1-T (FET) field effect transistor (FET) type ferroelectric memory cell of the present invention has a P-type channel region, an N-type drain region 2 and an N-type of a memory cell on a P-type region substrate 1. The source region 3 is formed. A ferroelectric layer 4 is formed on the channel region, and a word line 5 is formed on the ferroelectric layer 4.

Here, the buffer insulating layer 6 may be formed between the channel region and the ferroelectric layer 4 to stabilize the process. In other words, the buffer insulating layer 6 is formed to overcome the process and material differences between the channel region and the ferroelectric layer 4.

A semiconductor memory device having such a configuration reads / writes data using a characteristic in which the channel resistance of the memory cell varies depending on the polarization polarity of the ferroelectric layer 4.

That is, when the polarity of the ferroelectric layer 4 induces positive charge to the channel, the memory cell is turned off because of the high resistance channel state. In contrast, when the polarity of the ferroelectric layer 4 induces a negative charge to the channel, the memory cell is turned into a low resistance channel state. As described above, the ferroelectric memory cell becomes a nonvolatile memory cell by selecting the polarization polarity type of the ferroelectric layer 4 and writing data to the cell.

2 is a view for explaining a data storage location of a semiconductor memory device according to the present invention.

The 1-T (FET) field effect transistor (FET) type ferroelectric memory cell of the present invention includes a left-bit (Bit) storage unit 10 for storing 1 bit, and a write (1) for storing 1 bit. The dual-bit storage unit 20 may store a dual-bit in one unit cell. In the following description, the left-bit is referred to as an 'L-bit' and the write-bit is referred to as an 'R-bit' for convenience of description.

The ferroelectric layer 4 and the channel region disposed on the left side of the unit cell based on the channel region are referred to as the L-bit storage unit 10 to store data '1' or data '0'. The ferroelectric layer 4 and the channel region disposed on the right side with respect to the channel region of the unit cell are referred to as an R-bit storage unit 20 to store data '1' or data '0'.

In this case, when reading data stored in the L-bit storage unit 10, the N-type region 2 serves as a source region, and the N-type region 3 serves as a drain region. When the data stored in the R-bit storage unit 20 is read, the N-type region 3 serves as a source region, and the N-type region 2 serves as a drain region. Accordingly, one N-type region 2, 3 may be a drain region or a source region. Therefore, the data can be written to the L-bit storage unit 10 and the R-bit storage unit 20 simultaneously during the write operation of the memory cell, but the L-bit storage unit 10 and Data stored in the R-bit storage unit 20 cannot be read simultaneously.

The L-bit storage unit 10 stores data in which the polarity of the ferroelectric layer 4 is changed by the voltage applied between the N-type region 2 serving as the source region and the gate region (channel region). Set to area. In addition, the R-bit storage unit 20 stores data in which the polarity of the ferroelectric layer 4 is changed by the voltage applied between the N-type region 3 serving as the source region and the gate region (channel region). Set to area.

That is, because the channel bias voltage is weakly applied to the region between the L-bit storage unit 10 and the R-bit storage unit 20, the intended data is not read or written, and the read / write operation of the data is affected. Invalid data that does not extend is stored. The widths of the storage regions corresponding to the L-bit storage unit 10 and the R-bit storage unit 20 may be sufficiently changed according to the magnitude of the bias voltage applied to the drain / source region.

3 is a view for explaining a data write operation of a semiconductor memory device according to the present invention.

In order to store data '0' in the L-bit storage unit 10 and data '0' in the R-bit storage unit 20, a power supply voltage VDD is applied to the word line 5. The ground voltage GND is applied to both the N-type drain / source regions 2 and 3. In this case, a negative charge is induced in the channel region according to the polarity of the ferroelectric 4 so that the data '00' can be written.

4 is a diagram for describing a data '01' write operation of a semiconductor memory device according to the present invention.

In order to store data '0' in the L-bit storage unit 10 and data '1' in the R-bit storage unit 20, a negative read voltage -Vrd is applied to the word line 5. Then, the ground voltage GND is applied to the N-type drain / source region 2, and a positive read voltage Vrd is applied to the N-type drain / source region 3.

In this case, a negative charge is induced in the channel region of the L-bit storage unit 10 according to the polarity of the ferroelectric 4 so that the data '0' can be written. In addition, a positive charge is induced in the channel region of the R-bit storage unit 20 according to the polarity of the ferroelectric 4 so that the data '1' can be written.

5 is a view for explaining a data '10' write operation of a semiconductor memory device according to the present invention.

In order to store data '1' in the L-bit storage unit 10 and data '0' in the R-bit storage unit 20, a negative read voltage -Vrd is applied to the word line 5. Then, a positive read voltage Vrd is applied to the N-type drain / source region 2 and a ground voltage GND is applied to the N-type drain / source region 3.

In this case, positive charges are induced in the channel region of the L-bit storage unit 10 according to the polarity of the ferroelectric 4 so that the data '1' can be written. Then, a negative charge is induced in the channel region of the R-bit storage unit 20 according to the polarity of the ferroelectric 4 so that the data '0' can be written.

6 is a view for explaining a data '11' write operation of a semiconductor memory device according to the present invention.

In order to store data '1' in the L-bit storage unit 10 and data '1' in the R-bit storage unit 20, a negative read voltage -Vrd is applied to the word line 5. The positive read voltage Vrd is applied to both the N-type drain / source regions 2 and 3. In this case, positive charges are induced in the channel region according to the polarity of the ferroelectric 4 so that data '11' can be written.

7 is a view for explaining a read operation of the L-bit data of the semiconductor memory device according to the present invention.

In order to read the data stored in the L-bit storage unit 10, the read voltage Vrd is applied to the word line 5. The ground voltage GND is applied to the N-type drain / source region 2, and the sensing bias voltage Vsen is applied to the N-type drain / source region 3. In this case, the cell sensing current flowing in the channel region is sensed to read the data stored in the L-bit storage unit 10.

8 is a view for explaining a read operation of R-bit data of the semiconductor memory device according to the present invention.

In order to read the data stored in the R-bit storage unit 20, the read voltage Vrd is applied to the word line 5. The sensing bias voltage Vsen is applied to the N-type drain / source region 2 and the ground voltage GND is applied to the N-type drain / source region 3. In this case, the cell sensing current flowing in the channel region is sensed to read the data stored in the R-bit storage unit 20.

9A and 9B are graphs illustrating a bit line BL current in a read mode of a semiconductor memory device according to the present invention.

As shown in Fig. 9A, it is preferable to set the voltage value in the state in which the P-type channel region is turned on / off to the word line read voltage Vrd. That is, the word line read voltage Vrd flows the most bit line BL current when the channel region is on, and flows the least bit line BL current when the channel region is off.

As shown in FIG. 9B, when the voltage of the bit line BL is changed while the same word line read voltage Vrd is applied, the bit line BL current values are different according to the value of cell data stored in the memory cell. That is, when data "0" is stored in the memory cell, the bit line BL current flows a lot when the bit line BL voltage increases. On the other hand, when data " 1 " is stored in the memory cell, the bit line BL current does not change and flows less despite the increase in the bit line BL voltage.

10 is a timing diagram of a write cycle operation of the semiconductor memory device according to the present invention.

First, in the t0 section, R-bit data is read and amplified for all cells of the selected row address and stored in a register to be described later. In the t1 section, L-bit data is read and amplified for all cells of the selected row address and stored in a register to be described later.

That is, since data "0" is written to all the memory cells in the t2 section to be described later, it is not known what data is stored in the existing memory cell. Therefore, in order to know the data stored in the existing memory cell, the data is stored in the register before the data "0" is written to the memory cell.

Thereafter, in the period t2, data "0" is written to all cells of the selected row address. In the t3 section, the data stored in the register is rewritten to the memory cell in the refresh mode and restored, and the cells to be newly written are written with new external data. At this time, since the write operation of the data "0" has already been performed in the t2 section, the write operation is in the write "0" preserve mode, and new data is written to the data "1".

11 is a timing diagram of a refresh cycle operation of the semiconductor memory device according to the present invention.

First, in the t0 section, R-bit data is read and amplified for all cells of the selected row address and stored in a register. In the t1 section, L-bit data is read and amplified for all cells of the selected row address and stored in a register to be described later.

Subsequently, in a period t2, a refresh “0” operation for recovering the L-bit or R-bit data “0” among all cells of the selected row address is performed. In addition, in the period t3, a refresh "1" operation for recovering the L-bit or R-bit data "1" of all cells of the selected row address is performed.

12 is an overall configuration diagram of a semiconductor memory device according to the present invention.

The present invention provides the pad array 100, the refresh control means 110, the row address register 120, the row timing logic 130, the row decoder 140, the cell array 150, the read / The write control unit 160, the column decoder 170, the column address register 180, the column timing logic 190, the refresh status information register 200, the sense amplifier, the register and the write driver 210 , Input / output logic 220, I / O register 230, I / O buffer 240, and I / O pins 250.

Here, the refresh control means 110 includes a refresh controller 111 and a refresh counter 112. The cell array 150 of the present invention is configured to include a plurality of 1T-FET type unit cell structures according to FIG. 2.

The pad array 100 includes a plurality of pad PADs, and receives a row address and a column address through one pad and outputs them with a time difference. The refresh control unit 111 outputs the refresh signal REF and the refresh enable signal REF_EN for controlling the refresh operation according to the ras signal / RAS, the cas signal / CAS, the read / write command R, / W and the refresh control signal. .

The refresh counter 112 counts the refresh period according to the refresh signal REF applied from the refresh control unit 111 and the refresh control signal applied from the refresh state information register 200 to output the count address CA. The refresh control unit 111 and the refresh counter 112 output information about the refresh operation and the refresh count information to the refresh status information register 200.

The row address register 120 receives a row address applied from the pad array unit 100 and temporarily stores the row address. The row address register 120 outputs the activated row address RADD to the row decoder 140 according to the output of the row timing logic 130 and the read / write control signal RWCON applied from the read / write control unit 160. do.

The row timing logic 130 controls the storage operation and the address output timing of the row address register 120 according to the ras signal / RAS. The row decoder 140 decodes the activated row address RADD applied from the row address register 120 and outputs the decoded row address RADD to the cell array 150.

The read / write control unit 160 also controls read / write control signals to the row address register 120 in response to the ras signal / RAS, cas signal / CAS, and read / write commands R and / W. The RWCON is output and the operations of the column decoder 170, the sense amplifier, the register, and the write driver 210 are controlled.

The column decoder 170 decodes the column address applied from the column address register 180 under the control of the read / write controller 160 and outputs the decoded column address to the input / output logic 220. The column address register 180 receives a column address applied from the pad array 100 and temporarily stores the column address, and outputs the column address to the column decoder 170 under the control of the column timing logic 190.

In addition, the column timing logic 190 controls the storage operation and the address output timing of the column address register 180 according to the cas signal / CAS. The register 210 provides the refresh data to the memory cell under the control of the column timing logic 190 when the refresh signal REF is activated.

The refresh status information register 200 is a nonvolatile register for storing parameters related to refresh. The refresh status information register 200 stores the refresh count information, information on the power-off time of the system or the internal memory, and various other parameter information. The refresh control signal 200 provides a refresh control signal based on the parameter information during the refresh operation. Output In addition, at the time of power-off, information about the refresh control unit 111 and the refresh counter 112 is transmitted to the refresh status information register 200, and stores information related to an external command applied from the I / O buffer 240. do. In addition, information stored in the refresh status information register 200 is output to the system controller 300 through the I / O buffer 240 and the I / O pins 250.

The sense amplifier S / A is configured to detect and amplify cell data to distinguish data "1" from data "0". When writing data to a memory cell, the write driver W / D generates a driving voltage according to the write data to supply the bit line to the bit line. In addition, the register REG temporarily stores the data sensed by the sense amplifier S / A, and re-stores the data in the memory cell during the write operation.

The input / output logic 220 reads data stored in the cell array 150 or stores data in the cell array 150 according to the output of the column decoder 170 and the read / write commands R and / W. Here, the input / output logic 220 preferably includes a column select signal C / S. The input / output logic 220 then outputs the data stored in the cell array 150 to the data I / O register 230 according to the output enable signal / OE.

The I / O buffer 240 buffers read data stored in the I / O register 230 and outputs the buffered data to the I / O pins 250. The I / O buffer 240 buffers write data applied through the I / O pins 250 and outputs the buffered write data to the I / O register 230. The I / O buffer 240 outputs the information stored in the refresh status information register 200 to the system controller 300 through the I / O pins 250. The I / O pins 250 output data applied from the I / O buffer 240 to the system controller 300 through the data bus, or output data applied from the system controller 300 through the data bus. Output to the buffer 240.

Referring to the read / write operation process of the present invention having such a configuration as follows.

First, the pad array 100 receives a row address and a column address through a plurality of pad PADs and outputs them to the row address register 120 and the column address register 180, respectively. Subsequently, the row address register 120 and the column address register 180 are controlled by the row timing logic 130 and the column timing logic 190 by a timing multiplexing method. Output the column address.

At this time, the row address register 120 temporarily stores the row address in synchronization with the ras signal / RAS and outputs the activated row address RADD to the row decoder 140. In the output operation of the row address RADD, the column address register 180 temporarily stores the input column address.

The row address register 120 selects a row address applied from the pad array 100 during normal operation and outputs the row address to the row decoder 140. When the refresh enable signal REF_EN is activated in the refresh operation mode, the count address CA applied from the refresh counter 112 is selected and output to the row decoder 140.

On the other hand, the column address register 180 temporarily stores the column address in synchronization with the cas signal / CAS and outputs the column address to the column decoder 170. In the output operation of the column address, the row address register 120 temporarily stores the input row address.

Subsequently, when the output enable signal / OE is activated while the read command R is activated in the read operation mode, data stored in the cell array 150 is output to the I / O register 230 according to the input / output logic 220. do. On the other hand, when the output enable signal / OE is deactivated while the write command / W is activated in the write operation mode, data is stored in the cell array 150 according to the input / output logic 220.

A refreshing method of a semiconductor memory device according to the present invention will be described below.

The refresh control unit 111 refreshes the refresh signal REF for performing the refresh operation when the refresh operation command is applied according to the combination of the ras signal / RAS, the cas signal / CAS, the read / write command R, / W and the refresh control signal. The refresh enable signal REF_EN is output to the row address register 120. In addition, the refresh counter 112 counts the refresh period according to the refresh signal REF and the refresh control signal applied from the refresh control unit 111 and outputs the count address CA to the row address register 120.

The count address CA output from the refresh counter 112 is stored in the row address register 120. Thereafter, the column timing logic 190 outputs the data stored in the column address register 180 to the column decoder 170 in response to the cas signal / CAS. Then, in the state in which the sense amplifier S / A is activated, the refresh data stored in the register REG is written to the cell array 150 through the input / output logic 220.

Here, the refresh signal REF may be a control signal using the ras signal / RAS and the cas signal / CAS. That is, when the refresh signal REF is a control signal using the ras signal / RAS and the cas signal / CAS, the refresh operation is performed by using a cas biphoras (/ CBR; / CAS Before / RAS) method.

For example, in the normal operation mode for performing the read or write operation, the ras signal / RAS is activated before the cas signal / CAS and the normal operation is performed according to the row timing logic 130 and the column timing logic 190. . That is, when the ras signal / RAS is activated first, the external row address is activated, and the sense amplifier S / A is activated. After that, the external column address is activated when the cas signal / CAS is activated.

On the other hand, in the refresh mode, the refresh signal REF is activated by detecting that the cas signal / CAS is transitioned before the lath signal / RAS through the refresh control unit 111. That is, if the refresh control unit 111 detects that the cas signal / CAS is transitioned before the ras signal / RAS, the refresh control unit 111 determines the refresh mode and activates the refresh enable signal REF_EN.

When the refresh enable signal REF_EN is activated, the row address register 120 performs a refresh operation according to the count address CA generated by the refresh counter 112 while the path of the normal operation mode is blocked. Here, the refresh signal REF may be activated by detecting that the cas signal / CAS and the ras signal / RAS are simultaneously transitioned.

In the present invention, the refresh method using the cas biphoras (/ CBR; / CAS Before / RAS) method has been described as an embodiment, but the present invention is not limited to this, Self refresh, Auto refresh or The refresh operation may be performed through various methods similarly applicable using a clock or the like.

That is, in the refresh mode, the word line WL of the cell array 150 is selected according to the count address CA which is the output of the refresh counter 112. Accordingly, the cell array 150 senses and amplifies data of the corresponding cell having the 1T FET structure and stores the data in the sense amplifier register REG. Then, new data is written to the cell array 150 or data stored in the register REG is re-stored in the cell array 150.

Meanwhile, a refresh method according to on / off of a power source in the semiconductor memory device according to the present invention will be described as follows.

First, DRAM, which is a general volatile memory, starts uploading a new refresh operation by uploading memory data again when power is turned on while the system power is turned off. That is, when the system powers back on, the memory data must be uploaded unconditionally.

However, the semiconductor memory device according to the present invention determines whether the refresh time is exceeded in the refresh status information register 200 when the power is turned on while the system power is turned off.

As a result of the determination of the refresh status information register 200, when the preset refresh time is exceeded, memory data is uploaded again to start a new refresh operation. On the other hand, as a result of the determination of the refresh status information register 200, when the preset refresh time is not exceeded, it is determined that the refresh time is valid and continues the previous refresh operation.

That is, the refresh status information register 200 stores parameters related to refresh in a nonvolatile register. The refresh status information register 200 stores the refresh count information, the power-off time of the system or the internal memory, and various other parameter information in a nonvolatile state. Here, the refresh status information register 200 may detect that the power of the system or the internal memory is turned on / off through a separate power sensing means (not shown).

Accordingly, data stored in the refresh status information register 200 is read at power-off to calculate the elapsed refresh time. Here, the refresh elapsed time may be pre-stored through a separate mode register set (MRS), and the refresh elapsed time may be controlled at the system level.

Thereafter, the refresh elapsed time calculated according to the refresh control signal is transmitted to the refresh control unit 111 to control the refresh operation. Therefore, the present invention does not need to upload the refresh related information again even when the power is turned on in the power-off state.

A refreshing method of a semiconductor memory device according to the present invention will be described below. The refresh method according to the present invention is largely divided into a distributed refresh method and a burst refresh method.

First, the distributed refresh method is a method of performing a refresh operation at the same time allocation so that all cells can be refreshed within the refresh time according to the count address CA counted by the refresh counter 112. That is, if 8k rows are refreshed, the refresh operation is performed in a cycle in which each distributed refresh operation cycle is (refresh time) / 8k. Thus, data must be written for all word lines WL to be in an initialized state.

Second, the burst refresh method refers to a method of continuously performing an 8k refresh cycle during a burst refresh cycle time. Here, each pulse means each refresh cycle, and normal operation is performed in the read / write operation cycle section in which the pulse is inactive.

Meanwhile, the timer control operation in the refresh method of the semiconductor memory device according to the present invention will be described.

The refresh status information register 200 of the present invention determines whether the system power is off and stores the result. As a result of the determination of the refresh status information register 200, when the power is off, the refresh operation is controlled by using a system timer that the system has in the off state of the internal memory timer. These system timers mainly use batteries to store the date, time, etc., so that the power is always on.

On the other hand, as a result of the determination of the refresh status information register 200, the internal refresh operation is controlled using an internal memory timer that operates independently when the power is not turned off.

Herein, according to the present invention, one of the external system timer and the internal memory timer may be selected according to the on / off state of the power through the input / output data pins 250. That is, the refresh status information register 200 of the memory device including the internal memory timer exchanges data with the data bus through the I / O buffer 240 and the I / O pins 250. In addition, a system (CPU) including a system timer exchanges data with a memory device through a data bus.

Accordingly, the refresh operation is performed by using an external system timer that is always turned on when the power is turned off by exchanging data between the memory device and the system controller, and by using the internal memory timer when the power is turned on. Will perform the action.

The present invention can effectively maintain the refresh period and the memory data irrespective of whether the power supply of the memory chip is turned on or off. Accordingly, the memory chip power may be turned off between the refresh periods to reduce the current consumed by the chip, and the chip power may be supplied only during the refresh period to perform the refresh operation.

13 is a graph illustrating data retention characteristics of a semiconductor memory device according to the present invention.

In the conventional semiconductor memory device, the deterioration condition of the cell data occurs over time, and thus there is a limit in the data retention life. As a result, the bit line BL current corresponding to the cell data "1" and "0" decreases over time.

However, the present invention improves data retention characteristics by recovering deteriorated cell data by performing a refresh operation at a specific period when a bit line BL current decreases when the power supply is turned off.

That is, the present invention drives the refresh circuit to restore the cell data back to the initial state when the storage data holding characteristic of the memory cell is reduced to a predetermined target value or more. The deterioration threshold target time of the cell set as described above becomes the refresh time, and all the cells always operate within the refresh time.

Here, the present invention is a DRAM having a nonvolatile characteristic, so the power supply may be turned off. In addition, the sum of the on / off times of the power supply is set as the total data retention time, so that the refresh operation is not frequently performed, thereby reducing power consumption and improving operation performance.

14 is a plan view of a cell array of a semiconductor memory device according to the present invention.

In the cell array of the present invention, a plurality of word lines WL are arranged in a row direction. The plurality of bit lines BL are arranged in a direction perpendicular to the plurality of word lines WL. In addition, a plurality of unit cells C are positioned in an area where a plurality of word lines WL and a plurality of bit lines BL intersect.

Here, the bit lines BL <1>, BL <3>, BL <5>, BL <7>, BL <9> arranged in odd columns are bit lines for storing R-bits. The bit lines BL <0>, BL <2>, BL <4>, BL <6>, and BL <8> arranged in even columns are bit lines for storing L bits. And bit lines BL <1>, BL <3>, BL <5>, BL <7>, BL <9> in odd columns, and bitlines BL <0>, BL <2>, BL <4> in even columns , BL <6>, BL <8> are alternately arranged and are formed on different layers. Accordingly, when two bit lines BL are connected to one unit cell C, the area of the bit lines BL is prevented from increasing as compared with the related art.

That is, the bit lines BL <0>, BL <2>, of even columns in the upper or lower layers of the bit lines BL <1>, BL <3>, BL <5>, BL <7>, BL <9> in odd columns BL <4>, BL <6>, BL <8> are formed. And the bit lines BL <1>, BL <3>, of the even columns in the upper or lower layers of the even lines bit lines BL <0>, BL <2>, BL <4>, BL <6>, BL <8>. BL <5>, BL <7>, BL <9> are formed.

In addition, one unit bit cell C includes one word line WL and two bit lines BL disposed on different layers. For example, one unit cell C includes one word line WL <0>, an even bit line L-BL <2>, an odd bit line R-BL <3>, and a bit line contact BLC formed on different layers. Connected through.

15 is a diagram illustrating a cell array structure and an R-bit data read operation of a semiconductor memory device according to the present invention.

In the cell array of the present invention, a plurality of word lines WL are arranged in a row direction at regular intervals. The plurality of even / odd bit lines L-BL and R-BL are arranged in a vertical direction, that is, in a culling direction to intersect the plurality of word lines WL. In addition, a plurality of unit cells C are positioned in an area where a plurality of word lines WL and a plurality of even / odd bit lines L-BL and R-BL cross each other.

Here, the unit cell C of the 1-T (FET) field effect transistor (FET) structure is connected to one word line WL0 and two even / odd bit lines L-BL0 and R-BL1 formed on different layers. . In the present invention, one word line WL0 and an even / odd bit line pair L-BL0 and R-BL1 are described as an example for convenience of description, but the present invention is not limited thereto. The same applies to ... and the remaining plurality of even / odd bit line pairs L-BL2, R-BL3 ....

The drain / source terminal of the unit cell C is connected between the even / odd bit line pair L-BL0 and R-BL1, and the gate terminal is connected to the word line WL0. Each of the even / odd bit line pairs L-BL0 and R-BL1 arranged on different layers has one sense amplifier S / A, a write driver W / D, and a register REG. Connected with That is, each bit line BL is connected to one-to-one corresponding number of sense amplifiers S / A, write driver W / D, and register REG.

Here, the sense amplifier S / A is configured to detect and amplify the cell data to distinguish the data "1" from the data "0". The sense amplifier S / A is connected one-to-one with an even bit line L-BL0 and an odd bit line R-BL1. do. The sense amplifier S / A is applied with a reference voltage through the reference voltage terminal ref to generate a reference current.

The write driver W / D generates a driving voltage according to the write data to supply the bit line BL when the data is written to the memory cell. The write driver W / D corresponds to the even bit line L-BL0 and the odd bit line R-BL1. Is connected. In addition, the register REG is a temporary storage device for temporarily storing the data of the sense amplifier S / A and is connected in one-to-one correspondence with the even bit line L-BL0 and the odd bit line R-BL1.

The cell array of the present invention having the structure applies the read voltage Vrd to the selected word line WL0 in the read operation mode of the R-bit data, and applies the ground voltage GND to the remaining unselected word lines WL1 and WL2. A sensing bias voltage Vsen for sensing the sensing current of the unit cell C is applied to the even bit line L-BL0 connected to the unit cell C. The ground voltage GND is applied to the other odd bit line R-BL1.

In this case, the cell sensing current Isen flows according to the storage state of the cell data. Accordingly, the current flowing through the even / odd bit line pairs L-BL0 and R-BL1 varies according to the polarity of the ferroelectric layer 4, so that cell data stored in the unit cell C can be read.

That is, while the read voltage Vrd is applied to the word line WL0, the sensing bias voltage Vsen is applied to the even bit line L-BL0, and the ground voltage GND is applied to the odd bit line R-BL1, the odd bit line R-BL1 is applied. The value of the cell sensing current Isen flowing in is sensed through the sense amplifier S / A to read R-bit data.

Accordingly, when the channel region of the memory cell is turned off, the cell sensing current Isen may be sensed to read data “1” stored in the R-bit storage unit 20. On the other hand, when the channel region is turned on, data “0” stored in the R-bit storage unit 20 may be read by sensing the value of the cell sensing current Isen.

16 is a diagram illustrating a cell array structure and an L-bit data read operation of a semiconductor memory device according to the present invention.

The cell array of the present invention applies the read voltage Vrd to the selected word line WL0 and the ground voltage GND to the remaining unselected word lines WL1 and WL2 in the read operation mode of the L-bit data. The ground voltage GND is applied to the even bit line L-BL0 connected to the unit cell C. A sensing bias voltage Vsen for sensing the sensing current of the unit cell C is applied to the other odd bit line R-BL1.

In this case, the cell sensing current Isen flows according to the storage state of the cell data. Accordingly, the current flowing through the even / odd bit line pairs L-BL0 and R-BL1 varies according to the polarity of the ferroelectric layer 4, so that cell data stored in the unit cell C can be read.

That is, while the read voltage Vrd is applied to the word line WL0, the ground voltage GND is applied to the even bit line L-BL0, and the sensing bias voltage Vsen is applied to the odd bit line R-BL1, the even bit line L-BL0 is applied. The value of the cell sensing current Isen flowing in is sensed through the sense amplifier S / A to read L-bit data.

Accordingly, when the channel region of the memory cell is turned off, the cell sensing current Isen may be sensed to read data “1” stored in the L-bit storage unit 10. On the other hand, when the channel region is turned on, the data "0" stored in the L-bit storage unit 10 may be read by sensing the value of the cell sensing current Isen.

17 is a view for explaining a '0000 ...' write operation of the semiconductor memory device according to the present invention.

The cell array according to the present invention applies a power supply voltage VDD equal to or greater than the threshold voltage Vc at which the polarization characteristic of the ferroelectric varies in the selected word line WL0 in the write operation mode of the data '0000', and grounds the remaining unselected word lines WL1 and WL2. Apply voltage GND. The ground voltage is applied to all the even / odd bit line pairs L-BL and R-BL connected to the unit cell C.

Here, it is preferable that the read voltage Vrd is set smaller than the threshold voltage Vc, and the power supply voltage VDD is set larger than the threshold voltage Vc. In addition, the sensing bias voltage Vsen is preferably set smaller than the read voltage Vrd.

In this case, the ferroelectric material is polarized while the channel region of the memory cell is turned on. Accordingly, data '0000 ..' can be written to the memory cell. In other words, while the power supply voltage VDD is applied to the word line WL0 and the ground voltage is applied to the even / odd bit line pairs L-BL and R-BL, the channel region is turned on according to the polarization of the ferroelectric layer 4, The data '0000 ...' can be written to the cell.

FIG. 18 is a diagram for describing a '0101 ...' write operation of the semiconductor memory device according to the present invention.

The cell array of the present invention applies the negative read voltage -Vrd to the selected word line WL0 in the write operation mode of the data '0101', and applies the ground voltage GND to the remaining unselected word lines WL1 and WL2. Here, the negative read voltage -Vrd is a voltage value having an absolute value equal to the read voltage Vrd and having an opposite phase. The ground voltage is applied to all of the even bit lines L-BL connected to the unit cell C. The positive read voltage Vrd is applied to all the odd bit lines R-BL connected to the unit cell C.

In this case, a positive read voltage Vrd is applied to the N-type drain / source region 3 of the odd bit line R-BL, and a negative read voltage -Vrd is applied to the gate terminal so that the polarization of the ferroelectric layer 4 changes. It will be applied above Vc. As a result, the ferroelectric material is polarized while the channel region of the memory cell is turned off.

Accordingly, a voltage equal to or lower than the threshold voltage Vc is applied to the even bit line L-BL of the selected row so that the L-bit storage unit 10 of the memory cell maintains data '0'. Then, the data '1' can be written to the R-bit storage unit 20. That is, in the state where the negative read voltage -Vrd is applied to the word line WL0 and the ground voltage and the positive read voltage Vrd are applied to the even / odd bit line pair L-BL and R-BL, respectively, the ferroelectric layer 4 According to the polarization of the channel region, the channel region is turned off so that data '0101 ...' can be written to the memory cell.

FIG. 19 is a diagram for describing a '1010 ...' write operation of a semiconductor memory device according to the present invention.

The cell array of the present invention applies a negative read voltage -Vrd to the selected word line WL0 and a ground voltage GND to the remaining unselected word lines WL1 and WL2 in the write operation mode of the data '1010'. The positive read voltage Vrd is applied to all of the even bit lines L-BL connected to the unit cell C. The ground voltage is applied to all of the odd bit lines R-BL connected to the unit cell C.

In this case, a positive read voltage Vrd is applied to the N-type drain / source region 2 of the even bit line L-BL, and a negative read voltage -Vrd is applied to the gate terminal so that the polarization of the ferroelectric layer 4 changes. It will be applied above Vc. As a result, the ferroelectric material is polarized while the channel region of the memory cell is turned off.

Accordingly, a voltage lower than or equal to the threshold voltage Vc is applied to the odd bit line R-BL of the selected row, so that the R-bit storage unit 20 of the memory cell maintains data '0'. Then, data '1' can be written to the L-bit storage unit 10. That is, in the state where the negative read voltage -Vrd is applied to the word line WL0 and the positive read voltage Vrd and the ground voltage are applied to the even / odd bit line pair L-BL and R-BL, respectively, the ferroelectric layer 4 According to the polarization of the channel region, the channel region is turned off so that data '0101 ...' can be written to the memory cell.

20 is a view for explaining a '1111 ...' write operation of the semiconductor memory device according to the present invention.

The cell array of the present invention applies a negative read voltage -Vrd to the selected word line WL0 in the write operation mode of the data '1111', and applies a ground voltage GND to the remaining unselected word lines WL1 and WL2. The ground voltage is applied to all the even / odd bit line pairs L-BL and R-BL connected to the unit cell C.

In this case, the ferroelectric material is polarized with the channel region of the memory cell turned off. Accordingly, data '1111 ..' can be written to the memory cell. That is, in the state where the negative read voltage -Vrd is applied to the word line WL0 and the positive read voltage Vrd is applied to the even / odd bit line pairs L-BL and R-BL, the polarization of the ferroelectric layer 4 is performed. The channel region is turned off so that data '1111 ...' can be written to the memory cell.

21 is a timing diagram related to a read operation of the semiconductor memory device according to the present invention.

First, the word line WL0 selected in the period t1 transitions from the ground GND level to the read voltage Vrd level. In order to sense the R-bit data, the even bit line L-BL transitions from the ground GND level to the sensing bias voltage Vsen level. In this case, the value of the cell sensing current Isen flowing through the even bit line L-BL is sensed and amplified through the sense amplifier S / A. The cell data of the odd bit line R-BL is read and stored in the register REG.

Thereafter, the selected word line WL0 transitions from the ground GND level to the read voltage Vrd level in the t2 period. In order to sense the L-bit data, the odd bit line R-BL transitions from the ground GND level to the sensing bias voltage Vsen level. In this case, the value of the cell sensing current Isen flowing through the odd bit line R-BL is sensed and amplified by the sense amplifier S / A. The cell data of the even bit line L-BL is read and stored in the register REG.

22 is a timing diagram related to the write / refresh operation of the semiconductor memory device according to the present invention.

First, the word line WL0 selected in the period t1 transitions from the ground GND level to the read voltage Vrd level. The even bit line L-BL transitions from the ground GND level to the sensing bias voltage Vsen level. In this case, the values of the cell sensing current Isen flowing through the even bit line L-BL are sensed and sensed through the sense amplifier S / A for all the cells of the selected row. The cell data of the odd bit line R-BL is read and stored in the register REG.

Thereafter, the selected word line WL0 transitions from the ground GND level to the read voltage Vrd level in the t2 period. The odd bit line R-BL transitions from the ground GND level to the sensing bias voltage Vsen level. In this case, the value of the cell sensing current Isen flowing through the odd bit line R-BL is sensed and sensed through the sense amplifier S / A for all cells of the selected row. The cell data of the even bit line L-BL is read and stored in the register REG.

Then, in the period t3, the selected word line WL0 transitions from the read voltage Vrd level to the power supply voltage VDD level, and the even or odd bit lines L-BL and R-BL read the read voltage Vrd or ground voltage GND level at the sensing bias voltage Vsen level. To transition to. In this case, data '0' can be written for all cells of the selected row.

Then, the selected word line WL0 transitions from the power supply voltage VDD level to the negative read voltage -Vrd level in the period t4, and the even or odd bit lines L-BL and R-BL maintain the read voltage Vrd or ground voltage GND level. . In this case, data stored in the register REG may be written back to the memory cell to recover data, or new data applied from the outside may be written.

At this time, since the data '0' is already written in the t1 or t2 section, the data '0' is maintained in the t3 section, and a new write operation is performed on the data '1'.

23 is a plan view of a cell array of a semiconductor memory device according to the present invention.

In the cell array of the present invention, a plurality of word lines WL are arranged in a row direction. The plurality of bit lines BL are arranged in a direction perpendicular to the plurality of word lines WL. In addition, a plurality of unit cells C are positioned in an area where a plurality of word lines WL and a plurality of bit lines BL intersect.

Here, the bit lines BL <1>, BL <3>, BL <5>, BL <7>, BL <9> arranged in odd columns are bit lines for storing R-bits. The bit lines BL <0>, BL <2>, BL <4>, BL <6>, and BL <8> arranged in even columns are bit lines for storing L bits. And bit lines BL <1>, BL <3>, BL <5>, BL <7>, BL <9> in odd columns, and bitlines BL <0>, BL <2>, BL <4> in even columns , BL <6>, BL <8> are alternately arranged and are formed on different layers. Accordingly, when two bit lines BL are connected to one unit cell C, the area of the bit lines BL is prevented from increasing as compared with the related art.

That is, the bit lines BL <0>, BL <2>, of even columns in the upper or lower layers of the bit lines BL <1>, BL <3>, BL <5>, BL <7>, BL <9> in odd columns BL <4>, BL <6>, BL <8> are formed. And the bit lines BL <1>, BL <3>, of the even columns in the upper or lower layers of the even lines bit lines BL <0>, BL <2>, BL <4>, BL <6>, BL <8>. BL <5>, BL <7>, BL <9> are formed.

In addition, one unit bit cell C includes one word line WL and two bit lines BL disposed on different layers. For example, one unit cell C includes one word line WL <0>, an even bit line L-BL <2>, an odd bit line R-BL <3>, and a bit line contact BLC formed on different layers. Connected through.

24 is a diagram illustrating a cell array structure, a write driver W / D, a sense amplifier S / A, and a register REG of the semiconductor memory device according to the present invention.

The sense amplifier S / A is configured to sense and amplify cell data to distinguish data “1” from data “0” and is connected to each even bit line R-BL. In addition, the register REG is a temporary storage device for temporarily storing the data of the sense amplifier S / A and is connected to each even bit line R-BL. Here, the sense amplifier S / A and the register REG are connected to the input / output line IO // IO which is a data bus.

The write driver W / D generates a driving voltage according to the write data and supplies the driving voltage to the odd bit line L-BL when the data is written to the memory cell, and is connected to each odd bit line L-BL.

25 is a circuit diagram of a row decoder 140 of the semiconductor memory device according to the present invention.

The row decoder 140 controls the voltage level supplied to the word line WL according to the input of the row address. The row decoder 140 includes a row address decoder 400, a voltage supply unit 410, and a word line driver 430.

Here, the row address decoder 400 includes a NAND gate ND1 for NAND-operating the input of the row address and outputting the enable signal ENB.

The voltage supply unit 410 includes a plurality of NMOS transistors N1 to N3 which are switching elements. The NMOS transistor N1 is connected between the first voltage V1 applying end and the word line driver 430 to receive the voltage control signal V1_C through the gate terminal. The NMOS transistor N2 is connected between the second voltage V2 applying terminal and the word line driver 430 to receive the voltage control signal V2_C through the gate terminal. The NMOS transistor N3 is connected between the third voltage V3 applying end and the word line driver 430 to receive the voltage control signal V3_C through the gate terminal.

In the embodiment of the present invention, it is preferable that the first voltage V1, the second voltage V2, and the third voltage V3 supplied to the word line WL consist of a read voltage Vrd, a power supply voltage VDD, and a negative read voltage -Vrd, respectively.

That is, as shown in FIGS. 15 and 16, the read voltage Vrd may be supplied to the selected word line WL0 at the first voltage V1 during the data read operation. As illustrated in FIG. 17, the power supply voltage VDD may be supplied to the selected word line WL0 as the second voltage V2 during the write operation of data '00'. 18 to 20, a negative read voltage -Vrd may be supplied to the selected word line WL0 as the third voltage V3 during the write operation of the data '01', '10', and '11'. .

In addition, the word line driver 430 includes a word line driver, a pull-down device, and an inverter IV1 connected in series between the voltage supply unit 410 and the ground voltage terminal. Here, the common connection terminal of the NMOS transistor N4, which is a word line driving element, and the NMOS transistor N5, which is a pull-down element, is connected to the word line WL.

The enable signal ENB, which is an output of the row address decoder 400, is applied to the NMOS transistor N5 through a gate terminal. Inverter IV1 inverts enable signal ENB and outputs enable signal EN. The NMOS transistor N4 is supplied with the enable signal EN through the gate terminal.

FIG. 26 is an operational waveform diagram illustrating the row decoder 140 of FIG. 25.

First, the enable signal ENB is activated to a low level when a row address is input in the t0 period. As a result, the NMOS transistor N5 remains turned off, and the NMOS transistor N4 is turned on. When the voltage control signal V1_C is activated in this state, the NMOS transistor N1 is turned on to supply the first voltage V1 to the word line WL.

Thereafter, the enable signal ENB maintains a low level in the period t1. As a result, the NMOS transistor N5 remains turned off, and the NMOS transistor N4 is turned on. When the voltage control signal V2_C is activated in this state, the NMOS transistor N2 is turned on to supply the second voltage V2 to the word line WL.

Subsequently, the enable signal ENB maintains a low level in the period t2. As a result, the NMOS transistor N5 remains turned off, and the NMOS transistor N4 is turned on. When the voltage control signal V3_C is activated in this state, the NMOS transistor N3 is turned on to supply the third voltage V3 to the word line WL.

Next, the enable signal ENB is deactivated to a high level when the row address is not input after the period t2. Accordingly, the NMOS transistor N5 is turned on to supply the ground voltage to the word line WL.

FIG. 27 is a detailed circuit diagram of the write driver W / D and the sense amplifier S / A of FIG. 24.

The sense amplifier S / A includes a column selector 500, an equalizing unit 510, a register unit 520, a pull-up unit 530, an amplifying unit 540, an amplification activation control unit 550, The rod part 560 and 562 and the bias control part 570 and 572 are included.

Here, the column selector 500 includes NMOS transistors N6 and N7. The NMOS transistors N6 and N7 are connected between the input / output lines IO and / IO and the output terminals OUT and / OUT, respectively, and the column select signal YS is applied through the common gate terminal.

The equalizing unit 510 includes PMOS transistors P1 to P3. The PMOS transistor P1 is connected between the supply voltage VDD supply stage and the output terminal OUT. The PMOS transistor P3 is connected between the supply voltage VDD terminal and the output terminal / OUT. The PMOS transistor P2 is connected between the output terminals OUT and / OUT. The PMOS transistors P1 to P3 receive a sense amplifier equalizing signal SEQ through a common gate terminal.

The register unit 520 forms a pair of inverter latch structures and includes PMOS transistors P4 and P5 and NMOS transistors N8 and N9. PMOS transistors P4 and P5 and NMOS transistors N8 and N9 are cross coupled. In the embodiment of the present invention, for convenience of description, the register REG is described as a register unit 520.

The pull-up unit 530 includes a PMOS transistor P6. Here, the PMOS transistor P6 is connected between nodes of both ends of the sense amplifier, and the sense amplifier equalizing signal SEQ is applied through the gate terminal.

The amplifier 540 includes NMOS transistors N10 and N11. The NMOS transistor N10 is connected between the NMOS transistors N8 and N12 so that the cell voltage Vcell is applied through the gate terminal. The NMOS transistor N11 is connected between the NMOS transistors N6 and N9 so that the reference voltage Vref is applied through the gate terminal.

The amplification activation control unit 550 is connected between the amplifying unit 540 and the ground voltage terminal to receive the sense amplifier enable signal SEN through the gate terminal.

The load unit 560 includes a PMOS transistor P7. Here, the PMOS transistor P7 is connected between the power supply voltage terminal and the bit line R-BL so that the load voltage Vload is applied through the gate terminal.

The load unit 562 includes a PMOS transistor P8. Here, the PMOS transistor P8 is connected between the power supply voltage terminal and the reference voltage Vref applying terminal, and the load voltage Vload is applied through the gate terminal.

The bias control unit 570 includes an NMOS transistor N13. Here, the NMOS transistor N13 is connected between the cell voltage Vcell applying terminal and the bit line R-BL to apply the clamp voltage VCLMP through the gate terminal.

The bias control unit 572 includes an NMOS transistor N14. Here, the NMOS transistor N14 is connected between the reference voltage Vref applying terminal and the reference current Iref terminal, and the clamp voltage VCLMP is applied through the gate terminal.

The word line driver W / D is connected between the output terminal OUT and the write control unit 580. The write controller 580 includes an NMOS transistor N15 connected between the write driver W / D and the bit line L-BL to which the write control signal WCS is applied through the gate terminal.

An operation process of the sense amplifier S / A having such a configuration will be described with reference to the waveform diagram of FIG. 28 as follows.

When the clamp voltage VCLMP rises, the NMOS transistor N13 turns on to deliver the bit line current Icell of the main cell. When the clamp voltage VCLMP rises, the NMOS transistor N14 is turned on to transfer the reference current Iref.

The load units 560 and 562 include PMOS transistors P7 and P8 controlled by the load voltage Vload. By the load values of the PMOS transistors P7 and P8, the current Icell and the reference current Iref of the bit line BL are converted into the cell voltage Vcell and the reference voltage Vref.

The amplification activation control unit 550 is controlled by the sense amplifier enable signal SEN. The amplifier 540 is activated according to the state of the amplification activation controller 550. Here, the amplifier 540 amplifies the cell voltage Vcell and the reference voltage Vref using gains of the NMOS transistors N10 and N11.

Both nodes of the sense amplifier are precharged to a high level during the precharge period according to the operation of the pull-up unit 530. This improves the primary amplification characteristics of the sense amplifier S / A. The voltage amplified by the amplifier 540 is transferred to and stored in the register unit 520. That is, the register unit 520 temporarily stores the write data and the write data while the sense amplifier enable signal SEN is activated.

In addition, the register unit 520 exchanges data with the input / output lines IO and / IO according to the column selection signal YS. It serves to amplify the gain of the amplifier 540 once again to improve the offset characteristics of the sense amplifier S / A. The equalizing unit 510 precharges the output of the register unit 520 to a high level during the patch charging period.

The column selector 500 turns on the NMOS transistors N6 and N7 when the column select signal YS is activated. Accordingly, the output terminals OUT and / OUT and the input and output lines IO and / IO are selectively connected. The write driver W / D transfers data of the input / output line IO // IO to the bit line L-BL when the write control signal WCS is activated, or transfers the data stored in the register unit 520 to the bit line L-BL.

As described above, the present invention has the following effects.

First, the present invention applies a 1T-FET ferroelectric memory cell having a nonvolatile characteristic to a DRAM and stores a dual-bit in one unit cell to store a cell area. To be cut in half.

Second, the present invention can improve data retention characteristics without losing refresh information even when power is turned off in DRAMs having 1T-FET ferroelectric memory cells having nonvolatile characteristics. To be present.

Third, since the present invention has a non-volatile characteristic, the on / off time of the power supply is set to the total data retention time, so that the refresh operation is not frequently performed, thereby reducing power consumption and improving operation performance.

Fourth, the present invention provides an effect of maintaining the refresh information even when the power supply is turned off by performing the refresh operation according to the parameter information stored in the nonvolatile register when the power supply is turned off.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (61)

A channel region formed on the substrate; A drain region and a source region formed at both ends of the channel region; A ferroelectric layer formed on the channel region; And a word line formed on the ferroelectric layer, wherein a one-transistor (FET) field effect transistor (FET) type memory cell in which different channel resistances are induced in the channel region according to the polarity of the ferroelectric layer. A semiconductor memory device comprising: A left-bit storage unit for storing left-bit data applied through the first drain / source region; And A write-bit storage unit for storing write-bit data applied through the second drain / source region, A cell sensing current value that varies according to the polarity of the ferroelectric layer in a state in which a read voltage is applied to the word line and a sensing bias voltage is applied to one of the first drain / source region and the second drain / source region. The read operation of the double-bit data is performed by sensing the voltage, and the polarity of the ferroelectric layer is changed according to the voltage applied to the word line, the first drain / source region, and the second drain / source region. A semiconductor memory device employing a ferroelectric element, characterized in that data write operation is performed. The semiconductor memory device of claim 1, wherein a ground voltage is applied to the remaining regions of the first drain / source region and the second drain / source region. The method of claim 1, wherein a value at which currents of the first and second drain / source regions become maximum / minimum in the region where the channel region is on / off is set as a voltage value of the read voltage. Semiconductor memory device using a ferroelectric element. 4. The semiconductor memory device according to claim 1 or 3, wherein the read voltage is smaller than a threshold voltage value at which the polarization characteristic of the ferroelectric varies. The semiconductor memory device of claim 1, wherein the sensing bias voltage is smaller than the read voltage. The method of claim 1, wherein a power supply voltage is applied to the word line during a data '00' write operation to the left-bit storage unit and the write-bit storage unit, and grounded to the first and second drain / source regions. A semiconductor memory device employing a ferroelectric element, characterized in that a voltage is applied. 7. The semiconductor memory device according to claim 6, wherein the power supply voltage is larger than a threshold voltage value at which the polarization characteristic of the ferroelectric varies. The method of claim 1, wherein a negative read voltage is applied to the word line during data write operation of the left-bit storage unit and the write-bit storage unit, and a ground voltage is applied to the first drain / source region. And a ferroelectric element is applied to the second drain / source region. 2. The method of claim 1, wherein a negative read voltage is applied to the word line and data is positively applied to the first drain / source area during data write operation of the left-bit storage unit and the write-bit storage unit. And a read voltage is applied and a ground voltage is applied to the second drain / source region. 10. The semiconductor memory device according to claim 8 or 9, wherein the positive read voltage and the negative read voltage are voltage values having the same absolute value and opposite phases. The method of claim 1, wherein a negative read voltage is applied to the word line during the data '11' write operation to the left-bit storage unit and the write-bit storage unit, and the first and second drain / sources. A semiconductor memory device employing a ferroelectric element, wherein a positive read voltage is applied to a region. The semiconductor memory device of claim 1, further comprising a row decoder configured to control a voltage level supplied to the word line according to the input of the row address. A channel region, a drain region and a source region formed on the substrate; A ferroelectric layer formed on the channel region; A 1-T (One-Transistor) field effect transistor (FET) type memory cell including a word line formed on the ferroelectric layer and having different channel resistances induced in the channel region according to the polarity of the ferroelectric layer. A semiconductor memory device comprising: A plurality of word lines arranged in a row direction; A plurality of even bit lines arranged in a direction perpendicular to the plurality of word lines; And A plurality of odd bit lines arranged in a direction perpendicular to the plurality of word lines and alternately arranged with the plurality of even bit lines; The memory cell is connected between an even / odd bit line pair adjacent to each other among the plurality of even and odd bit lines, according to respective voltages applied to the word line and the even / odd bit line pair. And a polarity of the ferroelectric layer is changed to read / write dual-bit data. The semiconductor memory device of claim 13, wherein the memory cell further comprises a buffer insulating layer formed between the channel region and the ferroelectric layer. The semiconductor memory device of claim 13, wherein the plurality of even bit lines and the plurality of odd bit lines are formed on different layers. The method of claim 13, wherein the memory cell is A left-bit storage unit for storing left-bit data applied through the even bit line; And And a write-bit storage unit configured to store write-bit data applied through the odd bit lines. The memory device of claim 13, wherein a read voltage is applied to the word line of the memory cell, a sensing bias voltage is applied to one bit line of the even / odd bit line pair, and a ground voltage is applied to the remaining bit lines. The semiconductor memory device of claim 1, wherein a read operation is performed by sensing a cell sensing current value flowing through the bit line to which the ground voltage is applied. 18. The ferroelectric device of claim 17, wherein a value at which the current of the even / odd bit line pair becomes the maximum / minimum in the region where the channel region is turned on / off is set to the voltage value of the read voltage. Semiconductor memory device. 19. The semiconductor memory device according to claim 17 or 18, wherein the read voltage is smaller than a threshold voltage value at which the polarization characteristic of the ferroelectric varies. 18. The semiconductor memory device of claim 17, wherein the sensing bias voltage is smaller than the read voltage. 18. The method of claim 13 or 17, wherein the memory cell A sense amplifier for amplifying data sensed through the even / odd bit line pair; A write driver configured to generate a driving voltage according to write data and to supply the even / odd bit line pair when writing data to the memory cell; And And a register for storing data amplified by the sense amplifier. 22. The semiconductor memory device of claim 21, wherein each of the sense amplifier and the register is connected in one-to-one correspondence with the even bit line, and the write driver is connected in one-to-one correspondence with the odd bit line. The method of claim 21, wherein the sense amplifier A column selector for selectively connecting an input / output line and the register; An equalizing unit for equalizing the registers; A pull-up unit which pulls up both nodes of the register; An amplifier for amplifying the cell voltage and the reference voltage; An amplification activation control unit controlling whether the amplification unit is activated; A load unit configured to control the load of the cell voltage and the reference voltage; And And a bias controller for controlling the current and the reference current of the bit line. The semiconductor memory device of claim 13, wherein a power supply voltage is applied to the word line and a ground voltage is applied to the even / odd bit line pair during data '00' writing operation to the memory cell. . 25. The semiconductor memory device according to claim 24, wherein the power supply voltage is larger than a threshold voltage value at which the polarization characteristic of the ferroelectric varies. The method of claim 13, wherein a negative read voltage is applied to the word line, a ground voltage is applied to the even bit line, and a positive read voltage is applied to the odd bit line during a data '01' write operation to the memory cell. A semiconductor memory device employing a ferroelectric element, characterized in that applied. 15. The memory device of claim 13, wherein a negative read voltage is applied to the word line, a positive read voltage is applied to the even bit line, and a ground voltage is applied to the odd bit line. A semiconductor memory device employing a ferroelectric element, characterized in that applied. 28. The semiconductor memory device according to claim 26 or 27, wherein the positive read voltage and the negative read voltage are voltage values having the same absolute value and opposite phases. The ferroelectric device of claim 13, wherein a negative read voltage is applied to the word line and a positive read voltage is applied to the even / odd bit line pair when the data '11' is written to the memory cell. Applied semiconductor memory device. The semiconductor memory device of claim 13, further comprising a row decoder configured to control a voltage level supplied to the word line in response to an input of a row address. 33. The method of claim 30, wherein the loo decoder is A row address decoder configured to output an enable signal according to the row address; A voltage supply unit supplying a corresponding voltage to the word line according to a voltage control signal; And And a word line driver configured to control a voltage level of the word line according to a voltage applied through the voltage supply in response to the input of the enable signal. The method of claim 31, wherein the voltage supply unit First switching means for supplying a read voltage in accordance with the first voltage control signal; Second switching means for supplying a power supply voltage in accordance with the second voltage control signal; And And a third switching means for supplying a negative read voltage in accordance with the third voltage control signal. 32. The device of claim 31, wherein the word line driver A word line driver for selectively supplying the voltage to the word line according to the output of the row address decoder; And And a pull-down device configured to pull down the word line according to the output of the row address decoder. A channel region, a drain region and a source region formed on the substrate; A ferroelectric layer formed on the channel region; A 1-T (One-Transistor) field effect transistor (FET) type memory cell including a word line formed on the ferroelectric layer, wherein different channel resistances are induced in the channel region according to the polarity of the ferroelectric layer; A plurality of word lines arranged in a row direction; A plurality of even bit lines arranged in a direction perpendicular to the plurality of word lines; A plurality of odd bit lines arranged in a direction perpendicular to the plurality of word lines and alternately arranged with the plurality of even bit lines; And Refresh control means for performing a refresh operation at a specific refresh cycle to improve retention characteristics of data stored in the memory cell; The memory cell is connected between the even / odd bit line pairs adjacent to each other among the plurality of even bit lines and the odd bit lines, and the memory cells are connected according to respective voltages applied to the word line and the even / odd bit line pairs. A semiconductor memory device employing a ferroelectric element, characterized in that the polarity of the ferroelectric layer is changed to read / write double-bit data. 35. The apparatus of claim 34, wherein the refresh control means A refresh status information register which stores various parameter information for controlling the refresh operation in a nonvolatile manner and outputs a refresh control signal corresponding thereto; A refresh controller configured to output a refresh signal and a refresh enable signal to perform a refresh operation according to the refresh control signal; A refresh counter for counting a refresh period according to the refresh signal and outputting a count address; And And a row address register for selecting the count address and outputting the count address to the row decoder when the refresh enable signal is activated. 35. The semiconductor memory device of claim 34, further comprising a register for providing refresh data to the memory cell. 37. The semiconductor memory device of claim 36, further comprising column timing logic for activating the register during the refresh operation. 38. The semiconductor memory device according to claim 37, further comprising a pad array unit which is shared by input addresses and selectively inputs the input addresses with a predetermined time difference using a multiplexing scheme. 36. The semiconductor memory device of claim 35, wherein the refresh status information register stores refresh count information and information on power-off time of the system / internal memory. 36. The semiconductor memory device of claim 35, wherein the refresh signal is activated at a time when the cas signal transitions before the lath signal. 35. The semiconductor memory device of claim 34, wherein the memory cell further comprises a buffer insulating layer formed between the channel region and the ferroelectric layer. 35. The semiconductor memory device of claim 34, wherein the plurality of even bit lines and the plurality of odd bit lines are formed on different layers. 35. The memory cell of claim 34, wherein the memory cell is A left-bit storage unit for storing left-bit data applied through the even bit line; And And a write-bit storage unit configured to store write-bit data applied through the odd bit lines. 35. The method of claim 34, wherein a read voltage is applied to the word line of the memory cell, a sensing bias voltage is applied to one bit line of the even / odd bit line pair, and a ground voltage is applied to the remaining bit lines. The semiconductor memory device of claim 1, wherein a read operation is performed by sensing a cell sensing current value flowing through the bit line to which the ground voltage is applied. 45. The ferroelectric device according to claim 44, wherein a value at which the current of the even / odd bit line pair becomes the maximum / minimum in the region where the channel region is on / off is set to the voltage value of the read voltage. Semiconductor memory device. 46. The semiconductor memory device according to claim 44 or 45, wherein the read voltage is smaller than a threshold voltage value at which the polarization characteristic of the ferroelectric varies. 45. The semiconductor memory device of claim 44, wherein the sensing bias voltage is smaller than the read voltage. 45. The memory cell of claim 34 or 44, wherein the memory cell is A sense amplifier for amplifying data sensed through the even / odd bit line pair; A write driver configured to generate a driving voltage according to write data and to supply the even / odd bit line pair when writing data to the memory cell; And And a register for storing data amplified by the sense amplifier. 49. The semiconductor memory device according to claim 48, wherein each of the sense amplifier, the write driver, and the register is connected in one-to-one correspondence with the even bit line and the odd bit line. 35. The semiconductor memory device of claim 34, wherein a power supply voltage is applied to the word line and a ground voltage is applied to the even / odd bit line pair during data '00' write operation to the memory cell. . 51. The semiconductor memory device according to claim 50, wherein the power supply voltage is larger than a threshold voltage value at which the polarization characteristic of the ferroelectric is changed. 35. The method of claim 34, wherein a negative read voltage is applied to the word line, a ground voltage is applied to the even bit line, and a positive read voltage is applied to the odd bit line during a data '01' write operation to the memory cell. A semiconductor memory device employing a ferroelectric element, characterized in that applied. 35. The memory cell of claim 34, wherein a negative read voltage is applied to the word line, a positive read voltage is applied to the even bit line, and a ground voltage is applied to the odd bit line. A semiconductor memory device employing a ferroelectric element, characterized in that applied. 54. The semiconductor memory device according to claim 52 or 53, wherein the positive read voltage and the negative read voltage are voltage values having the same absolute value and opposite phases. 35. The ferroelectric device of claim 34, wherein a negative read voltage is applied to the word line and a positive read voltage is applied to the even / odd bit line pair during data '11' write operation to the memory cell. Applied semiconductor memory device. 35. The semiconductor memory device according to claim 34, further comprising a row decoder for controlling a voltage level supplied to the word line in response to an input of a row address. A plurality of word lines arranged in a row direction; A plurality of even bit lines arranged in a direction perpendicular to the plurality of word lines; A plurality of odd bit lines arranged in a direction perpendicular to the plurality of word lines and alternately arranged with the plurality of even bit lines; And A channel region, a drain region and a source region formed on the substrate; A ferroelectric layer formed on the channel region; A word line formed on an upper portion of the ferroelectric layer, the polarity of the ferroelectric layer being changed according to a voltage applied between the pair of adjacent bit lines among the plurality of bit lines and applied to the word line and the pair of bit lines 1-T (One-Transistor) field effect transistor (FET) type memory cells, The memory cell is connected between the even / odd bit line pairs adjacent to each other among the plurality of even bit lines and the odd bit lines, and the memory cells are connected according to respective voltages applied to the word line and the even / odd bit line pairs. A semiconductor memory device in which a polarity of a ferroelectric layer is changed to read / write double-bit data, Reading and writing data by inducing different channel resistances in a channel region of the 1T-FET type memory cell; And And refreshing the data of the memory cells at specific refresh cycles to improve the retention characteristics of the data stored in the memory cells. 58. The method of claim 57, wherein said refreshing step Reading data stored in the memory cell and storing the data in a register; Writing all row data to the memory cell; And And writing the data stored in the register to the memory cell to maintain the low data stored in the memory cell or to write the high data in the memory cell. 59. The method of claim 57, wherein the refresh period is allotted at the same time to refresh all of the memory cells during the refresh period. 60. The method of claim 59, wherein the refresh cycle is set to (refresh time) / (number of row addresses). The method of claim 57, Continuously performing the refresh operation on the row address during a burst refresh cycle; And And performing the read / write operation during a read / write operation cycle period.

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