KR19990025213A - ML semiconductor device and its manufacturing method - Google Patents
ML semiconductor device and its manufacturing method Download PDFInfo
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- KR19990025213A KR19990025213A KR1019970046760A KR19970046760A KR19990025213A KR 19990025213 A KR19990025213 A KR 19990025213A KR 1019970046760 A KR1019970046760 A KR 1019970046760A KR 19970046760 A KR19970046760 A KR 19970046760A KR 19990025213 A KR19990025213 A KR 19990025213A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Abstract
본 발명은 엠엠엘 반도체소자 및 그 제조방법에 관한 것으로서, 하나의 기판에 디램부와 로직부가 함께 형성되는 엠.엠.엘(merged memory logic : 이하 MML이라 칭함) 소자에서 로직 부분에는 MOS FET의 전류 구동능력을 향상시키기 위하여 게이트전극과 접합 영역 모두에 실리사이드막을 형성하고, 디램부에는 게이트전극상에만 실리사이드막이 형성되도록 하였으므로, 디램부에서의 실리사이드막에 의한 접합 파괴나 누설전류 발생을 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MLM semiconductor device and a method of manufacturing the same. In an M.M.L (merged memory logic: MML) device in which a DRAM part and a logic part are formed together on one substrate, In order to improve the current driving capability, a silicide film is formed on both the gate electrode and the junction region, and a silicide film is formed only on the gate electrode on the DRAM part, thereby preventing the junction breakage and leakage current caused by the silicide film in the DRAM part. Yield and reliability of device operation can be improved.
Description
본 발명은 MML 반도체소자 및 그 제조방법에 관한 것으로서, 특히 로직과 디램이 하나의 칩으로 형성되는 MML 소자에서 로직부에는 게이트전극과 접합 부분에 모두 실리사이드막을 형성하여 전류구동능력을 향상시키고, 디램부에는 게이트전극에만 실리사이드막을 형성하여 누설전류를 감소시킴으로써 접합 누설전류를 방지하여 소자 동작의 신뢰성을 향상시킬 수 있는 MML 반도체소자 및 그 제조방법에 관한 것이다.The present invention relates to an MML semiconductor device and a method of manufacturing the same. In particular, in an MML device in which logic and DRAM are formed as one chip, a silicide layer is formed in both the gate electrode and the junction part in the logic part to improve current driving capability. The present invention relates to an MML semiconductor device and a method of manufacturing the same, in which a silicide layer is formed on only a gate electrode to reduce leakage current, thereby preventing junction leakage current, thereby improving reliability of device operation.
반도체소자가 고집적화되어 감에 따라 모스 전계효과 트랜지스터(Metal Oxide Semiconductor Field Effect Transistor ; 이하 MOS FET라 칭함)의 게이트 전극도 폭이 줄어들고 있으나, 게이트전극의 폭이 N배 줄어들면 게이트전극의 전기저항이 N배 증가되어 반도체소자의 동작 속도를 떨어뜨리는 문제점이 있다. 따라서 게이트전극의 저항을 감소시키기 위하여 가장 안정적인 MOSFET 특성을 나타내는 폴리실리콘층/산화막 계면의 특성을 이용하여 폴리실리콘층과 실리사이드의 적층 구조의 폴리사이드가 저 저항 게이트로서 사용되기도 한다.As semiconductor devices become more integrated, the gate electrode of a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET) is decreasing in width, but when the width of the gate electrode is reduced by N times, the electrical resistance of the gate electrode is decreased. There is a problem that the N times increased to decrease the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, a polysilicon having a laminated structure of polysilicon layer and silicide may be used as a low resistance gate by using the characteristics of the polysilicon layer / oxide layer interface having the most stable MOSFET characteristics.
일반적으로 p 또는 n형 반도체기판에 n 또는 p형 불순물로 형성되는 pn 접합은 불순물을 반도체기판에 이온주입한 후, 열처리로 활성화시켜 확산영역을 형성한다. 따라서 채널의 폭이 감소된 반도체소자에서는 확산영역으로부터의 측면 확산에 의한 숏채널 효과(short channel effect)를 방지하기 위하여 접합깊이를 얕게 형성하여야 하며, 드레인으로의 전계 집중에 의한 접합 파괴를 방지하게 위하여 소오스/드레인 영역을 저농도 불순물 영역을 갖는 LDD 구조로 형성하는 등의 방법이 있다.In general, a pn junction formed of a p or n type semiconductor substrate with n or p type impurities is ion implanted into a semiconductor substrate and then activated by heat treatment to form a diffusion region. Therefore, in a semiconductor device having a reduced channel width, the junction depth should be shallow to prevent short channel effects due to side diffusion from the diffusion region, and to prevent junction breakage due to electric field concentration to the drain. For this purpose, there are methods such as forming a source / drain region into an LDD structure having a low concentration impurity region.
종래 MML 소자에서는 게이트전극의 저항을 감소시키고, 접합의 콘택 저항을 감소시키기 위하여 게이트전극과 접합상부에 실리사이드막을 형성하는데, 상기 MML 소자의 디램의 접합 부분에 형성되는 실리사이드막에 의해 접합 부분에서의 누설전류가 증가되고, 스파이크 현상에 의해 접합파괴 등이 발생하여 공정수율 및 소자 동작의 신뢰성이 떨어지는 등의 문제점이 있다.In the conventional MML device, a silicide film is formed on the junction of the gate electrode and the junction to reduce the resistance of the gate electrode and to reduce the contact resistance of the junction. There is a problem that leakage current increases, splice phenomenon occurs, and so on, resulting in poor process yield and reliability of device operation.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 MML 소자에서 디램부에는 게이트전극상에만 실리사이드막을 형성하여 디램부의 접합에서의 실리사이드막에 의한 누설전류 및 접합파괴를 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 MML 반도체소자 및 그 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to form a silicide film only on the gate electrode in the DRAM unit in the MML device to prevent leakage current and junction breakdown by the silicide film at the junction of the DRAM unit process The present invention provides an MML semiconductor device and a method of manufacturing the same, which can improve yield and reliability of device operation.
도 1a 내지 도 1f는 본 발명에 따른 반도체소자의 제조 공정도.1A to 1F are manufacturing process diagrams of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 반도체기판3 : 소자분리 산화막1: semiconductor substrate 3: device isolation oxide film
4 : 게이트산화막5 : 도전층4 gate oxide film 5: conductive layer
5A : 디램부 게이트전극5B : 로직부 게이트전극5A: DRAM gate electrode 5B: logic gate electrode
7 : 로직부 접합영역9 : 절연막 스페이서7 logic region junction region 9 insulating film spacer
10 : 제1감광막 패턴11 : 전이금속층10: first photosensitive film pattern 11: transition metal layer
13 : 실리사이드막15 : 디램부 접합영역13: silicide film 15: DRAM junction area
20 : 제2감광막 패턴20: second photosensitive film pattern
상기와 같은 목적을 달성하기 위한 본 발명에 따른 MML 반도체소자의 특징은,Features of the MML semiconductor device according to the present invention for achieving the above object,
디램부와 로직부가 하나의 기판에 형성되는 MML 반도체소자에 있어서,In an MML semiconductor device in which a DRAM unit and a logic unit are formed on one substrate,
상기 로직부의 게이트전극과 접합 부분상에 실리사이드막을 구비하고,A silicide layer on the gate electrode and the junction portion of the logic unit;
상기 디램부의 게이트전극상에 실리사이드막을 구비함에 있다.The silicide layer is provided on the gate electrode of the DRAM unit.
또한 본 발명에 따른 MML 반도체소자 제조방법의 특징은,In addition, the features of the MML semiconductor device manufacturing method according to the present invention,
디램부와 로직부가 하나의 기판에 형성되는 MML 반도체소자의 제조방법에 있어서,In the manufacturing method of the MML semiconductor device in which the DRAM unit and the logic unit is formed on one substrate,
반도체기판상에 디램부와 로직부를 분리하는 소자분리 산화막을 형성하는 공정과,Forming a device isolation oxide film separating the DRAM portion and the logic portion on the semiconductor substrate;
상기 반도체기판상에 게이트산화막을 형성하는 공정과,Forming a gate oxide film on the semiconductor substrate;
상기 구조의 전표면에 실리콘층을 형성하는 공정과,Forming a silicon layer on the entire surface of the structure;
상기 디램부의 상측과 로직부의 게이트전극으로 예정되어있는 부분상에 제1감광막 패턴을 형성하는 공정과,Forming a first photoresist pattern on an upper side of the DRAM unit and a portion of the logic unit as a gate electrode;
상기 제1감광막 패턴에 의해 노출되어있는 실리콘층을 제거하여 디램부의 전면을 덮고, 로직부에서는 게이트전극이 되는 실리콘층 패턴을 형성하는 공정과,Removing the silicon layer exposed by the first photoresist pattern to cover the entire surface of the DRAM unit, and forming a silicon layer pattern serving as a gate electrode in the logic unit;
상기 로직부의 반도체기판에 접합영역을 형성하고 제1감광막 패턴을 제거하는 공정과,Forming a junction region on the semiconductor substrate of the logic unit and removing the first photoresist pattern;
상기 실리콘층 패턴의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the silicon layer pattern;
상기 구조의 전표면에 전이금속층을 형성하는 공정과,Forming a transition metal layer on the entire surface of the structure;
상기 전이금속층을 열처리하여 하부의 실리콘과 반응시켜 로직부의 게이트전극 상부와 접합 상부 및 디램부를 덮은 실리콘층 패턴상에 실리사이드막을 형성하고 미반응 전이금속층을 제거하는 공정과,Heat-treating the transition metal layer to react with silicon at the bottom to form a silicide film on a silicon layer pattern covering the gate electrode, the junction upper part, and the DRAM part of the logic part, and removing the unreacted transition metal layer;
상기 로직부의 상부와 디램부의 게이트전극으로 예정되어있는 부분상에 제2감광막 패턴을 형성하는 공정과,Forming a second photoresist layer pattern on an upper portion of the logic unit and a portion of the DRAM unit as a gate electrode;
상기 제2감광막 패턴에 의해 노출되어있는 실리사이드막과 실리콘층을 순차적으로 식각하여 게이트전극을 형성하는 공정과,Sequentially etching the silicide layer and the silicon layer exposed by the second photoresist layer pattern to form a gate electrode;
상기 디램부의 반도체기판에 접합영역을 형성하는 공정을 구비함에 있다.And forming a junction region on the semiconductor substrate of the DRAM unit.
이하, 본 발명에 따른 MML 반도체소자 및 그 제조방법에 관하여 참조도면을 참조하여 상세히 설명한다.Hereinafter, an MML semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.
도 1f는 본 발명에 따른 MML 반도체소자의 단면도로서, 하나의 반도체기판(1)에 로직부(A)와 디램부(B)가 소자분리 산화막(3)에 의해 분리되어있고, 로직부에는 게이트전극(5A)과 접합영역(7)의 상부에 실리사이드막(13)이 형성되어있고, 디램부에는 게이트전극(5B)의 상부에만 실리사이드막(13)이 형성되어있다.FIG. 1F is a cross-sectional view of an MML semiconductor device according to the present invention, in which a logic portion A and a DRAM portion B are separated by an element isolation oxide film 3 on one semiconductor substrate 1, and a gate is formed on a logic portion. The silicide film 13 is formed on the electrode 5A and the junction region 7, and the silicide film 13 is formed only on the gate electrode 5B in the DRAM portion.
도 1a 내지 도 1f는 본 발명에 따른 반도체소자의 제조공정도이다.1A to 1F are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 반도체기판(1)에서 소자분리 영역으로 예정되어있는 부분상에 소자분리산화막(3)과 게이트산화막(4)을 형성하고, 상기 구조의 전표면에 게이트전극이 되는 도전층(5)을 형성하고, 디램부(A)를 가리고 로직부(B)의 게이트전극 패터닝 마스크인 제1감광막 패턴(10)을 형성한다(도 1a 참조).First, an element isolation oxide film 3 and a gate oxide film 4 are formed on a portion of the semiconductor substrate 1 that is intended as an element isolation region, and a conductive layer 5 serving as a gate electrode is formed on the entire surface of the structure. The first photoresist layer pattern 10, which is a gate electrode patterning mask of the logic unit B, is formed by covering the DRAM unit A (see FIG. 1A).
그다음 상기 제1감광막 패턴(10)에 의해 노출되어있는 도전층(5)을 제거하여 다결정이나 비정질 실리콘 등의 도전층(5) 패턴으로된 로직부(B)의 게이트전극(5B)을 형성하고, 상기 제1감광막 패턴(10)을 제거한 후, 상기 노출되어있는 로직부(B) 반도체기판(1)에 접합영역(7B)을 형성하고, 상기 도전층(5) 패턴에 측벽에 고온이나 중온(High temperature oxide or Middle temperature oxide) 또는 테오스(Tetra Echyl Ortho Silicate ; 이하 TEOS라 칭함)계 산화막이나 질화막으로된 스페이서(9)를 형성한다. 여기서 상기의 절연 스페이서(9) 이외에 후속 실리사이드 공정후에 형성하는 절연 스페이서는 저온에서 증착이 가능한 저압이나 플러즈마 여기 TEOS로 형성하여야 한다(도 1b 참조).Next, the conductive layer 5 exposed by the first photoresist pattern 10 is removed to form the gate electrode 5B of the logic portion B formed of the conductive layer 5 pattern such as polycrystalline or amorphous silicon. After removing the first photoresist layer pattern 10, a junction region 7B is formed in the exposed logic portion B semiconductor substrate 1, and high or medium temperatures are formed on the sidewalls of the conductive layer 5 pattern. A spacer 9 made of (High temperature oxide or Middle temperature oxide) or Teos (Tetra Echyl Ortho Silicate; TEOS) -based oxide film or nitride film is formed. Here, in addition to the insulating spacer 9, the insulating spacer formed after the subsequent silicide process should be formed of low pressure or plasma excited TEOS that can be deposited at low temperature (see FIG. 1B).
그후, 상기 구조의 전표면에 실리사이드화되는 재질, 예를들어 W, Ni, Co, Ti, Ta, Cr 등의 전이금속층(11)을 형성하고(도 1c 참조), 열처리하여 반도체기판(1) 이나 도전층(5) 패턴상에 실리사이드막(13)을 형성한 후, 산화막 상의 실리사이드화 하지 않은 전이금속층(11)을 전이금속과 실리사이드막간의 식각선택비차를 이용하여 습식식각 방법으로 제거하고, 상기 로직부(B)는 모두 보호하고 디램부(A)는 게이트 전극이 되는 부분만을 보호하는 제2감광막 패턴(20)을 형성한다(도 1d 참조).Thereafter, a silicided material is formed on the entire surface of the structure, for example, a transition metal layer 11 such as W, Ni, Co, Ti, Ta, Cr, etc. (see FIG. After the silicide film 13 is formed on the conductive layer 5 pattern, the non-silicided transition metal layer 11 on the oxide film is removed by a wet etching method using an etching selectivity difference between the transition metal and the silicide film. The logic portion B protects all of the DRAM portion A, and the second photoresist pattern 20 is formed to protect only the portion of the gate electrode (see FIG. 1D).
그 다음 상기 제2감광막 패턴(20)에 의해 노출되어있는 실리사이드막(13)과 도전층(5)을 제거하여 디램부(A) 게이트전극(5A)을 형성한 후(도 1e 참조), 상기 제2감광막 패턴(20)을 제거하고, 상기 디램부(A)의 반도체기판(1)에 디램부 접합영역(15)을 형성한다(도 1f 참조).Thereafter, the silicide layer 13 and the conductive layer 5 exposed by the second photoresist layer pattern 20 are removed to form the DRAM portion A gate electrode 5A (see FIG. 1E). The second photoresist layer pattern 20 is removed, and a DRAM junction region 15 is formed in the semiconductor substrate 1 of the DRAM unit A (see FIG. 1F).
이상에서 설명한 바와 같이, 본 발명에 따른 MML 반도체소자 및 그 제조방법은 하나의 기판에 디램부와 로직부가 함께 형성되는 MML 소자에서 로직 부분에는 MOS FET의 전류 구동능력을 향상시키기 위하여 게이트전극과 접합 영역 모두에 실리사이드막을 형성하고, 디램부에는 게이트전극상에만 실리사이드막이 형성되도록하였으므로, 디램부에서의 실리사이드막에 의한 접합 파괴나 누설전류 발생을 방지하여 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the MML semiconductor device and a method of manufacturing the same according to the present invention are bonded to the gate electrode in order to improve the current driving capability of the MOS FET in the logic part of the MML device in which the DRAM part and the logic part are formed together on one substrate. Since the silicide film is formed in all regions and the silicide film is formed only on the gate electrode in the DRAM part, it is possible to improve the process yield and the reliability of device operation by preventing the breakage of the junction or the generation of leakage current by the silicide film in the DRAM part. There is an advantage.
Claims (6)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100317532B1 (en) * | 1999-04-22 | 2001-12-22 | 윤종용 | Semiconductor device and method for fabricating the same |
| KR100321175B1 (en) * | 1999-12-29 | 2002-03-18 | 박종섭 | Method For Forming The Gate Electrode Of MML Semiconductor Device |
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| JPS61125043A (en) * | 1984-11-22 | 1986-06-12 | Hitachi Ltd | Semiconductor integrated circuit device |
| JP2752892B2 (en) * | 1993-09-20 | 1998-05-18 | 日本電気株式会社 | Semiconductor integrated circuit device and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100317532B1 (en) * | 1999-04-22 | 2001-12-22 | 윤종용 | Semiconductor device and method for fabricating the same |
| KR100321175B1 (en) * | 1999-12-29 | 2002-03-18 | 박종섭 | Method For Forming The Gate Electrode Of MML Semiconductor Device |
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