JPS61125043A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a silicide film from peeling and to reduce a resistance value of a conductive layer by providing the silicide film of a large quantity of silicon between a polycrystalline silicon film and a silicide film in a semiconductor integrated circuit device having the conductive layer provided with the silicide film on the upper part of the polycrystalline silicon film. CONSTITUTION:In the case of a memory cell of DRAM, a conductive layer 7A composes a gate electrode of MISFET to a switching element, and a conductive layer 7B is unified with the plural said gates arranged in a predetermined direction and constitutes a word line WL. The conductive layers 7A and 7B are respectively composed of a polycrystalline silicon film 7a, a silicide film 7b provided on the 7a, and a silicide film 7c of a large quantity of silicon provided in those inclusion portions. As a quantity of silicon of the silicide film 7c of a large quantity of silicon is more than that of the silicide film 7b, a stress through velumetric shrinkage after a heat treatment process is relieved, and then, as an adhesive strength between 7c and both the polycrystalline silicon film 7a and the silicide film 7b is strong, peeling between them is prevented.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to a semiconductor integrated circuit device having a conductive layer formed by providing a silicide film on a polycrystalline silicon film. It is about effective techniques.

[Background Art] There is a tendency for semiconductor integrated circuit devices (hereinafter referred to as DRAMs) equipped with dynamic random access memories to be faster by shortening the time for reading and writing information.

In DRAMs that employ the halted bit line method, reducing the resistance value of word lines formed of polycrystalline silicon films is one of the important technical issues. Therefore, the word line is constructed using a polycide film in which a molybdenum silicide film having a smaller resistance value than the polycrystalline silicon film is provided on top of the polycrystalline silicon film. A polycrystalline silicon film can stably maintain the threshold voltage when a gate electrode of a MISFET is formed from a polycide film.

However, the results of studies in such technology.

The inventors of the present invention have discovered that the stress caused by the volumetric shrinkage of the molybdenum silicide film after the heat treatment process causes the molybdenum silicide film to peel off from the polycrystalline silicon film, resulting in a defective semiconductor integrated circuit device.

In addition, the inventor has found that increasing the amount of silicon in the molybdenum silicide film reduces the stress and makes it difficult to cause peeling, but the resistance value of the polycide film increases, making it impossible to increase the operating time. I found a problem.

Note that one of the documents describing silicide films and polycide films includes, for example, IEEE ELECTORN DE
VICE LE DING TER5, VOL, EDL 3.
NO, 2FEBRUARY 1982 rRefr
acLory Mo5i2and MoSi2/Po1
ysilicon Bulk CMO5C1rcuij
There are sJ p37-p39.

[Object of the Invention] An object of the present invention is to provide a technique capable of suppressing peeling of a silicide film in a semiconductor integrated circuit device having a conductive layer formed by providing a silicide film on top of a polycrystalline silicon film. be.

Another object of the present invention is to suppress peeling of the silicide film and reduce the resistance value of the conductive layer in a semiconductor integrated circuit device having a conductive layer formed by providing a silicide film on top of a polycrystalline silicon film. Our goal is to provide the technology that is possible.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.

That is, in a semiconductor integrated circuit device having a conductive layer formed by providing a silicide film on top of a polycrystalline silicon film, a silicide film containing many silicon groups and having characteristics intermediate between the two is placed between the polycrystalline silicon film and the silicide film. establish.

As a result, stress on the silicide film can be alleviated, the adhesive force between the polycrystalline silicon film and the silicide film can be increased, and peeling of them can be suppressed, thereby making it possible to prevent defects in the semiconductor integrated circuit device. Further, since the resistance value of the silicide film can be reduced independently of the suppression of peeling, the operating time of the semiconductor integrated circuit device can be increased.

Hereinafter, the structure of the present invention will be explained along with an embodiment in which the present invention is applied to a DRAM employing the halt pit line method.

Embodiment FIG. 1 shows a DRAM for explaining an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a main part of a memory cell of FIG.

In FIG. 1, parts having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted.

In FIG. 1, 1 is a p-type semiconductor substrate made of single crystal silicon, and 2 is a field insulating film for electrically isolating memory cells.

3 is an insulating film, and 4 is a conductive plate, which constitutes an information storage capacitive element of a memory cell. The conductive plate 4 is composed of the first conductive layer in the manufacturing process, and is formed of, for example, a polycrystalline silicon film formed by CVD technology.

An information storage capacitive element constituting a memory cell is mainly composed of a semiconductor substrate 1, an insulating film 3, and a conductive plate 4.

5 is an insulating film that separates conductive layers, 6 is a MISFE
This is an insulating film that constitutes the gate insulating film of T.

7A and 7B are conductive NN (polycide films).

It is provided on a predetermined upper part of the insulating film 6 or on a predetermined upper part of the insulating film 5. The conductive layer 7A serves as a switch element.
This is for configuring the gate ff1tl of the S FET. The conductive layer 7B is integrated with the plurality of gate electrodes arranged in a predetermined direction, is provided to extend in a predetermined direction, and is for forming a word line WL.

The conductive layers 7A and 7B are composed of a polycrystalline silicon film 7a, a silicide film 1FJ7b provided on top of the polycrystalline silicon film 7a, a silicide film 7c with a large amount of silicon provided in an intervening portion thereof, and the like.

Polycrystalline silicon 1 and 7a are the threshold lf of MISFET.
Excellent in stabilizing electrical characteristics such as f1 voltage.

The polycrystalline silicon film 7a is formed by, for example, CVD technology, with a film thickness of about 2000 to 3000 angstroms (hereinafter referred to as A) and a resistance value of 20 to 30 angstroms.
Ω/mouth].

The silicide film 7b is particularly suitable for the conductive layer 7B (word line WL
) can be reduced, and the read operation time and write operation time of the switch element can be shortened. The silicide film 7b is made of, for example, molybdenum silicide (MoSi) formed by sputtering technology and heat treatment technology.
□), tantalum silicide (TaSi2), titanium silicide (TiSi2).

It is formed of tungsten silicide (WSi2) or the like.

The silicide film 7b has a thickness of, for example, 15
00~2500[A1 degree, its resistance value is 2~4[Ω/
[mouth] is formed. The silicide film 7b is.

Compared to high melting point metal films (Mo, T, a, Ti, W), the film quality stability against manufacturing processes and stability against oxidation is better, and the etching rate difference with the polycrystalline silicon film 7a is small. It has the characteristic of being easy to process.

The silicide film 7C containing a large amount of silicon has intermediate characteristics between the polycrystalline silicon film 7d and the silicide film 7b. In other words, since the amount of silicon is larger than that of the silicide film 7b, the stress caused by volume shrinkage after the heat treatment process (activation of the silicide film) is alleviated, and the adhesive strength to both the polycrystalline silicon film 7a and the silicide film 7b is improved. is strong.

Therefore, peeling between polycrystalline silicon film 7a and silicide film 7b can be suppressed. and.

Since the resistance value of the silicide film 7b can be controlled independently of the suppression of peeling, it can be sufficiently reduced. The silicide film 7C is formed, for example, by sputtering technology, with a thickness of about 500 to 1000 [A] and a resistance value of about 8 to 12 [Ω/gate]. Conductive layer 7A,'
7B is formed as the second conductive layer in the I2 manufacturing process.

8 is an n+ type semiconductor region, which has conductivity y! It is provided on both sides of B7A. This semiconductor region 8 is.

It is for configuring the source region or drain region of the MI S FET.

Mr S FET, which serves as a switching element of a memory cell, is mainly manufactured using a semiconductor substrate 1. It is composed of an insulating film 6, a conductive layer 7A, and a pair of semiconductor regions 8.

9 is an insulating film that electrically isolates conductive layers, and 10 is a connection hole.

Reference numeral 11 denotes a conductive layer, which is electrically connected to a predetermined semiconductor region 8 through a connection hole 1O, and is provided so as to extend above the insulating film 9 in a direction substantially perpendicular to the direction in which the conductive layer 7B extends. . This conductive PrJ11 is for configuring the data line DL, for example.

An aluminum film formed by sputtering technology is used. This conductive layer 11 is formed as the third conductive layer in the 812 manufacturing process.

[Effects] As explained above, according to the new technology disclosed in the two applications, the following effects can be obtained.

(1) ``In a semiconductor integrated circuit device having a conductive layer formed by providing a silicide film on top of a polycrystalline silicon film, between the polycrystalline silicon film and the silicide film.

By providing a silicide film with a large amount of silicon that has intermediate characteristics between the two, it is possible to alleviate the stress generated in the silicide film and increase the adhesive strength between the two, thereby suppressing peeling of the silicide film. .

(2) According to (1) above, defects in semiconductor integrated circuit devices can be prevented.

(3) According to (1) above, the resistance value of the silicide film can be reduced independently of the suppression of peeling, so the resistance value of the conductive layer can be reduced.

(4) According to (3) above, the operating time of the semiconductor integrated circuit device can be increased.

(5) With (2) and (1) above, it is possible to prevent defects in the semiconductor integrated circuit device and to increase the operating time.

Although the invention made by the present inventor has been specifically explained above based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof. Of course, it can be modified.

For example, in the embodiment described above, the present invention was applied to a DRAM that adopts a hole-put pit line method, but it is also applicable to a 6BMTS, SRAM that uses a polycide film.
, EFROM, ROM, etc., may be applied to semiconductor integrated circuit devices.

[Brief explanation of the drawing]

FIG. 1 shows a DRAM for explaining one embodiment of the present invention.
FIG. 2 is a cross-sectional view of a main part of a memory cell of FIG. In the figure, 1... semiconductor substrate, 2... field insulating film. 3.5.6.9... Insulating film, 4... Conductive plate,
7A, 7B, 11... Conductive layer, 7a... Polycrystalline silicon film, 7b... Silicide film, 7c... Silicide film (with a large amount of silicon), 8... Semiconductor region, 10
...It is a connection hole. Figure 1 t(p'''') Procedural amendment (method) Indication of the case Patent application No. 245988 of 1982 Name of the invention Semiconductor integrated circuit device Amendment person Mochi and 1 Patent applicant name Name rs+o) Japan Co., Ltd. Standing manufacturing fee
Person 1, page 3 of the specification, lines 9 to 122. rIEEE ELECTORN DEVICE LE
TTER8゜VOL, EDL 3, 42 FEBR
UARY l 982 rl'Lef-ractor
y Mo5il and MoSi2/Polysil
iconBulk CMO8C1rcuits J p
37-p39 j It says, ``IEE Electron Device Letters, EDL Volume 3,
No. 2, February 1982 "Bulk SEMOS circuit using high melting point molybdenum silicide and molybdenum silicide/polysilicon p37-p39 (IEEE EL
ECTORNDEVICE LETTER8, VOL,
EDL 3,42FEBRUARY 1982 rRe
factory MoS i2 and MoSil/
Polysilicon Bulk CMO8C1rc
uitsJp37-p39) Correct to J.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having a conductive layer formed by providing a silicide film on top of a polycrystalline silicon film, wherein a portion between the polycrystalline silicon film and the silicide film has a conductive layer formed from the silicide film. A semiconductor integrated circuit device characterized in that it is provided with a silicide film containing a large amount of silicon. 2. Claim 1, wherein the silicide film is composed of molybdenum silicide, tantalum silicide, titanium silicide, tungsten silicide, etc., which are compounds of polycrystalline silicon and a high-melting point metal.
2. The semiconductor integrated circuit device described in 2.