KR19990024636A - Complementary Morse Type Addition Circuit - Google Patents

Abstract

The CMOS full-addition circuit according to the present invention outputs the sum of the logic '1' when the logic bits '1' are odd during the carry-out and the data bits to be added, and the logic '0' when the logic '1' is even. A first logic circuit for outputting the sum of; The carry-out of logic '1' is output when the data bits to be added and the logic '1' of the carry-out are at least two or more, and the logic when fewer logic '1' is inputted. And a second logic circuit outputting the carry-out of '0'.

Description

Complementary Morse Type Addition Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full adder, and more particularly, to a CMOS full adder that can operate at a low power and is highly integrated.

To date, many kinds of full adders have been designed. By reducing the number of transistors constituting the full adder, the area, which is one of the important factors for measuring the performance of a library cell, can be reduced and power consumption can be reduced. The full adder currently used in the ASIC library typically includes more than 24-30 MOS transistors (Metal Oxide Semiconductor transistors).

It is therefore an object of the present invention to provide a CMOS full add circuit that occupies a small area and has low power consumption.

1 is a circuit diagram showing a full adder according to a preferred embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

1: first input terminal 2: second input terminal

3: third input terminal 4, 5: output terminal

10: first logic circuit 12, 14: inverter

20: second logic circuit

According to one aspect of the present invention for achieving the object described above, the first and second data bits to be added and the carry of the previous stage are accepted to output the sum of the data bits and the carry-out. A full adder circuit including a plurality of full adders for outputting a carry-out when a carry occurs in a summation, the full adder circuit comprising: logic '1' between the data bits to be added and the carry-out. First logic means for outputting the sum of logic '1' when there is an odd number and outputting the sum of logic '0' when logic '1' is even; The carry-out of logic '1' is output when the data bits to be added and the logic '1' of the carry-out are at least two or more, and the logic when fewer logic '1' is inputted. And second logic means for outputting the carry-out of '0'.

In this embodiment, the first logic circuit is configured as an EX-OR logic circuit.

In this embodiment, the first logic means comprises: a first power supply terminal for receiving a ground potential; A first output terminal for outputting the sum; A first MOS transistor having a gate, a source, and a drain, wherein the first data bit is applied to the gate and the second data bit is applied to the source; A second transistor having a gate and a source, the second data bit being applied to the gate and the first data bit being applied to the source and having a drain connected in common with the drain of the first transistor; A first inverter having an input terminal and an output terminal, the input terminal being connected to a common drain connection point of the first and second transistors, and inverting a phase of the connection point; An input terminal and an output terminal, connected between an input terminal and an output terminal of the first inverter, and inverting a phase of the carry-out by connecting the first output terminal to one of the input terminal and the output terminal in response to the carry-out; A second inverter for making; Third and fourth transistors each having a gate and a drain-source channel, the channels connected in series between the common connection point and the first power supply terminal, and first and second data bits applied to the respective gates. It is characterized by including.

In this embodiment, the first logic means is configured to control and control terminals respectively connected to the input terminal and the output terminal of the first inverter so as to maintain the stable state when the common connection point has a logically unstable state. A transfer gate having a current path formed between an input terminal and an output terminal of the second inverter; And a fifth transistor having a drain-source channel formed between the common connection point and the first power supply terminal and a gate connected to an output terminal of the first inverter.

In this embodiment, the first and second transistors are composed of P-channel MOS transistors.

In this embodiment, the third, fourth and fifth transistors are composed of N-channel MOS transistors.

By such a circuit, a chip area that can improve the performance of an ASIC library cell can be reduced.

Hereinafter, reference will be made in detail with reference to FIG. 1.

1, there is shown a circuit diagram showing a full addition circuit according to a preferred embodiment of the present invention. The full sum circuit takes the sum of the two data bits (A) and (B) and the carry (C) resulting from the addition of the previous stage, and the carry-out (C _OUT ) from the stage where the current calculation is performed. One of the logic cells to output. The truth table of the full addition circuit according to the present invention is represented by Table 1 below.

TABLE 1

A B C C _OUT SUM 0 0 0 0 0 One 0 0 0 One 0 One 0 0 One One One 0 One 0 0 0 One 0 One One 0 One One 0 0 One One One 0 One One One One One

As can be seen from Table 1, the sum SUM is logical when the logical number '1' is odd among the input signals, i.e., the data bits (A) and (B) to be added and the carry (C) provided from the previous stage. Outputs '1' and outputs logic '0' when there are even numbers. For convenience, a circuit for obtaining a sum SUM is called a first logic circuit 10. The carry-out C _OUT is a logic when the input signal, i.e., the data bits (A) and (B) to be added and the carry (C) provided from the previous stage are logically '1' at least two. It outputs '1' and outputs logic '0' when less than two. For convenience, the circuit for obtaining the carry-out C _OUT is called a second logic circuit 20.

Detailed circuitry for the first and second logic circuits 10 and 20 according to a preferred embodiment of the present invention is shown in FIG.

Referring to FIG. 1, the first logic circuit 10 performs the function of Exclusive-OR as described above, and includes five PMOS transistors M1, M2, M6, M8, and ( M10) and six NMOS transistors M3, M4, M5, M7, M9, and M11.

PMOS transistors (M1) and (M2) gated to first and second input terminals (1) and (2), respectively, for receiving first and second data bits (A) and (B) Has current paths respectively formed between the first input terminal 1 and the common connection point N1 and between the second input terminal 2 and the common connection point N1. NMOS transistors M3 and M4 having current paths sequentially formed in series between the common connection point N1 and ground potential Vss are respectively connected to the first and second input terminals 1 and 2, respectively. With gates connected.

The PMOS transistor M6 and the NMOS transistor M7 are provided as one inverter 12, the gates of which are connected to the common connection point N1 and the power supply voltage Vcc and the ground potential Vss. In between, its current paths are formed sequentially in series. Where the current paths of the transistors M6 and M7 are commonly connected, i.e., the NMOS transistor M5 with its gate connected to the output terminal N2 of the inverter, between the common connection point N1 and the ground potential Vss. It has a current path formed in it and performs a function for correcting when the input data bits (A) and (B) have an unsafe value of logic '0'.

PMOS transistor M10 and NMOS having current paths sequentially formed in series between the input terminals of transistors M6 and M7 provided as inverter 12, i.e., common connection point N1 and its output terminal N2. The transistor M11 has gates commonly connected to the third input terminal 3 for receiving the carry C. In addition, the transistors M10 and M11 are also provided as the inverter 14 and its output terminal is connected to the output terminal 4 for outputting the sum SUM.

Then, the PMOS transistor M8 and the NMOS transistor M9 are provided as transmission gates, the gates of which are connected to the common connection point N1 and the output terminal N2, respectively, and the current path is the transistors M10. And an input terminal and an output terminal of the inverter composed of M11.

As described above, the second logic circuit 20 has a logical '1' of two of the input signals, i.e., the data bits (A) and (B) to be added and the carry (C) provided from the previous stage. when more than one logic "1" carry-out outputs (C _oUT) - the output out (C _oUT), and the second carry-less when the logical "0" than the dog. The second logic circuit 20 according to the present invention comprises six PMOS transistors M12, M13, M16, M18, M19 and M22 and six NMOS transistors M14, It consists of (M15), (M17), (M20), (M21), and (M23).

The current paths of the transistors M12-M15 are sequentially formed in series between the power supply voltage Vcc and the ground potential Vss. Gates of the transistors M12 and M15 are connected to the third input terminal 3, and gates of the transistors M13 and M14 are connected to the first input terminal 1. The PMOS transistor M16 having a gate connected to the second input terminal 2 has a connection point N3 and a transistor M12 in which current paths of the transistors M13 and M14 are commonly connected to the second input terminal 2. Has a current path formed between the drains. The NMOS transistor M17 having a gate connected to the second input terminal 2 has a current path formed between the connection point N3 and the drain of the transistor M15.

The current paths of the transistors M18-M21 are sequentially formed in series between the power supply voltage Vcc and the ground potential Vss. Gates of the transistors M18 and M21 are connected to the first input terminal 1, and gates of the transistors M19 and M20 are connected to the second input terminal 2. The current paths of the PMOS transistor M22 and the NMOS transistor M23 are sequentially formed in series between the power supply voltage Vcc and the ground potential Vss, and their gates are commonly connected to the connection point N3. . In addition, its current paths are connected to an output terminal 5 for outputting a carry C _OUT . Since the CMOS full-addition circuit according to the present invention is constructed using a total of 23 MOS transistors, it consumes less power than the conventional one, and the area occupied by it is also small.

As described above, it is possible to provide a full integration circuit that is highly integrated and operable at low power.

Claims (6)

A plurality of outputs for receiving the first and second data bits to be added and a carry of the previous stage and outputting a sum of the data bits and the carry-out, and outputting a carry-out when a carry occurs in the sum; In a full adder circuit comprising two full adders: Outputting the sum of logic '1' when the number of data bits to be added and logic '1' during the carry-out are odd, and outputting the sum of logic '0' when logic '1' is even First logic means; The carry-out of logic '1' is output when the data bits to be added and the logic '1' of the carry-out are at least two or more, and the logic when fewer logic '1' is inputted. And second logic means for outputting the carry-out of '0'. The method of claim 1, And said first logic circuit comprises an EX-OR logic circuit. The method of claim 2, The first logic means includes a first power supply terminal for receiving a ground potential; A first output terminal for outputting the sum; A first MOS transistor having a gate, a source, and a drain, wherein the first data bit is applied to the gate and the second data bit is applied to the source; A second transistor having a gate and a source, the second data bit being applied to the gate and the first data bit being applied to the source and having a drain connected in common with the drain of the first transistor; A first inverter having an input terminal and an output terminal, the input terminal being connected to a common drain connection point of the first and second transistors, and inverting a phase of the connection point; An input terminal and an output terminal, connected between an input terminal and an output terminal of the first inverter, and inverting a phase of the carry-out by connecting the first output terminal to one of the input terminal and the output terminal in response to the carry-out; A second inverter for making; Third and fourth transistors each having a gate and a drain-source channel, the channels connected in series between the common connection point and the first power supply terminal, and first and second data bits applied to the respective gates. Full add circuit comprising a. The method of claim 3, wherein The first logic means includes control terminals connected to the input terminal and the output terminal of the first inverter and the input terminal of the second inverter, respectively, to maintain the stable state when the common connection point is logically unstable. A transfer gate having a current path formed between the output ends; And a fifth transistor having a drain-source channel formed between said common connection point and said first power supply terminal and a gate connected to an output terminal of said first inverter. The method of claim 3, wherein Wherein said first and second transistors are comprised of P-channel MOS transistors. The method of claim 4, wherein And said third, fourth and fifth transistors are composed of N-channel MOS transistors.