JPH0736667A - Full adder circuit - Google Patents

Abstract

PURPOSE:To make a full adder circuit high in speed and low in power consumption without reducing the number of element for the logic generation of the circuit block for outputting an SUM signal. CONSTITUTION:In a circuit block 30 for outputting an SUM signal, the number of element for the logic generation is made 8 transistors, and path gate logic is generated by using only NMOS 1 to 8 which are smaller than a PMOS in transmission delay time. Further, by using a CMOS inverter 22 for an output stage, the current driving of the sum signal is performed. A circuit block 31 for outputting a carry signal is made to have complemently path gate logic constitutions 9 to 18 using both of the PMOS and the NMOS by taking the balance of the current driving force with the circuit block 30 for outputting the SUM signal into comsideration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit of a full adder used in an adder, a multiplier, etc., and more particularly to a circuit of a full adder required to have high speed and low power consumption.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a circuit of a conventional full adder configured by using transfer gates. In FIG. 2, the full adder is composed of a first block 130 and a second block 131. The first block 130 is
N-channel MOS transistor (hereinafter referred to as NMOS)
102, 104, 106, 108 and P channel MO
S transistors (hereinafter referred to as PMOS) 101, 10
3, 105, 107 and a CMOS inverter 122. Reference numeral 140 denotes a node to which the source of the PMOS 101 and the source of the NMOS 102 are connected.
41 denotes a drain of the PMOS 101, a drain of the NMOS 102, a drain of the PMOS 103, and an NMOS 104.
Drain, PMOS 105 source, NMOS 106
Source, gate of PMOS 107 and NMOS 10
8 is the node to which the gate is connected. The second block 131 includes NMOSs 114 to 118 and PMOS1.
09 to 113 and a CMOS inverter 123.

In the first block 130, the input signal A is input to the gate of the PMOS 101 and at the same time,
It is input to the source of the PMOS 103. At this time, the input signal A controls the switching of the ON or OFF state of the PMOS 101. An inverted input signal A of A obtained by inverting the input signal A through the CMOS inverter 119 is input to the gate of the NMOS 102 and simultaneously to the drain of the NMOS 104. At this time, the inverted input signal A of A is N
It controls the switching of the on or off state of the MOS 102. Like the input signal A, the input signal C is input to the gate of the PMOS 105 and simultaneously to the source of the PMOS 107. At this time, the input signal C controls the switching of the ON or OFF state of the PMOS 105.

An inverted input signal C of C obtained by inverting the input signal C via the inverter 121 is input to the gate of the NMOS 106 and at the same time to the drain of the NMOS 108. At this time, the inverted input signal C of C is NMO.
It controls the switching of the on or off state of S106. The input signal B is input to the gates of the PMOS 103 and the NMOS 104, and at the same time, is input to the node 140. At this time, the switching of the ON or OFF state of the PMOS 103 and the NMOS 104 is controlled. Input signal B is at node 14
After being inputted to 0, it is inputted to the node 141 after passing through the PMOS 101 or the NMOS 102 which is turned on by the input signal A or A. After that, the input signal B passes through the PMOS 105 or the NMOS 106 which is turned on by the input signal C or C,
It is input to the CMOS inverter 122. The SUM signal is an output signal of the CMOS inverter 122.

In the second block 131, the input signal A is input to the gates of the PMOSs 110 and 113 and the NMOSs 115 and 116, and these PMOSs 110 and 113 are input.
And 113 and the switching of the on / off states of the NMOSs 115 and 116. Input signal B is PMOS
It is input to the gates of 109 and the NMOS 117, and controls switching of the PMOS 109 and the NMOS 117 between on and off states. The input signal C is the PMOS 11
1 and 112, input to the gates of NMOS 114 and 118, and these PMOS 111 and 112, NM
It is responsible for switching the OS 114 and 118 between ON and OFF states. In the block 131, the CMOS inverter 123 is set to the H level or the L level from the power supply or the ground through the nodes passing through the PMOS or the NMOS turned on by the input signals A, B, and C.
The level signal is input. Carry signal is this CMO
This is the output signal of the S inverter 123.

[0006]

In the block 30 which is a circuit for outputting the SUM signal of the full adder circuit shown in FIG. 2, the number of elements for logic generation is determined by the CMOS inverter 122 at the output stage. Since it is excluded, it has 8 transistors. Similarly, in the block 31 which is a circuit for outputting a carry signal,
The number of elements for generating logic is the CMOS of the output stage.
Since the inverter 123 is removed, the number of transistors is 10. The number of these elements is the smallest as compared with other conventional full adder circuits. To achieve higher speed or lower power consumption, it is necessary to further reduce the number of elements. However, if the circuit is not a circuit that takes out the inverted output of the SUM signal or the carry signal, it is very difficult in terms of logic generation to further reduce the number of elements. When the number of elements is increased, it is possible to reduce power consumption, but it is difficult to increase the speed together with this.

In view of the above problems, the present invention is a full adder circuit for realizing high speed and low power consumption without reducing the number of elements for logic generation of a circuit block for outputting a SUM signal. Is provided.

[0008]

In order to solve the above problems, in the present invention, the number of elements for logic generation in the circuit block for outputting the SUM signal is
Although eight transistors are used, the pass gate logic is generated by using only the NMOS, which has a smaller propagation delay time than the PMOS. Further, a CMOS inverter is used in the output stage to drive the current of the SUM signal. The circuit block for outputting the carry signal is S
Considering the balance of the current driving force with the block that is the circuit for outputting the UM signal, the complementary pass gate logic configuration is used in which both PMOS and NMOS are used.

[0009]

According to the present invention, with the above-described configuration, the NMOS circuit is constructed with the same number of elements as the conventional circuit.
It is possible to speed up the output of the SUM signal by configuring the pass gate logic using only the SUM signal.

When a full adder is used to form an adder or a multiplier, the carry signal is propagated to the next full adder due to its nature, so that a carry current larger than that of the SUM signal is used. Driving force is required. Therefore, regarding the circuit block for outputting the carry signal, PM
It is composed of a complementary pass gate logic that uses both OS and NMOS to secure the current driving force.

By using the NMOS in the block, which is a circuit for outputting the SUM signal, high speed is realized,
On the other hand, in the circuit block for outputting the carry signal, the current driving force is secured, so that the propagation delay due to the parasitic capacitance in the carry signal transmission path or the input capacitance of the full adder in the next stage can be prevented, so that it is low. The power consumption can be realized, and the full adder as a whole can achieve both high speed and low power consumption.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram showing a full adder circuit according to an embodiment of the present invention.

Referring to FIG. 1, a full adder according to the present invention includes a CMOS inverter 19 for generating input signals A, B and C, an inverted input signal of the input signal A, and a CMOS inverter for generating an inverted input signal of the input signal B. It is composed of an inverter 20, a CMOS inverter 21 for producing an inverted input signal of the input signal C, a first block 30, and a second block 31.

Further, the first block 30 is an NMOS.
1 to 8 and a CMOS inverter 22.
Reference numeral 40 denotes a node to which the drain of the NMOS1, the source of the NMOS2, the source of the NMOS5 and the drain of the NMOS8 are connected, and 41 is a node to which the drain of the NMOS2 and the source of the NMOS3 are connected.
Is the drain of NMOS3, the source of NMOS4, NM
This is a node to which the drain of OS6 and the source of NMOS7 are connected.

The second block 31 includes PMOSs 9 to 1
3, N-channel MOS transistors 14-18 and CM
It is composed of the OS inverter 23. However, in FIG. 1, all NMOs that make up the first block 30 are
The gate width and gate length of S and all the NMOSs forming the second block 31 are the same, and the second block 3
The gate widths and gate lengths of all the PMOSs that form 1 are first set to 1.5 times the gate widths of the NMOSs that form the first block 30 and the second block 31, and the gate lengths Is the same as the gate length of the NMOS forming the first block 30 and the second block 31.

The operation of the full adder configured as above will be described below. In the first block 30, the input signal A is input to the gates of the NMOSs 1 and 3, and controls the switching of the NMOSs 1 and 3 between ON and OFF states.
The inverted input signal A of A inverted via 9 is the NMOS
It is inputted to the gates of 2 and 4 and controls the ON or OFF state of these NMOSs 2 and 4. Input signal B
Is input to the node 41 and the input signal B is CMO.
Inverted input signal B of B inverted via S inverter 20
The input is input to the source of the NMOS1 and the drain of the NMOS4.

The input signal C is input to the gates of the NMOSs 6 and 8, and controls the ON / OFF state of the NMOSs 6 and 8, and the inverted input signal C of the input signal C inverted by the CMOS inverter 21. Is N
Input to the gates of MOS5 and MOS7, these NMOS
It is responsible for switching the on and off states of 5 and 7. The input signal B is input to the node 41 and then propagated to the node 42 or the node 40 by the input signal A or A-through the NMOS 3 or 2 which is turned on, and then the input signal C-or The CMOS is turned on via the NMOS 7 or 8 which is turned on by C.
It is input to the inverter 22. The SUM signal is an output signal of the CMOS inverter 22.

On the other hand, in the second block 31, the input signal A is input to the gates of the NMOSs 15 and 16 of the PMOSs 10 and 13, and controls the switching of the PMOSs 10 and 13 and the NMOSs 15 and 16 to the on or off state. The input signal B is PMOS 9 and N
It is input to the gate of the MOS 17 and controls the ON / OFF state of the PMOS 9 and the NMOS 17. The input signal C is PMOS 11 and 12, NMOS
Input to the gates of 14 and 18 and these PMOS1
It controls the switching of the ON and OFF states of 1 and 12 and NMOS 14 and 18. In the block 31, an H level signal or an L level signal is input from the power supply or the ground to the CMOS inverter 23 via each node passing through the PMOS or NMOS turned on by the input signals A, B and C. . The carry signal is an output signal of the CMOS inverter 23.

A truth table showing the operation of the full adder according to the present invention is shown in (Table 1).

[0021]

[Table 1]

As described above, according to the present embodiment, as shown in FIG. 1, in the block 30 which is a circuit for outputting the SUM signal, the number of elements for logic generation is the one excluding the inverter 22. Therefore, it has 8 transistors. This is a block 1 which is a circuit for outputting the SUM signal in FIG. 2 shown as a conventional example.
Although the number of elements for logic generation in 30 is the same, the logic generation of the block 30 in this embodiment is
Since the pass gate logic using only the NMOS is used, the PMOS and the NMOS are used together.
The signal propagation delay time is shorter than that of the block 130 shown in (1), and higher speed can be realized.

On the other hand, in the block 31 which is a circuit for outputting a carry signal, it is important to shorten the signal propagation delay time in the block, but the carry signal to be the input signal to the full adder in the next stage is important. Considering the characteristics, it is more important to secure the current driving force. Therefore, as shown in FIG.
PMO instead of pass gate logic using only MOS
By using a complementary pass gate logic of 10 transistors in which S and NMOS are used together, waveform deterioration of the carry signal is prevented and low power consumption is realized.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit diagram of a full adder circuit showing a second embodiment of the present invention. The configuration of this embodiment is the same as that of FIG. 1 showing the first embodiment, but is different from FIG. 1 in the points described below. As for the NMOS, the gate widths of all the NMOSs forming the first block 230 are equal to those of the NMOSs forming the second block 231.
The point is to increase the gate width from 1.6 times to twice.

The gate lengths of all the NMOSs forming the first block 230, the gate lengths of all the NMOSs forming the second block, and the second block 2
The gate lengths of all the PMOSs forming 31 are the same, and all the PMOSs forming the second block 231 are
The gate width of is equal to 1.5 times that of all the NMOSs forming the second block 231.

The operation of the full adder circuit configured as described above is the same as that of the full adder circuit of the first embodiment.
Block 230, which is a circuit for outputting a SUM signal
By increasing the gate width of the NMOS from 1.6 times to 2 times, it is possible to further speed up the full adder circuit of the first embodiment, which is faster than the conventional full adder circuit.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a circuit diagram of a full adder circuit showing a third embodiment of the present invention. The configuration of this embodiment is the same as that of FIG. 1 showing the first embodiment, but is different from FIG. 1 in the points described below. It is the second regarding NMOS
Of the gate widths of all the NMOSs that form the block 331 of FIG.
The point is to increase the gate width of S from 1.6 to 2 times.

The gate lengths of all NMOSs forming the first block 330, the gate lengths of all NMOSs forming the second block 331, and the gate lengths of all PMOSs forming the second block 331. Are the same, and all PMs configuring the second block 331 are
The gate width of the OS is 1.5 times that of all NMOSs included in the first block 330.

The operation of the full adder circuit configured as described above is the same as that of the full adder circuit of the first embodiment,
Block 33 which is a circuit for outputting a carry signal
By increasing the gate width of the NMOS of 1 from 1.6 times to 2 times, it is possible to further reduce the power consumption as compared with the full addition circuit of the first embodiment, which has lower power consumption than the conventional full addition circuit. Become.

A conventional example, a first example, a second example, and a third example by a circuit simulation using HSPICE.
The values of the propagation delay time and the power consumption of the circuit in this embodiment are shown in (Table 2). The simulation conditions are a power supply voltage of 3 V, the NMOS ratio of the blocks 230 and 231 is 1.6 in the second embodiment, and the NMOS ratios of the blocks 330 and 331 are the third embodiment.
The ratio is 1.6.

[0033]

[Table 2]

[0034]

As described above, according to the present invention, in the block which is the circuit for outputting the SUM signal, the pass gate logic is generated by using only the NMOS and the propagation delay time is smaller than that of the PMOS, and the carry signal is generated. In consideration of the balance of current driving force with the block which is a circuit for outputting the SUM signal, the circuit block for outputting It is possible to realize both low power consumption and low power consumption. Considering the performance of the full adder as the product of the propagation delay time and power consumption of the entire circuit, changing the transistor size within an appropriate range changes the balance between high speed and low power consumption. Therefore, it is possible to easily realize three variations of a high speed type and a low power consumption type, that is, a balanced match type, a high speed type and a low power consumption type.

Regarding the balance between high speed and low power consumption, FIG. 6 shows the relationship between transistor size, propagation delay time and power consumption, and FIG. 7 shows transistor size, propagation delay time and power consumption of the entire circuit. The product relation of is shown. In FIG. 7, a range indicated by 500 represents a range of suitable transistor sizes having high speed and low power consumption in the present invention.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a full adder circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional full adder circuit.

FIG. 3 is a circuit diagram of a full adder circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a full adder circuit according to a third embodiment of the present invention.

FIG. 5 is a diagram showing the relationship between the transistor size, the propagation delay time, and the power consumption of the full adder circuits of the first, second, third, and conventional examples of the present invention.

FIG. 6 is a diagram showing the relationship between the transistor size of the full adder circuit according to the first embodiment, the second embodiment, and the third embodiment of the present invention, and the product of the propagation delay time and the power consumption.

[Explanation of symbols]

 1-8 NMOS 9-13 PMOS 14-18 NMOS 19-23 CMOS inverter 24 power supply 25 ground 30 SUM signal generation block 31 carry signal generation block

Claims (3)

[Claims] 1. An exclusive OR of the first and second input signals is output upon receiving a first input signal and a second input signal, N
A first exclusive-OR circuit composed of channel MOS transistors, an output signal of the first exclusive-OR circuit, an inverted output signal of the first exclusive-OR circuit, and a third input signal A second exclusive OR composed of an N-channel MOS transistor and a CMOS inverter that receives and outputs an exclusive OR or exclusive NOT of the output signal of the exclusive OR circuit and the third input signal. A circuit, a first AND circuit that receives the first input signal and the second input signal and outputs a logical product of the first and second input signals, and the second input signal A second AND circuit that receives the third input signal and outputs a logical product of the second and third input signals; and a second AND circuit that receives the third input signal and the first input signal Third and first
A logical product of the input signals of the third logical product circuit, an output signal of the first logical product circuit, an output signal of the second logical product circuit, and an output signal of the third logical product circuit. And a logical sum circuit that outputs a logical sum of the output signals of the first, second, and third logical product circuits.
The first AND circuit, the second AND circuit, the third AND circuit, and the OR circuit are configured by using P-channel MOS transistors, N-channel MOS transistors, and CMOS inverters. Characteristic full adder circuit. 2. A gate width of an N-channel MOS transistor forming a first exclusive-OR circuit and a gate width of an N-channel MOS transistor forming a second exclusive-OR circuit are set to a first AND circuit and a second AND circuit. N-channel MOS forming the AND circuit, the third AND circuit, and the OR circuit
The full adder circuit according to claim 1, wherein the gate width of the transistor is 1.6 to 2 times. 3. A gate width of an N-channel MOS transistor forming the first AND circuit, the second AND circuit, the third AND circuit, and the OR circuit is set to the first exclusive OR circuit. 2. The gate width of the N-channel MOS transistor that constitutes the N-channel MOS transistor and the N-channel MOS transistor that constitutes the second exclusive OR circuit is 1.6 to 2 times as large as that of the N-channel MOS transistor.
Full adder circuit described.